Division Of - NTU EEE · 2018. 5. 9. · C. Ultra-low Power Subthreshold SRAM Design The objective of this research is to design and implement SRAMs for emerging ultra-low power/energy

The year 2010 marks an important milestone for the division. VIRTUS, a jointly-funded centre by Nanyang Technological University (NTU) and the Singapore Economic Development Board (EDB), was officially opened on 20 October 2010 by Mr S. Iswaran, the Senior Minister of State for Trade & Industry and Education. VIRTUS aims to be a world-class integrated circuits (ICs) design centre, developing key technologies required to design ICs and systems for applications in medical technology, clean technology and consumer electronics.

Seven top American, European and Chinese Universities have signed memoranda of understanding (MOU) with VIRTUS to collaborate in joint research in IC design. These seven Universities are the University of Michigan; Purdue University; University of California, Los Angeles, or UCLA; Technical University Munich; Linköping University; Zhejiang University; and Fudan University. Besides academic collaborations, VIRTUS has also forged close partnerships with leading industry players including Mediatek, Agilent Technologies, Verigy, SiliconCore Technology, United Microelectronics Corporation, Infineon, Broadcom Corporation and the Institute of Microelectronics. VIRTUS will continue to establish joint collaboration with world renowned universities, top research institutions and well-known companies in its pursuit of excellence in research and development in IC design and technology.

The division welcomes two new faculty members, Dr Natalie Kong Zhi Hui and Dr Arindam Basu. Natalie, our own PhD graduate, is an outstanding researcher in Green Electronics. Her co-invention of a super-chip that consumes thirty times less energy while operating seven times faster than contemporary designs based on state-of-the-art CMOS technology has attracted worldwide media attention. Basu, who has received his PhD degree from Georgia Institute of Technology, is a young and promising researcher in low-power VLSI design. Both of them add both depth and diversity in IC research activities in the division.

The faculty members in the division continue to do very well in bringing in external research grants. One of them that worth mentioning is the research project, “Rapid Design Verification Platform for Analog/RF Circuits Beyond the Scale of 65nm and 60GHz”, led by one of our junior faculty members, Prof Yu Hao. It secured $250,000 from National Research Foundation (NRF) under the highly competitive Proof of Concept (POC) Grant Call. This project is to develop a software tool to support integrated circuit (IC) design beyond the scale of 60GHz and 65nm. New simulation algorithms and device models will be developed to not only reduce the verification time but also to provide the accurate high-frequency model. The developed software tool can significantly reduce the design cycle and cost for the designs at the existing scale. More importantly, it can also be used for the emerging IC market of high data-rate (Giga-bit/second) wireless-links at the new scale of 60GHz and 65nm, which are critical components for 3D and high-definition (HD) multimedia electronics.

The research contribution by our faculty members has also gained international standing. Prof Zhang Yue Ping is elevated to the Fellow Grade of the Institute of Electrical and Electronics Engineers (IEEE). The IEEE Fellowship is highly regarded by the international engineering community as a prestigious honour that recognises individuals with an extraordinary record of accomplishments in any of the IEEE

Division Of Circuits And SystemsSchool of Electrical & Electronic Engineering

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Introduction

The Integrated Electronics Research Cluster consists of five laboratories, namely, IC Design I, IC Design II, VLSI, Integrated System Research, and Electronic Systems Measurements. All laboratories are well equipped with high-end PCs and networked to share a wide range of Linux-based and Window-based EDA tools, e.g. Cadence, Mentor Graphics, Agilent Technologies, Ansys, Synopsys, etc. for design and analysis of devices, circuits and systems. General test and measurement equipment such as digitizing scopes, function generators, signal generators, and spectrum analyzers, etc. are facilitated in IC Design II, Integrated System Research, and Electronic Systems Measurements laboratories. The IC design II laboratory also houses a High Frequency Characterization Room that is equipped with a Cascade 8” Probe System and an Integrated Characterization and Analysis System. This is to facilitate on-wafer S parameter RF device characterization from 50MHz to 50GHz, high frequency noise measurement from 0.3GHz to 26.5GHz and flicker noise measurement up to 100 KHz. The Integrated System Research laboratory also houses the acoustic sound room with specialized equipment for audio testing. The Electronic Systems Measurements laboratory also houses a GTEM (Gigahertz Transverse Electromagnetic) Cell for electromagnetic radiation susceptibility measurement.

fields of interest. Prof Zhang is cited for his contributions to integrated antennas and subsurface radio. Our Deputy Head, Prof See Kye Yak, has also been appointed by the Board of Directors of the IEEE Electromagnetic Compatibility (EMC) Society as the Technical Editor of the IEEE EMC Society Newsletters. Prof See has been selected for the appointment for his research expertise in EMC and active service contribution to the society.

The research work produced by our faculty members is also well recognized for their quality. Prof Lim Meng Hiot is honored with the Best Paper Award by 24th European Conference on Modelling and Simulation and one of Prof Yu Hao’s papers is awarded the 2010 best paper award by ACM Transactions on Design Automation of Electronic Systems. Besides our faculty members, our PhD student, Mr Lan Jingjing, supervised by Prof Goh Wang Ling and Prof Kong Zhi Hui, Natalie, is awarded with the Best Paper Award by 2010 International SoC Design Conference (ISOCC) in Seoul, while another PhD student, Mr Lu Yang, supervised by Prof Yeo Kiat Seng, is honored with the Best Paper Award by 2010 International Conference on High-Speed Circuits Design in Taiwan. In addition, another two of our PhD students, Mr Li Fei and Mr Mathias Faust, supervised by Prof Chang Chip Hong, has also clinched Gold and Silver Leaf Certificates Awards, respectively, at the Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics 2010. The Gold and Silver Leaf Certificates are awarded to the articles that demonstrated high quality research that are ranked amongst the top 10% of the presented papers.

Integrated Electronics Research Cluster


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A. Programmable Analog Electronics

The research activities of the Integrated Electronics Research Cluster are focused in the area of IC design in the first 4 laboratories, where activities in high frequency mixed signal and RF design are focused in IC Design I and II laboratories, design of digital systems is focused in the VLSI laboratory, and design of advanced audio systems is specialized in the Integrated System Research laboratory. For the Electronic Systems Measurements laboratory, the major research activities are in Electromagnetic Interference (EMI), Electromagnetic Compatibility (EMC), IC and opto-electronic components reliability and energy harvesting. The highlights of 2010 activities are as follows

Figure 1: Programmable analog circuits(a) die-photo, (b) block diagram and (c) test setup for the FPAA chip.

We have developed reconfigurable analog electronic circuits called Field Programmable Analog Array or FPAA which can be considered the dual of its well-known digital counterpart, Field Programmable Gate Array or FPGA. Similar to the FPGA, it has a set of computational “analog” blocks (CAB) located within a reconfigurable switch matrix. However, unlike traditional designs, our reconfigurable switches are made of floating-gate (FG) transistors which are similar to flash memory cells. The conductivity of these switches is governed by the charge on the floating-gate which can be controlled by the quantum mechanical processes of hot-electron injection and electron tunneling. Also, unlike traditional digital flash memory, we can control the charge on the gate in an analog way, thus making these FG devices useful for computation and not only as passive switches. Modifying the elements in the CAB allows us to have programmable chips for different applications. For example, the chip for analog signal processing has transconductance amplifiers, voltage buffers, Gilbert multipliers, transistors, multi-input translinear elements (useful in current mode circuits), capacitors, transistors etc. All of the elements have programmable parameters (like bias current, offset) with the programmability also being provided by FG devices. We have demonstrated the use of these circuits for audio processing, AM baseband circuits etc. For details, refer to A. Basu et. al., “A Floating gate based FPAA” IEEE JSSC, vol. 45, no. 9, pp. 1781-94, 2010. This work is being done in collaboration with Georgia Institute of Technology.


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Research Highlights

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B. Motion Detection Image Sensor with on-chip Object Localization

Fast-motion object detection and localization is important to a number of applications including surveillance, security monitoring and road traffic enforcement. These applications require continuous image acquisition and processing in real time. With the increasing demand on image quality as well as video speed, conventional cameras which have no or little computing capabilities fall short of meeting the requirements. Massive quantities of primitive, unimportant image data have to be transmitted and processed before the features of interest are obtained. To make things worse, some systems require multiple sensors to cover a large surveillance area and different view angles, together with the need of higher speed video (>100 f/s).

With the above considerations in mind, we proposed a 64x64 pixels temporal difference image sensor with on-chip object localization processing. The sensor compares two consecutive image frames and outputs those pixels with illumination change larger than predefined threshold. This will filter the background information and only report the active contour of the motion objects in the scene. The contour pixels are processed on-the-fly-by-cluster-based object localization circuits. The bounding box of the largest object is obtained and the sensor will autonomously switch to analog mode and zoom to the window of that object. The proposed algorithm can discard noisy clusters and at the same time merge small clusters if they grow and get close to each other.

Figure 2(a) Image sensor testing board stacked on an Opal-Kelly FPGA board (b) image sensor layout(c) simulation result which shows the active cluster


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C. Ultra-low Power Subthreshold SRAM Design

The objective of this research is to design and implement SRAMs for emerging ultra-low power/energy applications. Subthreshold circuits are attracting more interest than ever due to various energy-efficient applications such as wireless sensor nodes, implantable biomedical devices, and mobile electronics. The primary design requirement of them is the minimum energy consumption for the maximum battery lifetime that can be achieved by operation in the subthreshold region. However, the subthreshold circuits encounter many design issues such as low noise margin, high sensitivity to Process-Voltage-Temperature (PVT) variations, and small Ion-to-Ioff ratio. While digital circuits show acceptable robustness in the subthreshold region, design of subthreshold SRAMs is even more challenging due to additional design constraints. The main challenges include small margin in cell stability, write ability, bitline swing, and exponentially increased variations in performance and power.

To address the above issues, the research team has developed two SRAMs that have demonstrated successful operation in the subthreshold region. The SRAM chips were fabricated in a 130nm CMOS technology. The first SRAM test chip is equipped with circuit techniques such a novel 10T SRAM cell with data-independent bitline leakage and virtual-ground replica scheme. The proposed data-independent bitline leakage concept enables 1k cells to be attached to a bitline with the supply voltage of 0.2V, which is the largest number of cells per bitline in subthreshold SRAMs ever published. The second SRAM chip used an 8T SRAM cell to reduce the area overhead. The research team also developed circuit techniques such as marginal bitline leakage compensation, and a deep sleep mode for lowering minimum operating supply voltage and reducing leakage power consumption. The test chip showed successful SRAM operation at the supply level of 0.26V with 512 cells per bitline. While the conventional sleep mode cannot be used in subthreshold SRAMs, the proposed deep sleep mode realizes a sleep mode even in the subthreshold SRAMs. The proposed deep sleep mode reduced the leakage by 69%. The research works were presented in IEEE International Solid-State Circuits Conference (ISSCC) and IEEE Custom Integrated Circuits Conference (CICC), and were published in IEEE Journal of Solid-State Circuits (JSSC).

Figure 3: A 0.2V, 480kb 10T SRAM with 1k cellsper bitline for ultra-low-voltage computing.

Figure 4: A 0.26V, 64kb 8T SRAM with Vmin lowering techniquesand deep sleep mode.


The VIRTUS is an IC Design Centre of Excellence jointly funded by NTU and EDB to advance discovery and design (D&D) as well as research and development (R&D) in IC design and technology. The opening of VIRTUS on 20th October 2010 with more than 250 guests from the industry and the institutes of higher learning was graced by the Senior Minister of State for Trade & Industry and Education, Mr S Iswaran. With its door now opened, it will develop key technologies required to design integrated circuits and systems for applications in medical technology, clean technology and consumer electronics. The centre’s research activities can be broadly divided into the following major areas, namely sensors; analog, mixed-signal, power management and data converters; low-power and energy harvesting; RF and mm-wave IC’s; and new technology directions such as 3D-integration and physical design, 3D RF and mixed-signal circuits, and terahertz IC.

VIRTUS, IC Design Centre of Excellence

The sensors research group focuses on designing mixed signal VLSI circuits for low power smart sensor and integrating the sensors into systems. Recent achievements include the following.

Sensors

A. Dynamic resolution smart vision sensor

The objective of this project is to design a smart image sensor that can localize and automatically focus to the motion object. This project is lead by Asst Prof. Chen Shoushun. Fast-motion object detection and localization is important to a number of applications including surveillance, security monitoring and road traffic enforcement. These applications require continuous image acquisition and processing in realtime. With the increasing demand on image quality as well as video speed, conventional cameras with no or little computing capabilities, fall short of meeting the requirements. Massive quantities of primitive, unimportant image data have to be transmitted and processed before the features of interest are obtained. To make things worse, some systems require multiple sensors to cover a large surveillance area and different view angles, together with the need of higher speed video (>100 f/s).

With the above considerations in mind, the team has developed a mixed-signal 64x64 pixels temporal difference image sensor with on-chip object localization. The sensor compares two consecutive image frames and outputs those pixels with illumination change larger than predefined threshold. This will filter the background information and only report the active contour of the motion objects in the scene. The contour pixels are then processed on-the-fly-by-cluster-based object localization circuits. The bounding box of the largest object is obtained and the sensor will then autonomously switch to analog mode and zoom to the window of that object. The proposed algorithm can discard noisy clusters and at the same time merge small clusters if they grow and get close to each other. The sensor was implemented using UMC 0.18μm CMOS technology and features a 64x64 resolution, 150 frames/s and 0.5mW power consumption.


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Image sensor layout, (b-d) shows the on-chip object localization flow.detects the motion eventsthe size and position of the motion object is localizedthe sensor switches to analog mode and auto-focuses to the window of the object.

B. Integrated Sensing and Processing

Today, many sensory applications need thousands of sensors operating in tandem. Brain machine interfaces, Intra vascular ultrasound and wireless sensor networks are a few examples. The high bandwidth of generated data combined with tight power constraints make it virtually impossible to engineer such systems with a central processing unit. Hence, the trend has been to move towards “smart” sensors – sensors with an integrated capability for processing data as well. Since stringent power dissipation requirements often preclude using an ADC at every sensor, analog processing techniques have been used in many such cases. However, developing such smart systems is very time consuming, especially if the sensor design itself is in flux, since a typical ASIC design cycle takes several months and a new ASIC may be needed for the new sensor design.

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Figure 6: Figure demonstrates(a) conceptual block diagram and(b) die-photo of the reconfigurable smart sensor chip.

Figure 5(a)(b)(c) (d)

Hence, a reconfigurable “smart” sensor is being developed in collaboration with Georgia Institute of Technology. The lead investigator of this project is Asst. Prof. Arindam Basu. Based on the concept of field programmable analog arrays, this chip will be very useful for rapid prototyping of different sensors. Figure 6(a) depicts the conceptual block diagram – the system comprises low-noise circuits for sensing charge, capacitance, current or voltage. Using reconfigurable interconnect, the sensed signal can be processed using programmable analog circuits like Gilbert multipliers, filters, transconductors, translinear processors etc. The programmability of the circuit parameters and the reconfiguration of the topology is done using floating-gate (FG) transistors whose threshold is programmable using quantum mechanical processes of electron injection and tunneling. Built-in 0.35 μm CMOS, the 3mm X 3mm chip can program 9-bit accurate FG bias currents in 20 ms and a row of FG switches in 1 ms. The power consumption can be traded-off with noise or bandwidth requirements. The die photo of the chip is shown in Fig. 6(b).

C. Aging and process variation sensors for memory

Asst. Prof. Kim Tae Hyoung’s group is working on aging and process variation sensors for memory applications. The sensors will measure the circuit aging and the initial process variation, and will automatically control various parameters to maintain the requirements.

Following an aggressive device scaling trend, circuit reliability and variability are becoming ever more challenging issues. Reliability issues include bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). They are becoming more and more significant as the device scaling increases the electric field, especially in nanoscale technologies. Device variability caused by random dopant fluctuation (RDF) makes circuits deviate from the original design. This is exacerbated with device scaling. Memory circuits are particularly impacted by device variability since most of the devices are minimum-sized or close to the minimum size. To tackle the above issues, the team has developed sensing circuits for measuring frequency degradation coming from negative bias temperature instability (NBTI).

The main objective of this research is to provide design solutions for various systems, from high-performance applications where power consumption limits performance to battery-powered applications where energy efficiency is the primary design constraint. Faculty members involve in this work include Asst Prof. Tony Kim Tae Hyoung and Asst/Prof. Natalie Kong Zhi Hui.

In advanced CMOS process technologies, power consumption is one of the most challenging issues to be tackled for better performance and system reliability. Power consumption is a key limiting factor not only in high-performance applications but also in recently emerging ultra-low power applications where performance is compromised with energy efficiency for increasing

Low Power Integrated Circuits (IC) Design


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battery lifetime. The research group has developed various design techniques for low power applications. They include sub-threshold SRAMs, sub-threshold circuit optimization, and probabilistic CMOS (PCMOS) design. The research works were presented and published in premier IEEE conferences and journals such as International Solid-State Circuits Conference (ISSCC), IEEE Custom Integrated Circuits Conference (CICC), and IEEE Journal of Solid-State Circuits (JSSC). Recently, 3D ICs have attracted more and more interests as a momentum for continuing the Moore’s law. By stacking multiple chips, 3D ICs have smaller footprint, shorter interconnection lengths, and accordingly higher performance. However, 3D ICs consume more power per area and generate more heat, which is a significant issue in system reliability. Consequently, low power techniques are also essential for the reliable 3D IC design. To provide circuit solutions for the above issues, we are currently conducting research on the following topics:

(i) ultra-low voltage circuits design,(ii) low power memories design, and(iii) low power circuit techniques for 3D ICs.

In ultra-low voltage circuits design, sub-threshold of near-threshold circuits design has been investigated since they are crucial in many applications where batteries and energy harvesting devices have been used as a main power source. Minimum energy consumption can be achieved when supply voltage is lowered to or below the device threshold voltage where we are aiming at reliable circuit design. However, ultra-low voltage operation generates higher sensitivity to process-voltage-temperature (PVT) variations. One of the on-going projects is to design a sub-threshold base-band processor with variation tolerance. In this project, we will develop circuit techniques for mitigating the impact of process variations on circuit operation.

The second research topic is low power memories design. Since memory is one of the major power and energy consuming blocks, low power memory design is fundamental in numerous low power applications. Currently, we are conducting research on four different projects:

(a) sub-threshold SRAMs for enhanced cell stability,(b) logic-compatible embedded DRAMs,(c) CMOS-compatible resistive RAM (ReRAM), and(d) NEMS-based memory design for rugged electronics. We are collaborating with a research group in the Division of Microelectronics for the ReRAM project, and Institute of MicroElectronics (IME) for the NEMS-based memory design project.

Finally, the major performance impact that is offered by 3D integration is the possibility of reduced interconnect length due to the availability of a third dimension in which active devices can be placed. Nonetheless, the Through-Silicon Via (TSV) technique used to realize 3DIC may incur additional problems such as a thermal issue, interconnection reliability, and interconnection density. In this topic, we are working on high speed serial links for 3D interconnect, which aims to reduce power consumption and the area overhead of TSV, and improve interconnection reliability. Both wired and wireless serial links will be developed. We will also examine the thermal characteristics of a 3D IC, methods that could be done to circumvent the harmful effects related to this, and methods used for floor planning and place/route in a 3D scenario.


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The sensors research group focuses on designing mixed signal VLSI circuits for low power smart sensor and integrating the sensors into systems. Recent achievements of the RF research include the following.

RF and mm-Wave IC Design

A. Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

The high speed dual modulus prescaler is a critical functional block in frequency synthesizers which uses wide-band pulse swallow frequency dividers. The prescaler operates at the highest frequencies and consumes more power than other circuit blocks of the frequency synthesizer. In a pulse swallow frequency divider, the prescaler has two selectable division ratios, N and N+1. It is combined with programmable counters P and S to perform a programmable division ratio of (N×P+S). The prescaler is a synchronous circuit which is formed by D flip-flops and additional logic gates. Due to the incorporation of additional logic gates between the flip-flops to achieve the two different division ratios, the speed of the prescaler is affected and the switching power increases. Various flip-flops have been proposed to improve the operating speed of dual-modulus prescalers. The optimization of the D flip-flop in the synchronous stage is essential to increase the operating frequency and reduce the power consumption. High speed operation of MOS transistors is limited by their low transconductance. Therefore, dynamic and sequential circuit techniques or clocked logic gates such as true single phase clocks must be used in designing synchronous circuits to reduce circuit complexity, to increase operating speed, and reduce power dissipation.

The low power research group is collaborating with the Institute of Microelectronics (IME) for the projects of NEMS-based memory design for rugged electronics and ultra-low voltage circuit design, and MediaTek for the development of sub-threshold SRAMs for micro-watt applications. We also have several proposals pending for approval that will boost the quality of our research.

Figure 7: A 9T SRAM cell with data-independent bitlineleakage for improved read bitline swing

Figure 8: A simultaneous bidirectional transceiver usingcapacitive coupling.



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B. Miniaturization of Planar Monopole Antenna for Ultra-wideband Radios

Ultra-wideband (UWB) radio has drawn considerable attention recently. Significant progress has been made in its implementation and application. Two distinct schemes are currently under development. One features orthogonal frequency division multiplexing (OFDM) and the other direct sequence (DS) technique. In the OFDM-UWB scheme, a sub-band with 128 OFDM carriers occupies 528 MHz band, and different sub-bands are selected from time to time to achieve the frequency hopping; while in the DS-UWB scheme, only two sub-bands are used to avoid IEEE 802.11a, i.e., the mandatory low band with 2.05 GHz bandwidth and the optional high band with 4.775 GHz bandwidth. Unlike most UWB radio devices today are implemented in silicon

germanium (SiGe) technology, a single-chip solution of UWB radio has also been successfully demonstrated in complementary metal oxide semiconductor (CMOS) technology. With the characteristics of low power, low cost, and very high rates at limited range, UWB radio is positioned to address the applications for wireless personal area networks.

The research team has demonstrated through simulations that a 40% reduction in size can be realized by simply exploiting its structural symmetry. We find that the miniaturized beveled planar monopole antenna exhibits wider impedance bandwidth, higher cross-polar radiation, and slightly lower gain at higher frequencies as compared with its un-miniaturized counterpart. The miniaturization is described of a beveled planar monopole antenna in low temperature cofired ceramic technology for integration with ultra-wideband radios. We confirm the miniaturization with the measurements of both un-miniaturized and miniaturized beveled monopole antennas. The miniaturized beveled monopole antenna of size 17 × 10 × 1 mm3 has achieved impedance bandwidth of 8.25 GHz from 2.85 to 11.1 GHz, gain from -5.6 to 2.3 dBi, and broad patterns. Both frequency domain and time domain characteristics of the beveled monopole antennas are also carefully investigated with a normalized measured transfer function. This work has appeared in the IEEE Transactions of Antennas and Propagation, July 2010.

The team has studied the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Global Foundries 0.18 m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW. Details on this work can be found in the IEEE Transactions of Circuits and Systems-I, Jan 2010.

Figure 10: Fabricated beveled monopole antenna for UWB radio:(a) un-miniaturized and(b) miniaturized.

This project is in collaboration with A*STAR Institute of Microelectronics (IME). The project is lead by Assoc. Prof. Goh Wang Ling. The objective is to develop ultra-low-power, low noise neural recording amplifiers, ADCs, and multiplexing architectures to interface with large-scale neural probe array. The developed analog-mixed signal circuits will be integrated into a complete implantable wireless neural recording microsystem and have the system validated through thorough electrical testing and animal trials at subsequence stage.

Several challenges to be faced at the initial design stage are:(1) to have clear and large amplification for identification of spikes due to the weak neuron signal;(2) miniaturization of circuitry; and(3) low power consumption to avoid tissue damages.

In the proposed design, noise cancellation mechanism to minimize noise from the amplification system will be deployed. Using noise feedback, the noise can be suppressed and the signal can be constructive so as to improve on the signal to noise ratio. The Noise Efficiency Factor (NEF) is used as the parameter count for the tradeoff between power, noise performance, and bandwidth. An ideal bipolar single-transistor amplifier has an NEF of 1.0. All practical circuits have higher NEF. Based on Harrison’s calculation, 2.9 is the theoretical NEF limit for an amplifier with circuit topology constructed from MOS transistors, assuming current mirror ratio of unity. By using noise reduction technique, the research group is able to achieve a better trade off, attaining an NEF of 1.87 in simulation. The circuit is currently being fabricated and the simulation result will be confirmed soon with the measurement data.

Neural Interface IC

Figure 11Wireless Implantable Integrated Neural Recording Microsystem.

Technology Directions


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Wireless Implantable Neural Recording IC for Motor Prosthesis

Analog & Mixed Signal, and PowerManagement IC A. An Ultra Low Power ECG Acquisition and Monitoring ASIC System for WBAN Applications

Figure 12: (a) Demonstration of wireless body area network technique

Figure 12: (b) Transceiver Chip

A team leads by Asst. Prof. Zheng Yuanjin proposes a power and area efficient electrocardiogram (ECG) acquisition and signal processing application sensor node for wireless body area networks (WBAN). This sensor node can accurately record and detect the QRS peaks of ECG waveform with high frequency noise suppression. The proposed system is implemented in 0.18 μm CMOS technology with two chips: analog front end IC and digital ASIC, where the analog IC consumes only 79.6 μW with area of 4.25 mm2 and digital ASIC consumes 9µW @ 32 kHz with 1.2 mm2 . Therefore, this ECG sensor node is convenient for long-term monitoring of cardio-vascular condition of patients, and is very suitable for on-body WBAN applications.


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B. Floating-Gate-Based Field-Programmable Analog Array

Figure 13:Amplitude demodulation system implemented on the FPAA. It consists of a wide dynamic range Gilbert multiplier,Gm-C filter and a second order current mode delta sigma converter.

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) in 0.35-um CMOS has been proposed by Asst. Prof. A Basu. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (9 b of FG voltage) and speed (20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are also investigated.


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Head of DivisionYeo Kiat Seng, Professor

Arindam Basu, Assistant Professor

Boon Chirn Chye, Assistant Professor

Alper Cabuk, Teaching Fellow

Chan Pak Kwong, Associate Professor

Chang Chip Hong, Associate Professor

Chang, Joseph Sylvester, Associate Professor


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Staff Members

Staff Members

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Ho Duan Juat, Associate Professor

Jong Ching Chuen, Associate Professor

Kim Tae Hyoung, Assistant Professor

Kong Zhi Hui, Assistant Professor

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Chen Shoushun, Assistant Professor

Do Manh Anh, Professor

Goh Wang Ling, Associate Professor

Gwee Bah Hwee, Associate Professor


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Staff Members

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16 Yvonne Lam Ying Hung, Associate Professor

Lau Kim Teen, Associate Professor

Lim Meng Hiot, Associate Professor

Ng Lian Soon, Associate Professorr

Ong Keng Sian, Vincent, Senior Teaching Fellow

See Kye Yak, Associate Professor

Shi Xiaomeng, Teaching Fellow

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23 Siek Liter @ Hsueh Liter, Associate Professor

Tan Cher Ming, Associate Professor

Tan Meng Tong, Assistant Professor

Yu Hao, Assistant Professor

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27 Yu Yajun, Assistant Professor

Zhang Yue Ping, Associate Professor

Zheng Yuanjin, Assistant Professor


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Staff Members

Research Interest


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Boon Chirn Chye AssistantProfessor

[email protected]

Alper Cabuk [email protected]

Fellow

Chan Pak Kwong AssistantProfessor

[email protected]

Chang, Joseph Sylvester

AssistantProfessor

[email protected]

Do Manh Anh Professor [email protected]

Jong Ching ChuenAssociateProfessor

[email protected]

Gwee Bah Hwee AssociateProfessor

[email protected]

Chang Chip Hong [email protected]

Chen Shoushun [email protected] Professor

Goh Wang Ling [email protected]

Ho Duan Juat [email protected]

RFIC devices, Circuits and systems design, RFIC biomedical consumer electronic. 60GHz, 140GHz Transceiver Design.

RF IC design, High frequency clock & data recovery circuits, SONET systems

VLSI design, Digital filter design, Computer arithmetic, IP watermarking, Brain-inspired computing.

Mixed-signal smart vision sensors, Feature extracting biomimetic sensors for sensor networks, Energy-efficient algorithms for object recognition.

Wireless Telemetry IC Design, implantable neural recording IC, 3D IC for 100-GHz Application, Class D amplifiers, and FPGA-Based Investigation on Coding and Detection for Ultra-High Density Magnetic Recording.

Video coding, System level digital design,ASIC design.

Sensor circuits and systems, Analog/ mixed-signal IC design, Power management IC

Acoustics, audiology, electronics, IC design, Analogue and digital signal processing, Biomedical engineering, Pyschophysics.

R.F. circuits and systems, Mixed-signal IC design, Acoustics, Intelligent transport systems.

High-level synthesis, Parallel computation, Reconfigurable systems, Arithmetic circuits.

Subthreshold Low Power Asynchronous IC design, Dynamic Voltage Control System Design, Digital Class-D amplifier IC design, Acoustic noise reduction.

Arindam Basu [email protected]

Smart Sensors for Biomedical applications including BMI and Ultrasound ReconfigurableAnalog IC Computational Neuroscience Neuromorphic Engineering.

AssociateProfessor

Research Interest


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Kong Zhi HuiAssistantProfessor

[email protected]

Lau Kim Teen AssistantProfessor

[email protected]

Ng Lian Soon AssociateProfessor

[email protected]

See Kye Yak AssociateProfessor

[email protected]

Siek Liter AssociateProfessor

[email protected]

Lam Ying Hung, Yvonne

[email protected]

Lim Meng Hiot [email protected]

Ong Keng Sian, Vincent

[email protected]

TeachingFellow

Shi Xiaomeng [email protected]

Fellow

Ultra low-power, variation-aware, and high-performance memory and VLSI subsystem design; Three-dimensional (3D) IC design techniques using Through-Silicon-Via (TSV) technology; Green circuit, system, and architecture designs for healthcare applications, consumer electronics, and personal computers.

Low Power CMOS Design, Self-timed CMOS Circuits, Low Power Adiabatic Circuits, Subthreshold CMOS Circuits.

Analogue CMOS circuits, DAC/ADC, Micropower circuits, Analogue bipolar circuits.

Electromagnetic compatibility, Signal integrity and IC electromagnetic immunity.

Design of low-voltage low-power Bipolar, CMOS and BiCMOS Analog/Mixed-Signal ICs especially in the areas of Power Managementcircuits, PLLs and Data Converters.

Mixed-signal IC design, Analogue design automation.

Memetic Computation, Logistics and Mission Planning, Reconfigurable/Evolvable Circuits, Computational intelligence, Embedded systems, Financial Engineering, Fuzzy/neural hardware, Combinatorial optimization, Circuits and Systems Design Optimization.

Materials and device characterization, Analysis and modeling; Electron beam techniques; EBIC metrology.

RF device modeling and IC packaging.

Kim Tae Hyoung [email protected]

Low power, High performance digital, Mixed-mode memory circuit design, Ultra-low voltage sub-threshold circuit design for Energy efficient systems, Variation & aging tolerant circuits & systems and circuit techniques for 3D ICs.

Research Interest


42

Yeo Kiat Seng Professor [email protected]

Yu Yajun AssistantProfessor

[email protected]

Zheng YuanjinAssistantProfessor

[email protected]

Yu Hao [email protected]

PhD and MEng Degrees Awarded in 2010

Zhang Yue Ping [email protected]

Chang Chip HongChen Jiajia

Chan Pak KwongCui Jie

Siek LiterDuan Lian

Chang, Joseph SylvesterTan Meng Tong

Ge Tong

PhD

Project Title Student Supervisor / Co-Supervisor

Device modeling, RFIC design, Low-voltage low-power IC design.

VLSI digital signal processing, VLSI circuits and systems design.

Wideband high frequency RFIC and SoC design, MEMS and SAW device and circuits, UWB system and circuits, Bio-IC system and circuits, Adaptive signal and image processing ASIC.

RF IC design and analysis, Low-power and robust 3D system design, Computer-aided design. CMOS emerging technology.

Wireless chip area network, Single-chip radio and Radio bioelectronics.

Atila Alvandpour

VisitingProfessor

cum Director(VIRTUS)

[email protected]

Flexible Multi-band Wireless Transceiver AnalogFrontends, High-speed Data Converters (ADCs/DACs), Multi-GHz Digital Circuits and On-chip Memory Solutions.High-speed On/off-chip Communication Links,Clock Generation, Timing, and SynchronizationTechniques.Ultra-low-power IC Design for Medical Implant Devices.

Tan Meng TongAssistantProfessor

[email protected] design, Class D amplifiers, Analog and digital signal processing, Biomedical engineering.

Tan Cher Ming [email protected]

Materials and electronic devices reliability testing, physics and data analysis; Equipmentreliability and maintainability study, nano materials, remanufacturing reliability, energy harvesting device and circuits

New Design Methodologies for Low Complexity FIRFilters and Reconfigurable Constant Multipliers

A Monolithic Capacitive Transducer for Electrical Capacitance Tomography

A Burst Mode Optical Receiver for Ethernet Passive Optical Network

Analog class D amplifiers: Non-Linearities and Power-Efficiency


43

PhD and MEng Degrees Awarded in 2010

Tan Cher MingHou Yuejin

Yeo Kiat SengLim Chee Chong

See Kye YakLi Er Ping Liu Zhihong

Chang, Joseph SylvesterTan Meng Tong

Shu Wei

Yeo Kiat SengTong Ah Fatt

Chan Pak KwongYin Jee Khoi

Chang, Joseph SylvesterGwee Bah Hwee

Victor Adrian

PhD


Siek LiterDu Yuanyuan

Siek LiterWang Jinling

Yeo Kiat SengTan Meng Tong

Lao Jiahong

Tan Cher MingLiao Jie

Goh Wang LingSeyed MohammadEhsan Hosseini

A Low-Jitter Frequency Multiplier

MEng


Reliability Modeling for ULSI Interconnects

Design, modeling and characterization of On-Chip Transformer for Silicon RFIC

Efficient and Accurate Modeling of Finite-size Printed Circuit Structure

Nonlinearities of Analog Pulse Width Modulation (PWM) Class-D Amplifiers

Design of a Scalable RF Model for Deep Sub-Micron Mosfets

Modulation Schemes for Digital Modulators of Class D Amplifiers and of Switched-Mode DC-DC Converters

Design of Multi-Standard and Wideband Delta-sigma Modulator

Design of a Power Efficient Output Stage for DC-to-DCConverters

Hot Carrier Reliability Perspective on Silicon-on- Insula-tor (SOI) Lateral Double-Diffused MOSFET (LDMOS)

FPGA Implementation of Low Density Parity Check (LDPC) Coded Recording Channels

Top-Down Design Verification of Subranging Pipelined Analog-to-Digital Converter


44

Selected Publications in 2010A. Basu, S. Ramakrishnan, C. Petre, S. Koziol S. Brink and P. Hasler, "Neural Dynamics in Reconfigurable Silicon", IEEE Trans. on Biomedical Circuits and Systems, vol. 4, no. 5, pp. 311-19, Oct. 2010.

1.

A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, et.al, "A Floating-gate based Field Programmable AnalogArray", IEEE Journal of Solid State Circuits, vol. 45, no. 9, pp. 1781-94, Sept. 2010.

2.

A. Basu and P. Hasler, "Nullcline based design of Silicon Neurons", IEEE Trans. On Circuits and Systems I, vol. 57,no. 11, pp. 2938-47, Nov. 2010.

3.

A. Meaamar, C. C. Boon, K. S. Yeo and M. A. Do., "A Wideband Low Power Low-Noise Amplifier in CMOSTechnology", IEEE Transactions on Circuits and Systems I: Regular Paper, Vol. 57, No. 4, pp. 773 - 782, Apr 2010.

4.

G. T. Ong and P. K. Chan, "A Low Quiescent Biased Regulator with High PSR Dedicated to Micropower SensorCircuits", IEEE Sensors Journal, vol. 10, no. 7, pp. 1266-1275, July 2010.

7.

Y. Tian and P. K. Chan, "Design of High-Performance Analog Circuits using Wideband Gm-Enhanced MOSComposite Transistors", IEICE Trans. on Electronics, vol. E93-C, no. 7, pp. 1199-1208, July 2010.

8.

A. Cui, C. H. Chang, S. Tahar and A. A. Hamid, "A robust FSM watermarking scheme for IP protection ofsequential circuit design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2010. (Accepted for publication as regular paper).

9.

R. Muralidharan and C. H. Chang, "Radix-8 Booth encoded modulo 2n 1 multipliers with adaptive delay forhigh dynamic range residue number system", IEEE Transactions on Circuits and Systems-I: Regular Papers, 2010 (Accepted for publication).

10.

C. H. Chang and A. Cui, "Synthesis-for-testability watermarking for field authentication of VLSI intellectualproperty", IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 57, no. 7, pp. 1618-1630, July 2010.11.

V. Adrian, J.S. Chang and B.H. Gwee, "A Randomized Wrapped-Around Pulse Position Modulation Scheme forDC-DC Converters", IEEE Transactions on Circuits and Systems I: Regular Paper, accepted for publication, 2010.12.

S.S. Chen, A. Bermak, Y. Wang, "A CMOS Image Sensor With On-Chip Image Compression Based on PredictiveBoundary Adaptation and Memoryless QTD Algorithm," IEEE Transactions on Very Large Scale IntegrationSystems, Volume PP, Issue 99, pp.1-10, Jan. 2010.

13.

M.V. Krishna, M.A. Do, K.S. Yeo, C.C. Boon and W. M. Lim, "Design and Analysis of Ultra low power True singlephase clock CMOS 2/3 prescaler", IEEE transactions on Circuit & Systems-I, Regular paper, vol. 57, no.1,pp. 72-82, Jan 2010.

14.

A. V. Do, C. C. Boon, M. A. Do, K. S. Yeo and A. Cabuk, "An Energy-Aware CMOS Receiver Front End for Low-Power2.4-GHz Applications", IEEE Transactions on Circuits and Systems Part I: Regular Papers, vol. 57, no. 10, pp. 2675-2684, ISSN: 15498328, Dec 2010.

5.

Y. N. Miao, C. C. Boon, M. A. Do and K. S. Yeo, "High-Frequency Low-Power LC Divide-by-2/3 Injection-lockedFrequency Divider", Microwave and Optical Technology Letters, Vol. PP, No. 99, accepted, 2010.

6.

N. Zhu, W.L. Goh, WJ Zhang, K.S. Yeo, and Z.H. Kong, "Design of Low-Power High-Speed Truncation-Error-TolerantAdder and Its Application in Digital Signal Processing", IEEE Transactions on Very Large Scale Integration (VLSI)Systems, Vol. 18, Issue: 8, pp. 1225-1229, August 2010.

15.

M. R. Meher, C. C. Jong and C. H. Chang, "A high bit rate serial-serial multiplier with on-the-fly accumulationby asynchronous counters", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010 (Acceptedfor publication as regular paper).

17.

C.F. Law, B.H. Gwee and J.S. Chang, "Modeling and Synthesis of Asynchronous Pipelines", IEEE Transactions on Very Large Scale Integration Systems, (Regular Paper), accepted for publication, 2010.

16.


45

Selected Publications in 2010J. Keane, T. Kim, X. Wang, and C. H. Kim, "On-Chip Reliability Monitors for Measuring Circuit Degradation",Microelectronics Reliability Journal, Vol. 50, pp. 1039-1053, Aug. 2010.

18.

J. Keane, T. Kim, and C. H. Kim, "An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation",IEEE Trans. on VLSI Systems, Vol. 18, No. 6, pp. 947-956, June 2010.

19.

A. T. Do, Z. H. Kong, and K. S. Yeo, Criterion to evaluate input-offset voltage of a latch-type sense amplifier,"IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 1, pp. 83-92, 2010.

20.

A. T. Do, Z. H. Kong, K. S. Yeo, and Y. S. Low, "Design and Sensitivity Analysis of a New Current-mode SenseAmplifier for Low-power SRAM", accepted for publication in IEEE Trans. VLSI systems: Regular Papers, Apr 2010.

21.

Y. S. Ong, M. H. Lim and X. S. Chen, "Research Frontier: Memetic Computation - Past, Present & Future",IEEE Computational Intelligence Magazine, Vol. 5, No. 2, pp. 24 -36, 2010.

22.

L. Q. Song, M. H. Lim and P. N. Suganthan, "Ensemble of Optimization Algorithms for Solving QuadraticAssignment Problems," IJICIC, Accepted 2010.

23.

O. Kurniawan, C. C. Tan, and V.K.S. Ong, "Corrections to Charge Collection from within a Collecting JunctionWell", IEEE Transactions on Electron Devices, U.S.A., vol. 57, no. 9, p. 2358, Sep 2010.

26.

V. Tarateeraseth, B. Hu, K. Y. See and F. G. Canavero, "Accurate extraction of noise source impedance of an SMPS under operating conditions", IEEE Trans. on Power Electronics, Vol. 25, No. 1, pp. 111-117, January 2010.

27.

W. Y. Chang, K. Y. See and B. Hu, "Characterization of component under DC biasing condition using aninductive coupling approach", IEEE Trans. on Instrumentation & Measurement, Vol. 59, No. 8, pp. 2109-2113,August 2010.

28.

V. Tarateeraseth, K. Y. See, F. G. Canavero and W. Y. Chang, "Systematic electromagnetic interference filter designbased on information from in-circuit impedance measurement", IEEE Trans. on Electromagnetic Compatibility,Vol. 52, No. 3, pp. 588-598, August 2010.

29.

O. Kurniawan, C.C. Tan, V.K.S. Ong, E.P. Li, and C.J. Humphreys, "A Direct Method for Charge CollectionProbability Computation Using the Reciprocity Theorem", IEEE Transactions on Electron Devices, U.S.A.,vol. 57, no. 10, pp. 2455-2461, Oct 2010.

24.

C.C. Tan and V.K.S. Ong, "An Analytical Expression for Charge Collection Probability from Within a U-ShapedJunction Well", IEEE Transactions on Electron Devices, U.S.A., vol. 57, no. 11, pp. 3068-3073, Nov 2010.

25.

C. Baudot, C. M. Tan, and J. C. Kong, "FTIR spectroscopy as a tool for nano-material characterization", InfraredPhysics & Technology, vol. 53, pp. 434-438, 2010.

31.

X. Shi, K. S. Yeo, W. M. Lim, M. A. Do, and C. C. Boon, "A Spice Compatible Model of On-Wafer CoupledInterconnects for CMOS RFICS", PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER, vol. 102, pp. 287-299,May 2010.

30.

F. He and C. M. Tan, "Circuit level interconnect reliability study using 3D circuit model", MicroelectronicsReliability, vol. 50, no. 3, pp. 376-390, 2010.

33.

C.M. Fu, C. M. Tan, S.H. Wu and H.B. Yao, "Width dependence of the effectiveness of reservoir length inimproving electromigration for Cu/low-K interconnects", Microelectronics Reliability, vol. 50, pp. 1332-1335,2010.

32.

X.S. Loo, K.S. Yeo, K.W.J. Chew, L.H.K. Chan, S.N. Ong, M. A. Do and C. C. Boon, "An Accurate Two-portDe-embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors", IEEE Transactions on Microwave Theory and Techniques, accepted, Dec. 2010.

34.


46

Selected Publications in 2010Z. H. Lu, K. S. Yeo, W. M. Lim, M. A. Do and C. C. Boon, "Design of a CMOS Broadband Transimpedance AmplifierWith Active Feedback", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 3, pp. 461-472, Mar. 2010.

35.

A.T. Do, K.S. Yeo, J. Y. S. Low, J. Y. L. Low, X. L. Tan, and Z.H. Kong, "An 8T differential SRAM with improved noisemargin for bit-interleaving in 65 nm CMOS", accepted for publication in IEEE TCAS I, 2010.

36.

H. Yu, C. Chu, Y. Shi, D. Smart, L. He and S. Tan, "Fast Analysis of Large-scale Inductive Interconnect by BlockStructured Macromodeling", IEEE Transactions on Very Large Integrated Circuits and Systems (TVLSI) vol.18,no.10, pp1399-1411, October 2010.

37.

F. Gong, X. Liu, H. Yu, S. Tan and L. He, "A Fast Non-Monte-Carlo Yield Analysis and Optimization by StochasticOrthogonal Polynomials", ACM Transaction on Design Automation of Electronic Systems (TODAES) 2011(accepted), 2010.

38.

H. Qian, X. Huang, H. Yu, and C. Chang, “Cyber-physical Thermal Management of 3D Multi-coreCache-Processor System with Microfluidic Cooling”, Journal of Low Power Electronics (JOLPE), (accepted) 2010.39.

D. Shi, and Y. J. Yu, "Design of Linear Phase FIR Filters with High Probability of Achieving Minimum Numberof Adders", accepted by IEEE Trans. Circuits, Syst. I, 2010.40.

M. Sun, Y. P. Zhang, Y. L. Lu, "Miniaturization of planar monopole antenna for ultrawide-band radios", IEEETransactions on Antennas and Propagation, vol. 58, no. 7, pp. 2420-2425, July 2010. This is No. 5 of the Top10 Accessed Papers from the IEEE AP in July 2010.

43.

Y. P. Zhang, G. R. Han, W. M. Zhang, "Theory of periodically loaded oversized imperfect waveguide and itsapplication to the propagation of radio waves in long wall mining tunnels", IEEE Transactions on Antennasand Propagation, vol. 58, no. 5, pp. 1816-1822, May 2010.

44.

R. Bregovic, Y. J. Yu, A. Viholainen and Y. C. Lim, "Implementation of Linear-Phase FIR NearlyPerfect-Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry", IEEE Trans.Circuits, Syst. I, vol. 57, no. 1, pp. 139-151, Jan. 2010.

41.

Y. J. Yu, and Y.C. Lim, "Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space", Circuit Syst. Signal Process, vol. 29, no. 1, pp. 65-80, Jan. 2010.

42.

X. J. Li, Y. P. Zhang, "Flipping the CMOS switch", IEEE Microwave Magazine, vol. 11, no. 1, pp. 86-96, 2010.45.

M. U. Nair, Y. Zheng, C. W. Ang, Y. Lian, X. Yuan, and C. -H. Heng, "A Low SIR Impulse-UWB Transceiver Utilizing Chirp FSK in 0.18μm CMOS", IEEE Journal of Solid Circuits, vol. 45, no.11, pp. 2388-2403, Nov. 2010.

46.

S. -J. Cheng, L. Qiu, Y. Zheng and C. -H. Heng, "50-250 MHz ΔΣ DLL for Clock Synchronization", IEEE Journal of Solid Circuits, vol. 45, no. 11, pp. 2445-2456, Nov. 2010.

47.

X. Liu, Y. Zheng, M. W. Phyu, M. Je, and X. Yuan, "Multiple Functional ECG Signal Processing for Wearable Applications of Long-Term Cardiac Monitoring", IEEE Transactions on Biomedical Engineering,Pre-publication, 2010.

48.

Documents

Division Of - NTU EEE · 2018. 5. 9. · C. Ultra-low Power Subthreshold SRAM Design The objective of this research is to design and implement SRAMs for emerging ultra-low power/energy