Display Timing Calculation

(MB86R0x 'Jade' Series)

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Display Timing Formulae

frequencyhorizontalfScalerSC

PLLclockreferenceffrequencyverticalf

clockpixelf

h

ref

v

clkdot

==

==

=

)(

_ HTPVTRff vclkdot **_ =

SCf

f refclkdot =_

clkdot

ref

v

ref

ff

HTPVTRff

SC_**

==

HTPVTRf

f clkdotv *

_=

HTPVTRSCf

f refv **=MhzfJADE ref 666: =

MhzfJADE clockdot 67: _ <

Note:

VDPVf th *=

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Clock Generation in Jade Series Devices

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Display Timing Parameters

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Display Timing Guideline - 1

1. Select the display parameters from the display panel specification 0 < HDB ≤ HDP < HSP < HSP + HSW + 1 < HTP 0 < VDP < VSP < VSP + VSW + 1 < VTR

2. Calculate the pixel frequency

3. Calculate the scaler value Select integer value: ->Round down ->Round up Calculate the resulting pixel vertical frequency with the selected scaler value: Check that the calculated values fulfill the display specifications. Optional: adapt the blanking area to reach a more precise result.

HTPVTRff vclkdot **_ =

clkdot

ref

v

ref

ff

HTPVTRff

SC_**

==

SCf

f refclkdot =_ HTPVTRSC

ff ref

v **= Mhzf clockdot 67_ <

Note: Skew occurs between the syncs and the RGB/DE signals (the RGB and DE signals are delayed) : - Coral family – 13 pixel clock cycles - Carmine – 15 pixel clock cycles - The timing at the GDC pads is different to the register settings - Panels requiring less H-sync back porch are not supported – the H-sync has to be delayed by external logic

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Display Timing Guideline - 2

4. Set scaler register value The scaler value depends on the selected offset

NOTE: Also, when the PLL is selected as the reference clock, frequency division ratios 1/1 to 1/5 are non-functional even if set (!) other frequency division ratios are assigned. Therefore – valid setting range: 1/6 ... 1/64

NOTE: To achieve timings that require a setting higher than 1/64, the LCS bit of the DCM0/1 register can be used: LCS = 0: fdot_clk = (fPLL)/SC LCS = 1: fdot_clk = [(fPLL)/SC]/4

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Display Timing Example - 1

Display Panel: Toshiba Matsushita Display Technology, LTA065B0D0F (6") Vertical frequency: 60 Hz Excerpt from the display specification:

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Display Timing Example - 2

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Display Timing Example - 3

1. Select the display parameter

VTR

VDPVSW

VSP (tvde+tvfp)

HSWHTP

HDP

HSP (thde+thfp)

HTP 800 VTR 525

HSP 648 VSP 482

HSW 160 VSW 2

HDP 640 VDP 480

Mhznstperiodclockf cclkdot 75.2835minmax_ ====

HzmstvPeriodFramefv 5685.17maxmin ====

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Display Timing Example - 4

2. Calculate the pixel frequency 3. Calculate the scaler Round down: SC = 26

MhzHzHTPVTRff vclkdot 2.25800*525*60**_ ===

4.262.25

666** _

====MhzMhz

ff

HTPVTRff

SCclkdot

ref

v

ref

OKMhzMhzSCf

f refclkdot >−=== 62.26

26666

_

OKHzMhzHTPVTRSC

ff ref

v >−=== 99.60800*525*26

666**

Mhzf clockdot 67_ <

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Display Timing Example - 5

Round up: SC = 27 Try to reach a precise result by modifiying the blanking area: 4. Set scaler register value

OKMhzMhzSCf

f refclkdot >−=== 67.24

27666

_

OKHzMhzHTPVTRSC

ff ref

v >−=== 73.58800*525*27

666**

HTP 860 VTR 500

HSP 648 VSP 482

HSW 160 VSW 2

HDP 640 VDP 480 HzfMhzf

SC

v

clkdot

57.59

4.2626:

_

=

=

Offset 0x100 -> m = SC-1 = 25 = 0x19 Write register DCM1: 0x1900

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