Digital_assignment

7/30/2019 Digital_assignment

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Section 3-3

3.12 Show Karnaugh map for equation Y= F(A,B,C) = m(1, 2, 3, 6, 7)

3.13 Show Karnaugh map for equation Y= F(A,B,C,D) = m(1, 2, 3, 6, 8, 9, 10, 12, 13, 14)

Section 3-7

3-23 Give SOP form ofY= F(A,B,C,D) = M(0, 3, 4, 5, 6, 7, 11, 15)

3-24 Draw Karnaugh map ofY= F(A,B,C,D) = M(0, 1, 3, 8, 9, 10, 14, 15)

Section 3-8

3-29 Simplify to give POS form by grouping zeros in Karnaugh map for equation given in problem 3-23.

3-30 Simplify to give POS form by grouping zeros in Karnaugh map for equation given in problem 3-24.

Section 3-9 and 3-10

3-31 Get simplified expression ofY= F(A,B,C,D) = m(1, 2, 8, 9, 10, 12, 13, 14) using Quine-McClusky

method.

3-32 Get simplified expression ofY= F(A,B,C,D,E) = m(0, 1, 2, 3, 4, 5, 12, 13, 14, 26, 27, 28, 29, 30)

using Quine-McClusky method.

3-33 For the following Karnaugh map give SOP and POS form that do not show static-0 or static-1 hazard.

AB

AB

AB

AB

_ _

_

_

_

C C

1 1

0 0

1 0

1 0

3-34 Verify with timing diagram if the following circuit shows dynamic hazard.

A

B

C

D

Y


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4-12 Design a circuit that realizes following two functions using a decoder and two OR gates.

F1(A,B)=m(0,3) and F2(A,B)=m(1,2)

4-13 Design a circuit that realizes following three functions using a decoder and three OR gates.

F1(A,B,C)=

m(1,3,7), F2(A,B,C)=

m(2,3,5) and F3(A,B,C)=

m(0,1,5,7)

Change heading SECTION 4-8 to SECTION 4-8 and 4-9

Add

4-29 Write the (X>Y) equation for a 4-bit comparator.

4-30 Show how magnitude of two 10-bit numbers can be compared using IC 7485.

6-18 Show how two IC 74283s can be connected to add two 8-bit numbers. Does the carry ripple between

two ICs ?

6-19 Show how a parallel adder generates sum and carry bits while adding two numbers 1001 and 1011,

What is the final result?

SECTION 6-10

6-20 HowA


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8-31 Convert Tflip-flop toD flip-flop.

8-32 Convert SR flip-flop to Tflip-flop.

9-25 Show how modulo-8 switched tail counter works if is initialized with 1001. How to decode this

counter?

9-26 Show the circuit diagram for a 8-bit sequence detector which has to detect a fixed pattern 10011110

from incoming binary data stream.

10.31 Design a modulo-3 counter usingD flip-flop that counts as 011011. The unused state 00 goes to

01 at next clock trigger.

10.32 Design a modulo-5 counter usingD flip-flop the unused states of which go to one of the valid

counting state at next clock trigger.

10.33 Design a circuit usingJKflip-flop that behaves both as a modulo-5 and modulo-3 counter depending

on how it I initialized.

10.34 Design a modulo-8 counter (a) using SR flip-flop and (b) using Tflip-flop.

10.35 Design a sequence generator with minimum number of flip-flops that generates sequence 110001repetitively.

10.36 Design a sequence generator with minimum number of flip-flops that generates sequence 10110001

repetitively.

SECTION 11.1 AND 11.2

11-1 Draw state transition diagram of synchronous sequential logic circuit using Mealy Model that detects

three consecutive zeros from an input data stream,Xand signals detection by making output, Y=1.

11-2 Convert Mealy Model of problem 11-1 to Moore Model using conversion rules.

11-3 Using Moore Model draw state transition diagram of a serial parity checker circuit. If the number of1s received at inputXis even, parity checker output, Y=0. If odd number of 1s are received atX

then Y=1.

11-4 Convert Moore Model of problem 11-3 to a Mealy Model.

11-5 Using Moore Model draw state transition diagram of the circuit that generates a single pulse of width

equal to clock period when enabled byE=1. The circuit is reset byE=0 at any stage.

11-6 Draw state transition diagram of sequence detector circuit that detects 1101 from input data stream

using both Mealy and Moore Model.

SECTION 11.3 AND 11.4

11-7 For Mealy Model state transition diagram of sequence detector problem shown in Fig. 11.2b use

following state assignment and get corresponding state synthesis table for JKflip-flop based solution.

a :B=0,A=0 b:B=0,A=1 c:B=1,A=1

11-8 For Mealy Model state transition diagram of sequence detector problem shown in Fig. 11.2b use

following state assignment and get corresponding state synthesis table for JKflip-flop based solution.

a :B=0,A=0 b:B=0,A=1 c:B=1,A=1 d:B=1,A=0

11-9 Give design equations for problem 11-7. Compare this with solution given in section 11.4.


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11-10 Give design equations for problem 11-7. Compare this with solution given in section 11.4.

11-11 Give design equations for problem 11-1 for implementation withD flip-flops.

11-12 Implement circuit diagram for problem 11-1 usingJKflip-flops.

11-13 How many memory elements are necessary for Mealy and Moore Model in sequence detector

problem 11-6.

11-14 Implement (a) parity checker circuit of problem 11-3 and (b) single pulse generator circuit of

problem 11-5.

SECTION 11.5 TO 11.7

11-15 Show how using an additional column in ROM the combinatorial circuit of Fig. 11-9 for sequence

detector problem can be dispensed of.

11-16 Implement ROM based solution for problem 11-6 where output is directly derived from ROM.

11-17 In vending machine problem of section 11.6 we want to add an additional function. We give the

customer an option to get back the coins he has deposited if he finds himself short of money or

changes his mind midway. However, this function does not work if the cost of the product is reached.

A push button switch, P is used for this which when pressed generates P=1 and returns the coin

deposited thus far by activating C=1. Show what changes in ASM chart of Fig. 11-12 are necessary

for this.

11-18 Draw ASM chart for problem 11-5and implement the circuit using ROM.11-19 Find the minimum number of states necessary to represent following state table both by row

elimination and implication table method.

Present State Next State

X=0 X=1

Present Output

X=0 X=1

a f d 0 1 b c f 1 1c f b 1 1

d e g 1 1 e a d 1 1f g b 0 1

g a d 0 1

11-20 Reduce following state table using implication table method.

Present State Next State

X=0 X=1

Present Output

X=0 X=1

a h c 1 0 b c d 0 1c h b 0 0

d f h 0 0 e c f 0 1f f g 0 0

g g c 1 0

h a c 1 0

SECTION 11.8

11-21 State the condition of stability in asynchronous sequential logic.

11-22 One of the two inputs of a two input NOR gate is fed back from the output. Write its state stable and

encircle stable states, if any.

11-23 For state table in problem 11-30 show the stable states, if any.

11-24 For state table in problem 11-30 show how the circuit behaves whenxy=11 andA changes as 10.


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11-25 There are three inputsA,B and Cto an asynchronous sequential logic system. IfABC=111 at any

given time write the allowed combination of inputs that can follow.

11-26 Draw state table of following asynchronous sequential logic circuit.

A

B

x

X

SECTION 11.9

11-27 When does oscillation occur in an asynchronous sequential logic circuit?

11-28 How can essential hazard be prevented in asynchronous sequential logic circuit?

11-29 There are two inputsA,B and three feedback outputs x,y andz of an asynchronous sequential logic

system. IfxyzAB=10011 gives a stable state and inputAB changes as 1110, which of the following

next state does not give racing problem 10110, 00110, 11010, 00010 and 11110?11-30 Find out potential problems in following state table whereA is input andx andy are output

feedbacks.

01 10

0 0 0 1 1 1 1 0

0

1 00 01

10

xyA

00

01 11

SECTION 11.10

11-31 The Tfilp-flop has a single input T, and single output Q. For T=0, output does not change. For T=1,

output complements and remains at that value as long as T=1. Draw its (a) state diagram and (b)

primitive flow table.

11-32 For problem 11-31, use state reduction technique to check if a reduced flow table is possible.

11-33 Find design equations for problem 11-31 after appropriate state assignment.

11-34 Design a parity generator using asynchronous sequential logic that gives output=1 when it receives

odd number of pulses and output=0 if the number of pulses received is even. (Hint: State transition

diagram is same as problem 11-31)

11-35 Draw state transition diagram of a modulo-3 counter for asynchronous sequential logic. The counter

counts number of pulses appearing at its input and generates output=1 when three pulses arrive else

output=0.

11-36 Design modulo-3 counter stated in problem 11-35 using asynchronous sequential logic.

11-37 We require a circuit which will suppress narrow positive spikes on a signal line. The output of the

circuit will be an inverted and slightly delayed version of the input minus the spikes. Construct the

primitive flow table and show one state assignment scheme.

11-38 Get design equations for problem 11-37 and implement the circuit. Verify how it does noisesuppression.

12-14 Why data integrity of optical memory is better than magnetic memory?

12-15 What is the data transfer rate of a 52X CD-ROM drive?

12-16 Briefly explain Read, Write, Erase process of CD-RW media.

12-17 What is the data transfer rate of 8X DVD-ROM drive?


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SECTION 16-1

16-1 For memory configured as in Fig, if immediate addressing is allowed what is the maximum value of

number (in decimal) can be loaded through instruction fetch?

7 5 4 0

Opcode Address

16-2 What is the minimum size required forMAR if memory addressed has size 1K16?

16-3 For a more complex computer design, 75 different instructions are required. What size ofIR would

you likely to choose?

16-4 Draw data path of the computer described next. The computer in addition to what is described in

section 16-2 has two more registers P and Q, which can transfer data to/fromACCvia BUS. It also has a

CYflag that stores ALU overflow and a Z flag that is set when all the bits ofACCare zero.

SECTION 16-2

16-5 What does the following statement mean (X+ Y) :AB

16-6 Explain the meaning of XY :AB

16-7 Give the final content ofACCwhen following statements are executed

T1 : ACCACCMDR

T2 :ACCACC

16-8 State what the following statement performs for the computer described in problem 16-8.

T1 : ACCACC+MDR

CY& T2 : P ACC

CY& T2 : Q ACC

SECTION 16-3

16-9 Show how shift left operation with carry is executed.

16-10 Show how shift right operation with carry can be executed.

16-11 Consider the first instruction of the simple computer is replaced by MVI that moves immediate data

(immediate addressing) toACC. Write micro operations for this instruction. What change in hardware is

required for this?

16-12 Consider the first instruction of the simple computer is replaced by LDI that moves indirect data

(indirect addressing) toACC. Write micro operations for this instruction. Does it require any change in

hardware?

SECTION 16-4

16-13 What does LOADMAR = T0 + T2 mean?


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16-14 Explain if there will be any problem if by mistake the control unit is developed on logic equation

LOADMAR = T0 + T2 + T4.

16-15 Show using diagrams control inputs to ALU. Consider IC 74181 (Section 6-10, Chapter 6) is used as

ALU.

16-16 Show using diagrams control inputs to Memory.

SECTION 16-5

16-17 How many clock cycles are required to execute program given for example 16-7?

16-18 How many clock cycles are required to execute program given for example 16-8?

16-19 If the two numbers used in example 16-7 are 5 and 8, and data section immediately follows program

section show the memory values in binary after the program is executed? How will it be represented in

hexadecimal?

---------Example 16-7

Write a program for this computer that adds two positive integers, available in memory locations addr1 and

addr2, multiplies the sum by 5 and stores final result in location addr3. Consider, the numbers are small

enough not to cause any overflow i.e. data at every stage require less than 8-bits for its representation.

Solution

Addition of two numbers is straightforward and can be done using LDA and ADD instructions. For

multiplication with 5 we have to use an indirect technique. Two left shift give multiplication by 4 and one

addition will make it multiplication by 5. Alternatively, 5 ADD operations will also give multiplication by

5. The program can be written as follows.

LDA addr1

ADD addr2STA addr3

SHL

SHL

ADD addr3

STA addr3

HLT

Note that, we have used addr3 as intermediate storage of addition result. Since in the computer designed

there is no instruction to place data on a register fromACC(and also retrieve the same) we had to use

memory. Storing intermediate results in registers speeds up the process but here we are limited by the

architecture and instruction set available. Also note, we could have used any other available memory

location for intermediate storage.

--------

16-20 If the two numbers used in example 16-8 are F216 and D616 and data section immediately follows

program section show the memory values in binary after the program is executed?

--------

Example 16-8

Write a program for this computer that performs bit-wise Ex-OR operation on two numbers available in

memory locations addr1 and addr2. The result is to be stored in location addr3.


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Solution

Our designed computer can perform only two kind of logic operations AND and NOT. Therefore, we break

Ex-OR logic of two numbers sayA andB in such a way that there is only AND and NOT operator.

Y=AB =AB +AB = ((AB).( AB)) [From DeMorgans Theorem]

Thus the program can be written as shown next. The logic operation performed by each instruction isshown as comment after semicolon.

LDA addr1 ;A

NOT ;A

AND addr2 ;AB

NOT ; ( AB)

STA addr3

LDA addr2 ;B

NOT ;B

AND addr1 ;AB

NOT ; (AB)

AND addr3 ; (AB).( AB)

NOT ; ((AB).( AB))STA addr3

HLT

--------

16-21 Write a program that compares two binary data located in addr1and addr2 of memory by making all

the bits ofaddr3 one if two numbers are exactly equal.

16-22 Write a program that executes following where Dataaddrrefers to data corresponding to address addr.

Dataaddr7 = (Dataaddr1 + Dataaddr2 + Dataaddr3 + Dataaddr4) 3 - (Dataaddr5 + Dataaddr6) 2

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