Digital Systems Testing Using BIST

8/13/2019 Digital Systems Testing Using BIST

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Advanced Embedded Memory

Testing and Analysis Using Built In Self TestPresented by

B.S.N Kishore

11741D5705M.tech(VLSI SystemsDesign)

Intell Engineering

College,Anantapuram

Under the guidance of

Smt.M.Mahitha M.tech

Assistant ProfessorDepartment of ECE


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AIM

To detect for faults in embedded read only memories.


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INTRODUCTION

Different types of faults occur like stuck at faults,

transition faults ,bridging faults etc.

It is imperative to deploy effective means of testingand diagnosing non volatile memory failures.


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Limitations of Existing System

The earlier method made use of algorithms baseddiagnosing like March a and march b .

Hardware area and hardware cost is increased.

Speed of is also less.


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BUILT IN SELF TEST(BIST)


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BIST(cont.)

BIST is a design for testability technique in whichtesting is accomplished through built in hardwarefeatures.

Output response analyzer indicates that the expectedresponse of the CUT is to be compared with the

reference response i.e. the golden response.


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PROJECT IMPLEMENTATION

The different modules that are implemented are:

Bist Controller

ROM Array Row Selector

Column Selector

Combined Row and Column Selector

Signature Register


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BIST CONTROLLER

BIST controller has a control on both test patterngenerator and output response analyzer

BIST controller consists of the reference responsewhere it sends to the signature register.

It generates row and column addresses that is sent tothe decoder.


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DETERMINISTIC PARTITIONING

The deterministic partitioning helps rows andcolumns decomposed into 2 partitions of same size

where n = 0.5 log v

Different groups of partitions are formed thus, suchthat the numbers are repeated in other partitions.


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ROW SELECTIONS


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ROW SELECTIONS(CONT.)

The row selector comprises of the upcounters forpartitions,groups,the LFSR and the offset counter.

The circuit implements the following formula

r =Sk+(p(gk)),k=0,1,...,P1.

For 16 rows forming 4 partitions( n =2) ,and withgroup 3 and partition 2,data is compacted fromrows 2,5,11,12


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ROW SELECTIONS (CONT.)


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COLUMN SELECTIONS


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PHASE SHIFTERS FOR COLUMN PARTITIONING


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COLUMN SELECTIONS(CONT.)

There is a need for two 1 out 4 column decoders andone phase shifter connected to the decoder selectingbits.

The addresses that are observed by the columndecoder 0 result in selection of columns 0,5.

The addresses that are received by column decoder 1result in selection of column 14 and 11.


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COLUMN SELECTIONS(CONT.)


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COMBINED ROW AND COLUMN SELECTIONS


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COMBINED ROW AND COLUMN SELECTION(CONT.)

The Combined row and column selection helps to findthe cells where rows and columns intersect.

They help to find single cell failures throughemploying signature register injector network.


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SIGNATURE REGISTER


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SIGNATURE REGISTER(CONT.)

Signature register is used to collect the test responsesarriving from selected memory cells

It compares the responses with that of golden responseand failing rows and/or columns are detected

The register can be reset at the beginning of every runover address space and the content of the register is

downloaded once per run .


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SIGNATURE REGISTER INJECTOR NETWORK


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a)single stuck at column and single stuck at row failure b)Error

free responsec)Erroneous response.


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Row Selector simulation result


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Column Selector simulation result


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Combined row and column selectorresult


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CONCLUSIONS The presented approach allows uninterrupted

collection and processing of test responses at systemspeed.

The new combined selection logic allows to collect testresults in parallel leading to shorter test time without

compromising quality of diagnosis and it clearlyconforms high accuracy of diagnosis .


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FUTURE SCOPE This method can be developed further to achieve

testing of more bits at once so that productivityincreases further.

The diagnositc data that needs to be scanned outduring ROM test may be decresed further.


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REFERENCES Digital Systems Testing and

Testability,Abramovici,Friedman,Jaico Press. D. Appello, V. Tancorre, P. Bernardi, M. Grosso, M.

Rebaudengo, and M. Sonza Reorda, Embeddedmemory diagnosis: An industrial workflow, inProc.ITC,2006

J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W.Maly, Enabling embedded memory diagnosis via testresponse compression, inProc.

High performance memory testing:Design principles,fault modelling and self test R.D Adams

http://nptel.iitm.ac.in http://www.edaboard.com/search.php?searchid=2570410
http://nptel.iitm.ac.in/http://www.edaboard.com/search.php?searchid=2570410http://www.edaboard.com/search.php?searchid=2570410http://nptel.iitm.ac.in/


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THANK YOU!

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Digital Systems Testing Using BIST