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GENERIC OFF LINE BIST ARCHITECTURE
S.Chandra Sekhar Srinivas
1250210108
18/7/2011
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DIGITAL SYSTEMS TESTING &TESTABLE DESIGN
INTRODUCTION
We consider BIST approaches for testing a single block
of combinational logic
Here we will consider general off-line BIST structures that are applicable to chips and boards consisting of blocks of combinational logic interconnected by storage cells
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DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN
Off line BIST architecture consists of several key elements namely
Test pattern generators (TPG)
Output response analyzers (ORA)
The circuit under test (CUT)
The distribution system (DIST)
The BIST controller
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Digital systems testing and testable design
Generic form of Centralized and separate BIST architecture
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DIGITAL SYSTEMS TESTING AND TESTABLE DESIGN
Off-line BIST architecture at the chip level and board level can be classified according to the following criteria
Centralized or Distributed BIST circuitry
Embedded or Separate BIST elements
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Generic form of distributed and separate BIST architectures
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DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
• Here each cut is associated with its own TPG and ORA circuitary
• These leads to more overhead but less test time
• Accurate diagnosis
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DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
Generic form of distributed and Embedded BIST architecture
•Here TPG and ORA elements are configured from functional elements with in the CUT, such as registers
• Advantage : This leads to more complex design to control and
has less hard ware
The choice of BIST architecture is a function of several factors , some of which are listed below .
Degree of test parallelism Fault coverage Levels of packaging Test time Physical constraints Complexity of replaceable units Factory and field test and repair strategy Performance degradation
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DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
Specific BIST architectures
Several BIST architectures proposed by various research and development groups
Centralized and Sepreate Board – level BIST architecture (CSBL)
Built in Evaluation and Self – Test architecture (BEST)
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DIGITALSYSTEM TESTING AND TESTABLE DESIGN
Centralized and Separate Board – level BIST architecture (CSBL)
It has the following attributes
Centralized and Separate BIST architecture
No boundary scan
Combinational or Sequential CUT
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DIGITALSYSTEM TESTING AND TESTABLE DESIGN
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DIGITAL SIGNAL PROCESSORS & ARCHITECTURES
A centralized and separate BIST architecture (CSBL)
Built in Evaluation and Self – Test architecture (BEST)
The built in evaluation and self test architecture is an application of the CSBL design to chips
The below figure shows BEST architecture
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DIGITAL SYSEM TESTING AND TESTABLE DESING
In General logic being tested is a sequential circuit
The inputs to the CUT are driven my a PRPG and the outputs are compressed using a MISR
Either a MUX can be used or PI’s can be loaded into the PRPG and then loaded into the CUT . The same concept applied to the output
Both Embedded and Separate version of architecture exists
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DIGITAL SYSTEM TESTING AND TESTABLE DESIGN
Embedded : PI’s and PO’s to the CUT go directly to registers and driven by registers
Separated : PRPG and MISR need to be added to the CUT
Here the BIST architecture results in low fault coverage because they are based on the testing sequential circuits
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DIGITALs SYSTEM TESTING AND TESTABLE DESIGN
CONCLUSION
To over come this problem an internal scan path can be used with in the CUT
So that the testing of CUT can be reduced to the problem of testing the combinational logic.
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DIGITAL SYSTEM TESTING AND TESTABLE DESGN
THANK YOU
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DIGITAL SYSETM TESTING AND TESTABLE DESIGN
![Metamorphic Testing: Testing the Untestable€¦ · are often referred to as non-testable (or untestable) [1]–[3]. Metamorphic testing (MT) is an effective technique for alleviating](https://img.pdfslide.us/doc/110x75/60526363bf6dbb585a17083f/metamorphic-testing-testing-the-untestable-are-often-referred-to-as-non-testable.jpg)
