Digital System and IC Design_sandeppani Ppts

8/10/2019 Digital System and IC Design_sandeppani Ppts

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Sandeepani School of VLSI Design 1

Digital System and IC Design

PART ONE

Sandeepani School of VLSI Design


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System:


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Digital System!


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Digital system Design

System Design:

Large design broken down into sub design with specified characteristics

Eg :Digital computer

Logic Design:Involves determining how to interconnect basic logic building blocks to

perform a specific function Eg :Binary Addition(Interconnection Logic and Flip Flop)

Circuit Design:Interconnection such as resistors, Diodes, transistors

Switching NetworksCombinational

Sequential


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Combinational vs. Sequential


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Levels of integrated circuits


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Binary Valued Signals



Binary Valued Signals contd



VLSI: but why? Integration improves the design:

lower parasitics = higher speed;

lower power; physically smaller.

Integration reduces manufacturing cost-(almost) nomanual assembly.


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VLSI and you Microprocessors:

personal computers;

microcontrollers.

DRAM/SRAM/flash.

Audio/video and other consumer

systems.

Telecommunications.



Moores Law Gordon Moore: co-founder of Intel.

Predicted that number of transistors per

chip would grow exponentially (doubleevery 18 months).

Exponential improvement in technology

is a natural trend: steam engines,dynamos, automobiles. Moores Law


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Field-programmable gate arrays FPGAs are programmable logic devices:

Logic elements + interconnect.

Provide multi-level logic.

LE

LE

LE

Interconnect

network

LE

LE

LE


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FPGAs and VLSI

FPGAs are standard parts:

Pre-manufactured, shorter design cycle.

Dont worry (much) about physical design.

Time to market is less, but FPGAs are slower,

larger, more power-hungry.

Custom silicon: Tailored to your application.

Generally lower power consumption.

Time to market is more


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ASIC D i F l


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ASIC Design F low

System Level Tools

Behavioral HDL

Behavioral Synthesis

Simulation (Behavioral/RTL)

Logic/Test synthesis)

Power Estimation

(RTL, Gate and Transistor Level)

Floor Planning & Placement Static Timing Analysis

Even-Driven Cycle Based Sim:

Formal verification

Static Timing Analysis

Even-Driven Cycle Based Sim:

Formal verification

Meets Timing

Routing

Parasitic Extraction

Meets Timing In-Place optimization

no

Yes

no

LVS/DRC

Yes

post

Layout- Verification

pre


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Embedded Digital System: The big picture


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Number System & Conversions


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1. (500.21)10 = ( ? )22. (436.71)8 = ( ? )163. Convert (231.3)Base 4 to Base 7

Convert Base 4 to Base 10

Convert Base 10 to Base 7Ans : (63.515) Base 7

Examples

4. 31684518 = ?

5. CB2H972H= ?

6. 0011.100120001.11102= ?

7. 79 - 26 in BCD representation?

8. 5 - 8 in XS-3?9. Divide (10)10by (4)10in binary representation.

10. Convert (847)10to gray code representation.

11. Perform direct subtraction: (9)10(10)10?


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Binary Addition

Binary Subtraction

Binary multiplication

Binary Division

Binary Arithmetic


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Boolean Algebra

AXIOMS :

DEFINITIONS:

THEOREMS:


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Problems

Perform the following number system

conversions:

a) (728)8 = ?16

b) 10111100.001010012 = ?8

c) 2AA216 = ?2

d) 201.128 = ?2 = ?16


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Prove

1. A + AB = A+B2. Sum of products of three variables is equal to 1.

3. Product of sums of three variables is equal to 0.

4. ABC+ABC+ABC+ABC+ABC = AB+C

Problems


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Block Diagram of a Combinational Circuit


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x1

x2

x3F F= (x1 + x2) . x3

x1

x2

F

Analysis of the Logic Network

Simplified Logic Network

F= (x1 + x2)


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Analysis and Simplify the Logic Network

x1

x2

F


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Basic Gates


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Representation Of Numbers

Signed magnitude

1s Complement

2s Complement


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Signed magnitude representation

Humans use a signed-magnitude system: we add + or - in front of amagnitude to indicate the sign.

We could do this in binary as well, by adding an extra sign bit to thefront of our numbers. By convention:

A 0 sign bit represents a positive number. A 1 sign bit represents a negative number.

Examples:

11012 = 1310 (a 4-bit unsigned number)

0 1101 = +1310 (a positive number in 5-bit signed magnitude)

1 1101 = -1310 (a negative number in 5-bit signed magnitude)


0 0100 = +410 (a positive number in 5-bit signed magnitude)

1 0100 = -410 (a negative number in 5-bit signed magnitude)


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Signed magnitude

operations Negating a signed-magnitude number is trivial: just change the sign

bit from 0 to 1, or vice versa.

Adding numbers is difficult, though. Signed magnitude is basicallywhat people use, so think about the grade-school approach toaddition. Its based on comparing the signs of the augend and

addend: If they have the same sign, add the magnitudes and keep that

sign.

If they have different signs, then subtract the smallermagnitude from the larger one. The sign of the number with thelarger magnitude is the sign of the result.

This method of subtraction would lead to a rather complex circuit

+ 3 7 9+ - 6 4 7

- 2 6 8

5 13 176 4 7

- 3 7 92 6 8

because


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Ones complementrepresentation

A different approach, ones complement, negates numbers bycomplementing each bit of the number.

We keep the sign bits: 0 for positive numbers, and 1 fornegative. The sign bit is complemented along with the rest of

the bits.

Examples:


0 1101 = +1310 (a positive number in 5-bit ones complement)

1 0010 = -1310 (a negative number in 5-bit ones complement)


0 0100 = +410 (a positive number in 5-bit ones complement)

1 1011 = -410 (a negative number in 5-bit ones complement)


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Why is it called ones

complement? Complementing a single bit is equivalent to subtracting it from

1.

0 = 1, and 1 - 0 = 1 1 = 0, and 1 - 1 = 0

Similarly, complementing each bit of an n-bit number isequivalent to subtracting that number from 2n-1.

For example, we can negate the 5-bit number 01101.

Here n=5, and 2n-1 = 3110= 111112.

Subtracting 01101 from 11111 yields 10010:

1 1 1 1 1- 0 1 1 0 1

1 0 0 1 0


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Ones complementaddition

To add ones complement numbers:

First do unsigned addition on the numbers, includingthesign bits.

Then take the carry out and add it to the sum.

Two examples:

This is simpler and more uniform than signed magnitude

addition.

0101 (+5)+ 0010 + (+2)

0111 (+7)

0101 (+5)

+ 1101 (-2)1 0010 (+3)

10011

1010 (-5)+ 0010 + (+2)

1100 (-3)

0101 (-5)+ 1101 (-2)

1 0111 (-7)1

1000


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Twos

complement Our final idea is twos complement. To negate a number, complement

each bit (just as for ones complement) and then add 1.

Examples:


0 1101 = +1310 (a positive number in 5-bit twos complement)

1 0010 = -1310 (a negative number in 5-bit onescomplement)

1 0011 = -1310 (a negative number in 5-bit twos complement)


0 0100 = +410 (a positive number in 5-bit twos complement)

1 1011 = -410 (a negative number in 5-bit onescomplement)

1 1100 = -410 (a negative number in 5-bit twos complement)


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0101 (+5)+ 0010 + (+2)

0111 (+7)

0101 (+5)+ 1110 (-2)1 0011 (+3)

1010 (-5)+ 0010 + (+2)

1101 (-3)

0101 (-5)+ 1110 (-2)1 1001 (-7)

Twos complement Addition


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b3b2b1b0 Sign and magnitude 1s complement 2s complement

0111 +7 +7 +7

0110 +6 +6 +6

0101 +5 +5 +5

0100 +4 +4 +4

0011 +3 +3 +3

0010 +2 +2 +2

0001 +1 +1 +1

0000 +0 +0 +0

1000 -0 -7 -8

1001 -1 -6 -7

1010 -2 -5 -6

1011 -3 -4 -5

1100 -4 -3 -4

1101 -5 -2 -3

1110 -6 -1 -2

1111 -7 -0 -1

Comparison


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ProblemsPerform

1. (6)10(4)10and

2. (4)10(6)10using 1`s complement

Perform

1. (6)10(4)10and

2. (4)10

(6)10

using 2`s complement


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Gates:electronic circuit that realizes a logical expression

l


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Logical Expressions

K M


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K-Maps


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Arithmetic CircuitsAdders:

Half adder

Full adderSerial adder

Ripple carry adder

Carry look ahead adder


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Implementation of Half Adder


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Implementation of Full Adder


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4-Bit Ripple carry adder


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4-Bit Carry Adder-Subtractor


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Serial Adder

Delay

Xi

Yi

Si

Ci + 1

Ci

Full Adder


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Carry Look Ahead Adder

Generation and Propagation Circuit

CLA - Generation Circuit


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4-Bit Carry Look Ahead Adder


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BCD Adder


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2bit X 2bit Multiplier


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Magnitude Comparator

Q. Design a 2-bitdigital comparator that accepts two

words A and B and gives three outputs :

G(>),

E(=) and

L(


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Q. Design a 4-bitdigital comparator that accepts two

words A and B and gives three outputs :

G(>),

E(=) and

L(


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2-bit Magnitude ComparatorAnswer:

let x1= (A1 ex-nor B1)

x0= (A0 ex-nor B0)

Z A=B= x1. x0

Z A>B= A1B1+ x1. A0B0

Z A


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4-bit Magnitude Comparator

Answer:

Z A=B= x3. x2 . x1. x0

Z A>B= A3B3+ x3. A2B2 +x3. x2.A1B1+ x3. x2. x1. A0B0

Z A


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4Bit Magnitude Comparator


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Design a 3- way Light controller

Let x1, x2, x3 be the input variables that denote the state

of each switch . Assume light is off if all the switches are

open. Closing any one switch will turn the light on .Thenturning on the second switch will turn off the light.thus the

light will be on if exactly one switch is closed and it will be

off if two or no switches are closed.If the light is off when two

Switches are closed then it must be possible to turn the light

On by closing the third switch.


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Problems

Q.1.Design a circuit which will accept 4-bit binary and

will provide 5-bit BCD code?

Q.2. Design a 3-bit squarer?

Q.3. A circuit accepts a 4-bit I/p data & generates an o/p

Z=1whenever I/p is a prime number. Design thecircuit?


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ProblemsQ.4. The conditions under which an insurance company

will issue a policy are :

A married female 25 years old or older, orA female under 25 years or

A married male under 25 years with no accident record, or

A married male with accident record, or

A married male under 25 years or older with no accident

record.

Obtain a simplified logic expression starting to whom a

policy can be issued.


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Universal Logic Element


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Universal Logic Element

Which of these are Universal logic

elements?

1. 2:1 MUX2. Ex-or2

3. {f(x,y)=xy}

4. {f(x,y,z)=(x+y)z}

5. Nand2


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Universal Logic Gate Introduction

A set of gates is said to be universal if any

combinational system can be implemented using

gates just from that set.

The set {AND,NOT} or {OR,NOT} is universal

. So any set of gates that can implement either{AND,NOT} or {OR,NOT} is universal.


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Universal Logic gate : Nand2

Lets start with NAND gate.

NAND(x,y)= (xy)NAND(x,x)=(xx)=xNOT(x)=NAND(x,x)

NOT gate can be implemented by a NAND gate

AND(x,y)= xy = ((xy))=(NAND(x,y)) . From the previous step, we know

how to implement NOT gate by a NAND gate

AND(x,y)=(NAND(x,y))=NAND(NAND(x,y), NAND(x,y))

So,AND gate can be implemented by only using NAND gates

Since we can implement AND and NOT by only NAND gates,

{NAND, NOR} is a universal set,even without NOR gate.


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Universal Logic Gate NAND Function NAND ::= Negative AND

Y = ( A B )

NOT

OR

AND

YINVAA Y

AB

A

BAND 2Y Y

OR 2BY

AY

A

B

=

=

=

NAND 2 Y Y

A

BA

YA A

NAND 2BY YNAND 2BB

A

ANAND 2

ANAND 2B

Y

YANAND 2B

Y

A

BY

B


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Universal Logic Gate NOR Function

NOR ::= Negative ORY = ( A + B )

NOT

OR

AND NOR 2

YINV

AA Y

AB

A

BAND 2Y Y

OR 2BY

A

YA

B

=

=

=

A

NOR 2BY

YA

AA

NOR 2BY

YANOR 2B

Y

A

BY

B

YA A

NOR 2BY YNOR 2BB

A

U i l L i G


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Universal Logic Gate

Multiplexor Function Multiplexor

Y = A S + B S

NOT OR AND

Y

Y

A

Y

V C C

G N D

G N D

G N DG N D

YS 1 S 0

YD 0

D 1

D 2

D 3

D 0

D 1

D 2

D 3

M X 4 M X 4M X 4

A

B

Y

Y

Y

Y

V C C

S 1 S 0

V C C

YD 0

D 1

D 2

D 3

S 1 S 0

Y

A

B

Y

Y


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Basic Data Processing Circuits


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Decoder (3:8)


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2-4 line Decoder with Enable Input


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Problems using Decoder

Q. Implement 4:16 Decoder using two 3:8 Decoders

Q. Realize a full adder using one 3:8 decoder &

residual gates


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4:16 Decoder using 3:8 Decoder


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Full Adder using Decoder


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Problems using Decoder

Q. Design BCD to decimal

with false data rejected

with false data accepted


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Encoder

Decimal-to-BCD Encoder

Octal-to-Binary Encoder

Limitations


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Q. Realize the following using only one 2:1 Mux

1. NOT

2. And2

3. OR2

4. Ex-or2

5. Ex-nor2

6. Latch

Problems


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Q. 1. Realize the function F(A,B,C,D)=m(1,2,3,6,8,9,11,14)

using an 8-to-1 MUX with control inputs A,B, and C.

2. Repeat Q.1 with control inputs A,C, and D.

3. Repeat Q.1 using a 4-to-1 MUX and added gates.

Problems


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Q1. Design a sequence generator that generates

the sequence 11100011.

Q2. Design 1:8 demultiplexer using two 1:4demultiplexers.

Q3. Implement the following boolean function

using 8:1 MUX,

F(A,B,C,D) = (0,1,3,4,8,9,15)

Problems


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Buffer

A Buffer is a logic circuit which has one I/p line &

one output line. It is a current amplifier & also called as driver.


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Tri-State Buffer

Q. Implement a 2-to-1 Mux with Tri-state buffers


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Answer 2-1 line Mux

Or

2-1 line Mux with Tri-state buffer


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Combinational.

Output depends only on current input values.

Sequential.

Output depends on current input values and

present state of the circuit, where the present

state of the circuit is the current value of thedevices memory.

Sequential circuits


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Bistable Elements The simplest sequential circuit.

It consist of a pair of inverters connected as

shown below. Notice the feedback loop.


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Digital Analysis

Two stable states.

If Q is HIGH then the lower inverter has a HIGH at its

input and a LOW at its output. This in turn forces the

upper inverters input to be LOW and its output to beHIGH.

If Q is LOW then the lower inverter has a LOW at its

input and a HIGH at its output. This in turn forces

the upper inverters input to be HIGH and its output

to be LOW.


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Latches and Flip-Flops Binary cells capable of storing 1 bit of

information.

Generates one of two possible stable states.

Two outputs labeled Q and Q.

One or more inputs.

These sequential devices differ in the way

their outputs are changed:

The output of a latch changes independent

of a clocking signal.The output of a flipflop changes at specific

times determined by a clocking signal.


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SR Latch with Control Input


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D Latch

This latch eliminates the problem thatoccurs in the SR latch when R=S=0.

C is an enable input:

When C=1 then the output follows theinput D and the latch is said to be open.

Due to this fact this latch is also calledtransparent latch.

When C=0 then the output retains itslast value and the latch is said to beclosed.


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Edge Triggered D Flip-Flop

This flip-flop is made out of two D latches. The first latch is

the master, and the second the slave.

When CLK_L= 1 the master is open and the slave is closed.

Qm and Dsfollow Dm.


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Edge Triggered D Flip-Flop

When CLK_L= 0 the master is closed, the slave is open and

Qm is transferred to Qs . Note that Qs does not change if Dm

changes because the master latch is closed leaving Qm fixed.


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JK Flip Flop


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Excitation table of Flip Flops


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Flip Flop to Flip Flopconversions


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FFFF conversions

1. D-T D=TQ

2. T-D T=DQ

3. D-JK D=QJ+QK4. D-SR

5. T-SR

6. JK-SR

7. SR-JK


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D from JK Flip Flop


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Sequential Circuit Example


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Problems

Q. Design a circuit that generates two waveforms of 90 phase shift.

Q. Design a 50% duty cycle frequency doubler for an input

clk pulse of 50% duty cycle.

More Problems, Many more Problems. Let us continue!


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Timing Issues


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Timing Issues Timing parameters

Timing diagram

Set up time Hold time

Clock Skew

Slack

Critical path

Maximum Frequency of Operation


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Timing parameters


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Timing diagram


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Setup and Hold Time

Setup and hold time define a window of time which the D input must be

valid and stable in order to assure valid data on the Q output.

Setup Time (Tsu)Setup time is the time that the D input must be valid before the

Flip-Flop samples.

Hold Time (Th)Hold time is the time that D input must be maintained valid after the

Flip-Flop samples.

Propagation Delay (Tpd)Propagation delay is the time that takes to the sampled D

input to propagate to the Q output.


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FF1 FF2

Q1Q2

CLOCKD

A LONG SLOW PATH

IN

CLK

Clock Skew

Synchronous systems using edge triggered flip-flops work

properly only if all flip-flops see the triggering edge at the

same time.

The difference between arrival times of the clock at different

devices is called clock skew.


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Slack

At each node is a group of events

modeling signal transitions

Arrival Time (AT) - when the signal arrives

AT

D Q

QB

RT

Required Time (RT) - when the signal is needed

SLEW

Slew (SLEW) - time for signal transition from logic levels


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Slack

AT RT

SLEW

Q. Am I meeting timing at this node?

SLACK= RT-AT

+SLACK

Timing is met when slack is greater than or equal to zero


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Maximum Operating Frequency


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Recap

Shift registers: SISO, PISO, PIPO, SIPO

Shift register counters- ring counters and twisted ring counters

Asynchronous/ synchronous counters


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Interesting Problems:

Q1. Design a divide-by-3 counter with 50% duty cycle?


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Interesting Problems: contd

Q2. Design a divide-by 1.5 counter?

Q3. Design a black box whose input clock and

output relationship as shown in diagrambelow.


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Topics

FSM Basics

Types of Machines

Example Designs


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Finite state machinesare so named because the sequentiallogic that implements them can be in only a fixed numberof possible states.

FSM is a systematic way of specifying anysequential logic.

Ideally suited for complex sequential logic.

Finite State Machines

What is an FSM?


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What is an FSM?Design Specification Point of View

State machines are a means of specifyingsequential circuits which are generally

complex in their transition sequence and depend on several control inputs.

What is an FSM?


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What is an FSM?Digital Circuit Point of View

State machines are a group of flip-flops, whose

group-state transition pattern from one set of

values to another and depends on several controlinputs


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Mealy Machine

The outputs depend on the current state andthe present value of the inputs.

Mealy outputs are asynchronous and canchange in response to any changes in theinputs, independent of the clock.

Glitches-How to avoid?

Require less no. of states compared toMoore Machine.


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Moore Machine

The outputs depend only on the present

state.

The outputs are computed by acombinational logic block whose only

inputs are the flip-flops' state outputs

The outputs change synchronouslywith thestate transition and the clock edge.

Finite state machine


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Finite state machine

FSM Structure:-

. State register

- Stores current state

. Next state decoder logic (A)

- Decides next state based oncurrent state and inputs

. Output logic (B)

-Decodes state (or states and

inputs) to produce outputs

.Outputs from the FSM can be a

function of:

- Current state only (moore)

- Current state and the current

inputs (Mealy)

A B

A B

c1k

c1k Moore FSM

Mealy FSM


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FSM Design examples

Q1. Design a circuit that asserts its single output

whenever its input string has two 1's in

sequence.

Cases:

(i) Non-overlapping

(ii) Overlapping of sequence


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FSM Design examples

Q2. Assume a stream of 50k bits are given to the

circuit whose output Z=1 when no. of 1`s in

50k bits are odd else Z = 0. Design thecircuit. (using Mealy machine)


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FSM Design examples

Q3. Design a circuit to detect a sequence 010 and1001

(i) non-overlapping(ii) overlapping

usingMealy machine or Moore.


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FSM Design examples

Q4. A sequential circuit accepts two i/p`s X & Yand generates an o/p Z = 1 whenever the i/p`sare equal for consecutive 4 clock cycle.Design a Mealy machine.(check overlapping)

Note:If any state machine has ninputs, no.of arrows leaving the state will be 2n.


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FSM Design examples

Q6. A sequential circuit has one I/p and one o/p. when

I/p sequence 110occurs the o/p becomes 1 and

remains 1 until the sequence 110 occurs inwhich case the o/p returns to zero. The output

remains zero until 110 occurs the third time.

Draw the state diagram and state table.


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Problems, more problems

Q. Design a pulse train generator circuitusing shift register for the following pulse

train: 1 0 0 0 1 1 0

Next Question: Now can you design a circuit togenerate a specified waveform.


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Introduction Memories


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Classification

MEMORY

RAM HYBRID ROM

SRAM

DRAM

FLASH

EEPROM

PROM

EPROM

MASKED


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Memory array architecture


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Latch and Register based Memory


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A


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RAM

Types : SRAM & DRAM

Primary difference: lifetime of the data they

store. Which to choose & on what basis?

Speed, Area & Cost.


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ROM

Types : MASKED, PROM & EPROM

They are class of PLD s.

Distinguished by the methods used to write new

data to them (usually called programming) and

the number of times they can be rewritten.


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ROM

MASKED : Programmed by manufacturer.

PROM : One time programmable.

EROM : Erased & re-programmable again & again.

PLD s


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PLD s

ROM


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ROM


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ROM


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ROM

HYBRID


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HYBRID

Combine features of both

EEPROM: Once written, the new data will remainin the device forever--or at least until it iselectrically erased.

FLASH: The major difference is that flash devicescan only be erased one sector at a time, not byte-

by-byte as in EEPROM.


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C i i


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Comparison: memoriesType Volatile Writeable Erase Size Cost(per Byte) Speed

SRAM Yes Yes Byte Expensive Fast

DRAM Yes Yes Byte Moderate Moderate

Masked

RAM No No N/A Inexpensive Fast

PROM No Only once N/A Moderate Fast

EPROM No Yes Entire Chip Moderate Fast

EEPROM No Yes Byte Expensive Fast

FLASH No Yes Sector Moderate Fast


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Digital System and IC Design_sandeppani Ppts