Digital PM Demodulator for Digital PM Demodulator for Brazilian Data Collecting Brazilian Data Collecting

SystemSystemJosé Marcelo L. Duarte – UFRN – Natal, BrazilJosé Marcelo L. Duarte – UFRN – Natal, Brazil

Francisco Mota das Chagas – UFRN – Natal, BrazilFrancisco Mota das Chagas – UFRN – Natal, BrazilManoel J. M. de Carvalho – INPE – Natal, Brazil Manoel J. M. de Carvalho – INPE – Natal, Brazil

ContentsContents

IntroductionIntroduction• BDCS Signal CharacteristicsBDCS Signal Characteristics• Signal Processing SystemSignal Processing System

Split Loop ArchitectureSplit Loop Architecture Loop Filter ProjectLoop Filter Project Phase Detector Low Pass Filters ProjectPhase Detector Low Pass Filters Project ImplementationImplementation SimulationsSimulations Conclusions and Final ConsiderationsConclusions and Final Considerations

IntroductionIntroduction This work describes the design and This work describes the design and

implementation of a digital PM demodulator for implementation of a digital PM demodulator for processing LEO satellite signals from Brazilian processing LEO satellite signals from Brazilian Data Collecting System (BDCS).Data Collecting System (BDCS).

Altera Cyclone II DSP Development Kit, equipped Altera Cyclone II DSP Development Kit, equipped with EP2C70 FPGA, was used for implementation.with EP2C70 FPGA, was used for implementation.

Demodulation is done by second order Digital PLL Demodulation is done by second order Digital PLL (Phase-Locked Loop) with Split-Loop architecture (Phase-Locked Loop) with Split-Loop architecture and –and –ππ to + to +ππ linear phase detector made by a linear phase detector made by a cartesian to polar converter.cartesian to polar converter.

BDCS Signal CharacteristicsBDCS Signal Characteristics

CarrierCarrier 2.26 GHz2.26 GHz

Our generated IF is 15 MHzOur generated IF is 15 MHz

ModulationModulation PM, ±1.8 radPM, ±1.8 rad

Base BandBase Band 65 to 125 kHz65 to 125 kHz

Maximum Doppler ShiftMaximum Doppler Shift ±60 kHz±60 kHz

Maximum Doppler Maximum Doppler accelerationacceleration

-750 Hz/s-750 Hz/s

Phase noise at carrier Phase noise at carrier frequencyfrequency

-30 to -20 dBc/Hz-30 to -20 dBc/Hz

Signal Processing SystemSignal Processing System

DPLL Standard ArchitectureDPLL Standard Architecture

Split Loop ArchitectureSplit Loop Architecture

In standard PLL architecture, delay is In standard PLL architecture, delay is present in both proportional and integral present in both proportional and integral action possibly causing instabilities.action possibly causing instabilities.

Split-Loop (Gustrau and Hoffmann, 99) is a Split-Loop (Gustrau and Hoffmann, 99) is a second order PLL architecture where the PI second order PLL architecture where the PI loop filter is divided into proportional and loop filter is divided into proportional and integral parts, making two loops. integral parts, making two loops.

Split-Loop ArchitectureSplit-Loop Architecture

Split-Loop ArchitectureSplit-Loop Architecture

Since the integral output varies Since the integral output varies slowly, phase delay due to low pass slowly, phase delay due to low pass filtering on this signal is negligible. filtering on this signal is negligible. Thus, Split-Loop architecture is less Thus, Split-Loop architecture is less affected by phase detector low pass affected by phase detector low pass filtering delay than the standard filtering delay than the standard architecture. This has allowed use of architecture. This has allowed use of a narrower filter in phase detector, a narrower filter in phase detector, without compromising system without compromising system stability.stability.

Split-Loop Linear ModelSplit-Loop Linear Model

Split-Loop Linear ModelSplit-Loop Linear Model

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Loop Filter Loop Filter ProjectProject Choice of KChoice of KPP and K and KII parameters was made parameters was made

designing an analog second order PLL and designing an analog second order PLL and mapping their poles to the discrete time mapping their poles to the discrete time domain.domain.

Performance specifications chosen:Performance specifications chosen:• Damping Factor (Damping Factor (ξξ) = 1.2;) = 1.2;• Lock Range = 30 kHzLock Range = 30 kHz

PLL Band PLL Band ((ωω3db3db) results 11,17 kHz. ) results 11,17 kHz. Thus, PLL will Thus, PLL will not have dynamic to follow the modulation, so not have dynamic to follow the modulation, so demodulated signal will appear in error signal.demodulated signal will appear in error signal.

Steady state phase error due to Doppler Steady state phase error due to Doppler Effect results Effect results

ΘΘee = 7.6 = 7.6··1010-6-6 rad rad

Phase Detector Low Pass Phase Detector Low Pass Filters ProjectFilters Project

FIR filters with linear phase response were used FIR filters with linear phase response were used to avoid phase deformation;to avoid phase deformation;

Decimation by 16 was done to reduce the number Decimation by 16 was done to reduce the number of necessary taps to implement the filters.of necessary taps to implement the filters.

FIR 1 serves as anti-aliasing filter;FIR 1 serves as anti-aliasing filter; FIR 2 has ±0.5 dB gain region from 0 to 125 kHz FIR 2 has ±0.5 dB gain region from 0 to 125 kHz

and -60 dB gain cut region starting at 240 kHz.and -60 dB gain cut region starting at 240 kHz.

ImplementationImplementation

Software NCO Compiler and FIR Filter Software NCO Compiler and FIR Filter Compiler from Altera were used to Compiler from Altera were used to generate HDL code for NCO and FIR filters generate HDL code for NCO and FIR filters respectively;respectively;

The cartesian to polar converter was The cartesian to polar converter was implemented using CORDIC algorithm implemented using CORDIC algorithm operating on vectoring mode;operating on vectoring mode;

Quartus II software was used to program Quartus II software was used to program the FPGA;the FPGA;

SimulationSimulation

BDCS signal modelBDCS signal model DSP BuilderDSP Builder

• Hardware in the Hardware in the Loop (HIL)Loop (HIL)

CorrelationCorrelation• Delay of 25 usDelay of 25 us

Simulation with SNR = -7.5 dBSimulation with SNR = -7.5 dB

Simulation with SNR = -13.5 dBSimulation with SNR = -13.5 dB

Conclusions and Final Conclusions and Final ConsiderationsConsiderations

Split loop architecture has improved Split loop architecture has improved output SNR and system performance.output SNR and system performance.

Simulations demonstrated that the Simulations demonstrated that the demodulator works as expected, but demodulator works as expected, but improvement need to be done, since improvement need to be done, since the linear operation limit of the DPLL the linear operation limit of the DPLL is being exceeded when input SNR is is being exceeded when input SNR is lower than -10lower than -10 dB dB..