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8/14/2019 Digital Logic Structures Ch3
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Introduction to ComputingSystems and Programming
Digital Logic Structures
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Introduction to Computing Systems and Programming Fall 1384, 3
Basic Logic Operations
Truth Tables of Basic Operations
Equivalent Notations Not A = A = A A and B = A.B = AB = A intersection B
A or B = A+B = AB = A union B
AND
111001
010
000A.BBA
OR
111101
110
000A+BBA
NOT
01
10
A'A
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Introduction to Computing Systems and Programming Fall 1384, 4
More Logic Operations
XOR and XNOR
XOR
011
101
110
000
ABBA
XNOR
111
001010
100
(AB)
BA
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Introduction to Computing Systems and Programming Fall 1384, 5
Logical Operations Example
AND useful for clearing bits
AND with zero = 0
AND with one = no change
OR useful for setting bits
OR with zero = no change
OR with one = 1
NOT unary operation -- one argument flips every bit
11000101
AND 00001111
00000101
11000101
OR 00001111
11001111
NOT 11000101
00111010
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Introduction to Computing Systems and Programming Fall 1384, 6
Simple Switch Circuit
SwitchSwitch openopen::
No current through circuitNo current through circuit
Light isLight is offoff VVoutout isis +2.9V+2.9V
SwitchSwitch closedclosed::
Short circuit across switchShort circuit across switch
Current flowsCurrent flows
Light isLight is onon
VVoutout isis 0V0VSwitch-based circuits can easily represent two states:
on/off, open/closed, voltage/no voltage.
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Transistor
Microprocessors contain millions of
transistors Intel Pentium II: 7 million
Intel Pentium III: 28 million
Intel Pentium 4: 54 million
Logically, each transistor acts as a switch
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N-type MOS Transistor
Gate = 1
Gate = 0Terminal #2 must beconnected to GND (0V).
MOS = Metal Oxide SemiconductorMOS = Metal Oxide Semiconductor
two types: N-type and P-typetwo types: N-type and P-type
N-typeN-type
when Gate haswhen Gate haspositivepositive voltage,voltage,
short circuit between #1 and #2short circuit between #1 and #2
(switch(switch closedclosed))
when Gate haswhen Gate has zerozero voltage,voltage,
open circuit between #1 and #2open circuit between #1 and #2
(switch(switch openopen))
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P-type MOS Transistor
P-type is complementary to N-type when Gate haspositive voltage,
open circuit between #1 and #2
(switch open)
when Gate has zero voltage,
short circuit between #1 and #2
(switch closed)
Gate = 1
Gate = 0Terminal #1 must beconnected to +2.9V.
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CMOS Circuit
Complementary MOS
Uses bothN-type and P-type MOS transistors
P-type Attached to + voltage Pulls output voltage UP when input is zero
N-type Attached to GND Pulls output voltage DOWN when input is one
For all inputs, make sure that output is eitherconnected to GND or to +, but not both!
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Inverter (NOT Gate)
0 V2.9 V
2.9 V0 VOutIn
01
10OutIn
Truth table
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NOR Gate
010
001
1
0
A
01
10
CB
C
A
B
2.9 v
0 v
0 v
P
N
P
N
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Introduction to Computing Systems and Programming Fall 1384, 13
NOR Gate Operation
2.9 v
0 v 0 v
P
N
P
0 v
0 v2.9 v
2.9 v
0 v0 v
N
P
N
2.9 v
2.9 v
0 v
N
0 v 0 v
P
N
P
N
2.9 v
2.9 v
0 v
0 v
P
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Introduction to Computing Systems and Programming Fall 1384, 15
NAND Gate (AND-NOT)
110
101
1
0
A
01
10
CB
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Introduction to Computing Systems and Programming Fall 1384, 16
AND Gate
Add inverter to NAND.
010
001
1
0
A
11
00
CB
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Introduction to Computing Systems and Programming Fall 1384, 17
Basic Logic Gates
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Introduction to Computing Systems and Programming Fall 1384, 18
More Inputs
AND/OR can take any number of inputs. AND = 1 if all inputs are 1.
OR = 1 if any input is 1.
Similar for NAND/NOR.
Can implement with multiple two-input gates,
or with single CMOS circuit.
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Introduction to Computing Systems and Programming Fall 1384, 19
Logical Completeness
Can implement ANY truth table with AND, OR, NOT.
1010
0001
1101
0011
1
0
00
A
010
011
1
0
B
01
00
DC
1. AND combinations
that yield a "1" in thetruth table.
2. OR the resultsof the AND gates.
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Introduction to Computing Systems and Programming Fall 1384, 20
Practice
Implement the following truth table.
101
110
011
0
A
00
CB
001
010
111
0
A
10
CB
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Introduction to Computing Systems and Programming Fall 1384, 21
Summary
MOS transistors are used as switches to implementlogic functions. N-type: connect to GND, turn on (with 1) to pull down to 0
P-type: connect to +2.9V, turn on (with 0) to pull up to 1
Basic gates: NOT, NOR, NAND Logic functions are usually expressed with AND, OR, and NOT
Properties of logic gates Completeness
can implement any truth table with AND, OR, NOT
DeMorgan's Law
convert AND to OR by inverting inputs and output
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Introduction to Computing Systems and Programming Fall 1384, 22
Logic Structures
We've already seen how to implement truth tablesusing AND, OR, and NOT -- an example of
combinational logic.
Combinational Logic Circuit output depends only on the current inputs
stateless Sequential Logic Circuit
output depends on the sequence of inputs (past andpresent)
stores information (state) from past inputs
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Introduction to Computing Systems and Programming Fall 1384, 23
Decoder
n inputs, 2n outputs exactly one output is
1 for each possibleinput pattern
1, iff A,B is 00
A
B
1, iff A,B is 01
1, iff A,B is 10
1, iff A,B is 11
i = 0
i = 1
i = 2
i = 3
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Introduction to Computing Systems and Programming Fall 1384, 24
Multiplexer
n-bit selector and 2n inputs, one output output equals one of the inputs, depending on
selector
4-to-1 MUX
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Introduction to Computing Systems and Programming Fall 1384, 26
Full Adder
Add two bits and carry-in,
produce one-bit sum and carry-out.
10110
01001
10101
10011
1
1
1
0
S
1
1
0
0
B
010
000
1
0
A
11
00
Cout
Cin
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Introduction to Computing Systems and Programming Fall 1384, 27
Four-bit Adder
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Introduction to Computing Systems and Programming Fall 1384, 28
Combinational vs. Sequential
Combinational Circuit always gives the same output for a given set of inputs
ex: adder always generates sum and carry,regardless of previous inputs
Sequential Circuit stores information output depends on stored information (state) plus input
so a given input might produce different outputs,depending on the stored information
example: ticket counter advances when you push the button output depends on previous state
useful for building memory elements and state machines
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Introduction to Computing Systems and Programming Fall 1384, 29
R-S Latch
If both R and S are one, out could be either
zero or one. quiescent state -- holds its previous value
note: if a is 1, b is 0, and vice versa
1
0
1
1
1
1
0
0
1
1
0
0
1
1
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Introduction to Computing Systems and Programming Fall 1384, 30
Clearing the R-S latch
Suppose we start with output = 1, then
change R to zero.
Output changes to zero.
1
0
1
1
1
1
0
0
1
0
1
0
0
0
1
1
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Introduction to Computing Systems and Programming Fall 1384, 31
Setting the R-S Latch
Suppose we start with output = 0, then
change S to zero.
Output changes to one.
1
1
0
0
1
10
1
1
1
0
0
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Introduction to Computing Systems and Programming Fall 1384, 33
Gated D-Latch
Two inputs: D (data) and WE (write enable) when WE = 1, latch is set to value of D
S = NOT(D), R = D
when WE = 0, latch holdsprevious value S = R = 1
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Introduction to Computing Systems and Programming Fall 1384, 34
Register
A register stores a multi-bit value. We use a collection of D-latches, all controlled by a
common WE.
When WE=1, n-bit value D is written to register.
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Introduction to Computing Systems and Programming Fall 1384, 35
Memory
Now that we know how to store bits, we can build
a memory a logical k m array of stored bits.
k= 2n
locations
m bits
Address Space:
number of locations(usually a power of 2)
Addressability:
number of bits per location(e.g., byte-addressable)
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Introduction to Computing Systems and Programming Fall 1384, 36
Address Space
n bits allow the addressing of 2n memory
locations. Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations).
If each location holds 1 byte then the memory is 16MB.
If each location holds one word (32 bits = 4 bytes) then it
is 64 MB.
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Introduction to Computing Systems and Programming Fall 1384, 37
Addressability
Computers are either byte or word addressable - i.e. each
memory location holds either 8 bits (1 byte), or a full standard
word for that computer (typically 32 bits, though now manymachines use 64 bit words).
Normally, a whole word is written and read at a time:
If the computer is word addressable, this is simply a single address
location.
If the computer is byte addressable, and uses a multi-byte word, then the
word address is conventionally either that of its most significant byte (big
endian machines) or of its least significant byte (little endian machines).
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Introduction to Computing Systems and Programming Fall 1384, 38
Memory Structure
Each bit is a gated D-latch
Each location consists of w bits (here w = 1)
w = 8 if the memory is byte
addressable
Addressing n locations means log2n address
bits (here 2 bits => 4 locations)
decoder circuit translates
address into 1 of n addresses
WE
A[1:0] D
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Introduction to Computing Systems and Programming Fall 1384, 39
A2222 by 3 bits memory:by 3 bits memory:
two address lines: A[1:0]two address lines: A[1:0]
three data lines: D[2:0]three data lines: D[2:0]
one control line: WEone control line: WE
One gatedOne gated
D-latchD-latch
Memory example
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Introduction to Computing Systems and Programming Fall 1384, 40
22 x 3 Memory
addressdecoder
word select word WE
address
writeenable
input
bits
output bits
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Introduction to Computing Systems and Programming Fall 1384, 41
Memory details
This is a not the way actual memory is implemented. fewer transistors, much more dense, relies on electrical properties
But the logical structure is very similar. address decoder
word select line
word write enable
Two basic kinds ofRAM (Random Access Memory)
Static RAM (SRAM) fast, maintains data without power
Dynamic RAM (DRAM) slower but denser, bit storage must be periodically refreshed
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Memory building blocks
Building an 8K byte memory using chips that are 2K by 4 bits.Building an 8K byte memory using chips that are 2K by 4 bits.
CS = chip select:
when set, it enablesthe addressing,
reading and writing
of that chip.
This is an 8KB
byte addressable
memory
d
e
c
od
er
CS CS
CS CS
CS CS
CS CS
A10-A0
A12-A11
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits
2K x 4 bits 2K x 4 bits
2K x 4 bits2K x 4 bits