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Memories
Digital Integrated
CircuitsA Design Perspective
Semiconductor
Memories
Memories
Chapter Overview
Memory Classification
Memory Architectures
The Memory Core
Periphery
Reliability
Case Studies
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Semiconductor Memory Classification
Read-Write MemoryNon-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E2PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
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Memory Architecture: Decoders
Word 0
Word 1
Word 2
Word N 2 2
Word N 2 1
Storagecell
M bits M bits
Nwords
S0
S1
S2
SN 2 2
A 0
A 1
A K 2 1
K 5 log2N
SN 2 1
Word 0
Word 1
Word 2
Word N 2 2
Word N 2 1
Storagecell
S0
Input-Output(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signalsK = log2N
Decoder reduces the number of select signals
Input-Output(M bits)
Decoder
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Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing torail-to-rail amplitude
Selects appropriateword
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Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks2. Block address activates only 1 block => power savings
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Read-Only Memory Cells
WL
BL
WL
BL
1WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
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MOS OR ROM
WL[0]
VDD
BL[0]
WL[1]
WL[2]
WL[3]
Vbias
BL[1]
Pull-down loads
BL[2] BL[3]
VDD
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MOS NOR ROM
WL[0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND
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MOS NOR ROM Layout
Programmming using the
Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5 x 7 )
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MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11 x 7 )
Programmming using
the Contact Layer Only
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MOS NAND ROM
All word lines high by default with exception of selected row
WL [0]
WL [1]
WL [2]
WL [3]
VDD
Pull-up devices
BL [3]BL [2]BL [1]BL [0]
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Precharged MOS NOR ROM
PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Precharge devices
BL [2] BL [3]
GND
pref
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Non-Volatile Memories
The Floating-gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_p
tox
tox
Device cross-section Schematic symbol
G
S
D
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Floating-Gate Transistor Programming
0 V
2 5 V0 V
DS
Removing programming
voltage leaves charge trapped
5 V
2 2.5 V5 V
DS
Programming results inhigher VT.
20 V
10 V 5 V 20 V
DS
Avalanche injection
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FLOTOX EEPROM
Floating gate
Source
Substratep
Gate
Drain
n1 n1
FLOTOX transistorFowler-Nordheim
I-V characteristic
20–30 nm
10 nm
-10 V
10 V
I
VGD
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EEPROM Cell
WL
BL
VDD
Absolute threshold control
is hard
Unprogrammed transistor
might be depletion
2 transistor cell
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Flash EEPROM
Control gate
erasure
p-substrate
Floating gate
Thin tunneling oxide
n 1 source n1 drainprogramming
Many other options …
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Characteristics of State-of-the-art NVM
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Read-Write Memories (RAM)
STATIC (SRAM)
DYNAMIC (DRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
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6-transistor CMOS SRAM Cell
WL
BL
VDD
M5M6
M4
M1
M2
M3
BL
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CMOS SRAM Analysis (Read)WL
BL
VDD
M 5
M 6
M 4
M1VDDVDD VDD
BL
Q = 1Q = 0
Cbit Cbit
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CMOS SRAM Analysis (Read)
0
0
0.2
0.4
0.6
0.8
1
1.2
0.5
Voltage rise [V]
1 1.2 1.5 2
Cell Ratio (CR)
2.5 3
Vo
lta
ge
Ris
e (
V)
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CMOS SRAM Analysis (Write)
BL = 1 BL = 0
Q = 0
Q = 1
M1
M4
M5
M6
VDD
VDD
WL
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6T-SRAM — Layout
VDD
GND
WL
BLBL
M1 M3
M4M2
M5 M6
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Resistance-load SRAM Cell
Static power dissipation -- Want R L largeBit lines precharged to VDD to address tp problem
M3
RL RL
VDD
WL
Q Q
M1 M2
M4
BL BL
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SRAM Characteristics
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3-Transistor DRAM Cell
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTn
WWL
BL1
M1 X
M3
M2
CS
BL2
RWL
V DD
VDD 2 VT
D VV DD 2 VTBL 2
BL 1
X
RWL
WWL
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3T-DRAM — Layout
BL2 BL1 GND
RWL
WWL
M3
M2
M1
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1-Transistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
V BL VPRE– VBIT VPRE–CS
CS CBL+------------= =V
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DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.
DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage
is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD
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Sense Amp Operation
D V(1)
V(1)
V(0)
t
VPRE
VBL
Sense amp activatedWord line activated
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1-T DRAM Cell
Uses Polysilicon-Diffusion Capacitance
Expensive in Area
M1 wordline
Diffusedbit line
Polysilicongate
Polysiliconplate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxiden+ n+
Inversion layerinduced byplate bias
Poly
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SEM of poly-diffusion capacitor 1T-DRAM
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Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layerCell plateWord line
Insulating Layer
IsolationTransfer gate
Storage electrode
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Periphery
Decoders
Sense Amplifiers
Input/Output Buffers
Control / Timing Circuitry
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Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
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Hierarchical Decoders
• • •
• • •
A2A2
A 2A3
WL 0
A2A3A2A 3A2A3
A3 A3A 0A0
A0A 1A 0A1A0A1A0A1
A 1 A1
WL 1
Multi-stage implementation improves performance
NAND decoder using
2-input pre-decoders
Memories
Dynamic Decoders
Precharge devices
VDD
GND
WL3
WL2
WL1
WL0
A0A0
GND
A1A1
WL3
A0A0 A1A1
WL 2
WL 1
WL 0
VDD
VDD
VDD
VDD
2-input NOR decoder 2-input NAND decoder
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4-input pass-transistor based column
decoder
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
2-input NOR decoder
A0S0
BL 0 BL 1 BL 2 BL 3
A1
S1
S2
S3
D
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4-to-1 tree based column decoder
Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders
buffersprogressive sizingcombination of tree and pass transistor approaches
Solutions:
BL 0 BL 1 BL 2 BL 3
D
A 0
A 0
A1
A 1
Memories
Decoder for circular shift-register
V DD
V DD
R
WL 0
V DD
f
ff
f
V DD
R
WL 1
V DD
f
ff
f
V DD
R
WL 2
V DD
f
ff
f• • •
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Sense Amplifiers
tp
C V
Iav
----------------=
make V as small
as possible
smalllarge
Idea: Use Sense Amplifer
outputinput
s.a.smalltransition
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Differential Sense Amplifier
Directly applicable to
SRAMs
M 4
M 1
M 5
M 3
M 2
VDD
bitbit
SE
Outy
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Differential Sensing ― SRAMVDD
VDD
VDD
VDD
BL
EQ
Diff.SenseAmp
(a) SRAM sensing scheme (b) two stage differential amplifier
SRAM cell i
WL i
2xx
VDD
Output
BL
PC
M3
M1
M5
M2
M4
x
SE
SE
SE
Output
SE
x2x 2x
y
y
2y
Memories
Latch-Based Sense Amplifier (DRAM)
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.
EQ
VDD
BL BL
SE
SE
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Reliability and Yield
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Noise Sources in 1T DRam
Ccross
electrode
a -particles
leakageCS
WL
BL substrate Adjacent BL
CWBL
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Open Bit-line Architecture —Cross Coupling
SenseAmplifierC
WL 1
BL
CBL
CWBL CWBL
CC
WL 0
C
CBLC C
WL D WL D WL 0 WL 1
BL
EQ
Memories
Folded-Bitline Architecture
SenseAmplifier
C
WL 1
CWBL
CWBL
C
WL 0 WL 0 WL D
CC
WL 1
CC
WL D
BL CBL
BL CBL
EQ
x
x
y
y
…
Memories
Transposed-Bitline Architecture
SA
Ccross
(a) Straightforward bit-line routing
(b) Transposed bit-line architecture
BL 9
BL
BL
BL 99
SA
CcrossBL 9
BL
BL
BL 99
Memories
Alpha-particles (or Neutrons)
1 Particle ~ 1 Million Carriers
WL
BL
V DD
n 1
a -particle
SiO 21
1
1111
22
22
2
2
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Redundancy
MemoryArray
Column Decoder
Row Decoder
Redundantrows
Redundantcolumns
RowAddress
ColumnAddress
FuseBank
:
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Error-Correcting Codes
Example: Hamming Codes
with
e.g. B3 Wrong
1
1
0
= 3
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Redundancy and Error Correction
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Sources of Power Dissipation in
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PERIPHERY
ROW
DEC
selected
non-selected
CHIP
COLUMN DEC
nC DE VINT f
mC DE VINT f
CPTVINT f
IDCP
ARRAY
m
n
m(n 2 1)ihld
miact
VDD
VSS
IDD 5 S C iD V if1S IDCP
From [Itoh00]
Memories
Programmable Logic Array
GND GND GND GND
GND
GND
GND
V DD
V DD
X 0X 0 X 1 f0 f1X 1 X 2X 2
AND-plane OR-plane
Pseudo-NMOS PLA
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Dynamic PLA
GND
GNDVDD
VDD
X 0X 0 X 1 f0 f1X 1 X 2X 2
ANDf
ANDf
ORf
ORf
AND-plane OR-plane
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Semiconductor Memory Trends
(updated)
From [Itoh01]
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Trends in Memory Cell Area
From [Itoh01]
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Semiconductor Memory Trends
Technology feature size for different SRAM generations