Digital ElectronicsIntroduction to VHDL

Few words about the project

The project consists in implementing a real time system on a CPLD coded in VHDL:

• The CPLD is the logic component used for the project (see figure 1).

• The CPLD is soldered on an electronic board which also has leds, input/output pins and2 clocks whose frequency can be modified thanks to 2 potentiometers (see figure 2).

• VHDL is the language used to program the CPLD.

• Real time system = system interacting in real time with a user. In our case, via buttons,the user sends signals to the CPLD and the CPLD sends the appropriate response backto the user using for example leds.

Figure 1: CPLD Figure 2: Carte electronique

1 Programmable logic circuit

A CPLD is a programmable logic circuit, i.e. a logic integrated circuit that can be reconfig-ured after it was made. When the CPLD is programmed from a VHDL code, the CPLD isreconfigured to a logic circuit that behaves as described in the code. Therefore, it’s completelydifferent from a processor.

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As described in the figure 3, with classical languages as Python, MatLab or C, the code iscompiled or interpreted and transformed into machine code stored in the memory. Then, theprocessor executes sequentially the machine code as a list of instructions.

The VHDL code is analysed by a software (like Quartus) that transforms the code intoa logic circuit. This operation is called Synthesis. Then, the programmable logic circuit isreconfigured into the logic circuit described by the VHDL code.

Figure 3: Classical Programming Figure 4: VHDL

How does programmable logic device work ?

We are going to see now how a programmable logic device is reconfigured into the desired logiccircuit.

Let’s suppose that we would like to build a logic circuit that realizes a boolean function:

O = f(I1, I2, ...)

As you’ve seen in the course, this function can be written as a sum of minterms and can besimplified to a smaller sum of products equation (using Karnaugh map for example):

O = product1 + product2 + ...

whose product factors are the inputs and their complement. Therefore, any boolean functioncan be represented as in figure 5.

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Figure 5: Sum of products

For example, the XOR function can be written as:

O = I1 I2 + I1 I2

and the corresponding logic circuit is represented in the figure 6.

Figure 6: XOR logic circuit

PAL 18L8

PALs are the simplest programmable logic circuits. The circuit of the PAL 18L8 is representedin the figure 9. 18L8 means that there are 18 inputs and 8 outputs. Let’s consider the outputO19 in the figure 7. As you can see, the output has the same configuration as the generalcircuit shown in the figure 5 with an additional gate (Three state buffer) at the end that willbe discussed later. The circuit consists in an OR gate whose inputs are the outputs of ANDgates. The inputs of the AND gates are defined by a programmable network. On the verticalchannels of the programmable network, there are the 16 inputs and their complement and thehorizontal channels are the inputs of the AND gates.

Each intersection of the programmable array logic (PAL) can be configured during theprogramming to connect the horizontal and vertical channels as desired to build any logiccircuit. For more explanations, we can find some documentation on the web as https:

//www.geeksforgeeks.org/programming-array-logic/.

In a previous paragraph, it was said that the PAL had 18 inputs and 8 outputs. Actually,it’s not true. The PAL has 10 inputs, 2 outputs (O8 and O1) and 6 pins which can be config-ured either as an input or as an output thanks to a Three State Buffer Gate. As can be seen

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in the truth table of the Three State Buffer in the figure 8, the output can be equal to theinput or to be at high impedance in function of the signal En. High impedance means thatthe output has a floating voltage and the three state buffer acts as an open circuit. There-fore, the I/O canal is configured as an input. Then, the input signal and its complement aretransmitted to programmable array logic to be available for the configuration of the AND gates.

In conclusion, the PAL is a component that can be configured to create a very large numberof different combinational boolean functions.

Figure 7: PAL 18L8

Figure 8: Three State Buffer

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Figure 9: PAL 18L8

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PAL + Macrocell

In order to implement sequential functions, a macrocell is used in combination with a PAL(see figure 10). A macrocell is composed of a register and a multiplexer so that the outputcan be registered if necessary during the program (see figure 11). In function of c1 and c0, themultiplexer selects the input coming either from the register or directly from the PAL.

Figure 10: PAL + Macrocell

Figure 11: Macrocell

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CPLD

A CPLD is the association of several logic elements composed of a PAL and macrocells (figure13) interconnected with a programmable network (figure 12).

For the project, you will use a cpld that includes 160 logic elements. Therefore, there is aperformance constraint and you will be limited in the complexity of your system. It also meansthat you have to optimize the code to minimize the number of logic elements required.

Figure 12: Architecture of a CPLD

Figure 13: Architecture of a logic block

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Pros and Cons

The hardware of a programmable logic device provides advantages but has some flaws comparedwith the classical programming.

Main pros:

• Parallel processing: the hardware allows to perform several tasks at the same time bydifferent logic circuits in the devices. Useful for data conversion, image filtering, ...;

• It can work at high frequency for critical control application;

• Low size and low power consumption.

Main cons:

• Limitation of the complexity application due to the number of logic elements;

• The implementation is generally more complex.

2 VHDL introduction

Since the hardware is completely different from a processor, an adapted language is required.

VHDL (Very High speed integrated circuit hardware Description Language) is a hardwaredescription language designed to describe the behaviour and the architecture of a digital elec-tronic system. Verilog is another hardware description language mostly used in USA. Severalsoftwares are available to code in VHDL and/or verilog:

• Altera Quartus,

• Xillinx ISE,

• Lattice ISP Lever,

• Altium Designer,

• etc.

For the project, Altera Quartus will be used. The most important tools of the soltware to codein VHDL are:

• Text editor to write the code;

• A simulator to test the code;

• An analyser to transform the VHDL code into a logic circuit;

• A Place & Route. This tool does what we saw in the previous section. It configures theprogrammable networks in order to realize the logic circuit given from the analyser.

Therefore, for the project, the first section will not be useful as the software Quartus does allthe job for you. However, understanding how the programmable logic device works may allowyou to better optimize your code.

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3 VHDL Bases

Any VHDL program is composed of at least one inseparable entity/architecture pair.

• The entity describes the Inputs/Outputs of your system.

• The architecture describes the internal operation of the system. It defines how the ouputsare determined in function of the inputs.

Some libraries are available to provided a collection of related data types, functions, etc. Themain libraries are ieee.std logic 1164 for the definition of basic types as bit and ieee.numeric stdfor all the signed and non-signed operations. To include these libraries, write these 3 lines atthe begin of your VHDL code.

Entity

An entity is a specification of the design’s external interface. All the inputs and the outputs ofthe system are specified. For example, the entity of a multiplexer 4 to 1 is described as follow:

The type std logic corresponds to the type of a signal. It will be detailed in a following section.

• mux41 is the name of the entity;

• 6 inputs are specified as type std logic;

• Y is the only output of type std logic.

Architecture

An architecture is a specification of the design’s internal implementation.

The VHDL code describes a logic circuit. Therefore, all statements are per-formed in parallel (”at the same time”). The order of the instructions has noinfluence on the result.

There are 3 different types of statement:

• Assignment statement,

• Structural Description,

• Process Statement.

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Assignment Statements

The assignment statement defines the signal’s value thanks to a logic or mathematical expression

First example: Boolean equation

The architecture of the entity mux 41 is defined with a boolean equation. The value of theoutput Y is determined in function of the 6 inputs. However, it can be very messy to describethe behaviour of a system using boolean equations.

Second example: When-else condition

This implementation realizes exactly the same function as the first example. In this example,a When-else condition is used instead of a boolean equation. The code is more readable andunderstandable. There are a lot of other possible declarations:

• condition case-when,

• condition with-select-then,

• ...

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Structural Description

This type of architecture uses existing component (in another file or library) to create a morecomplex one. For example, we can implement a 3-bits adder with two 2-bits adders. First, let’simplement the 2-bits adder.

I1 and I2 are the inputs and the result of the addition is O2 and O1. Let’s now use the 2-bits adder in the 3-bits adder implementation. The resulting circuit of the following code isrepresented in the figure 14.

Figure 14: Circuit of the structural description of the 3-bits adder

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• A, B and C are the 3 inputs of the 3-bits adder;

• R, S are the result of the addition;

• The 2-bits adder component is first declared before the implementation of the statementsof the architecture;

• S1, S2 and S3 are declared as signal. Signals are used as intermediate values in orderto implement more complex circuits. It’s the closest equivalent to variables in classicalcomputer programming.

• A first 2-bits adder named c1 is initialized thanks to the first statement of the architecture.The assignment of the inputs and outputs of the component follows the order in whichthey appear in the entity i.e. I1 <= A, I2 <= B, O1 <= S1 and O2 <= S2.

• A second 2-bits adder named c2 is initialized.

• The output R is given by the operation S1 OR S3.

Process Statement

Process Statements include a set of sequential statements that assign values to signals. Thesestatements allow you to perform step-by-step computations. The example below uses a processstatement to describe the behaviour of the multiplexer 4 to 1.

• Declaration of the process statement called main.

• The list in the parenthesis after process is called the sensitivity list. A sensitivity listcontains the signals that cause the Process Statements to execute if their value changes.In other words, if a value of a signal in the sensitivity list changes, the process statementis re-evaluated.

• All the statements in a process are interpreted sequentially. Therefore, process statementsallow to implement more complex systems in an easier way. It is this type of declarationthat you will most often use in your project.

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• Although the instructions are interpreted sequentially, the program will analyze the pro-cess to transform it into a set of ”parallel instructions” to be synthesized into a logiccircuit.

Variables vs Signals

In a process, the value assignment of a signal ”occurs at the end of the process”. In other words,the assignment has no effect on the further execution of the process in progress. If you need inyour implementation, a signal that have to be reused in the process after an assignment withthe updated value, you have to use a variable.

A variable has to be declared inside a process statement. It can only be used inside thatprocess. The assignment of a value to a variable is directly effective and accessible in the restof the process.

The following code requires the utilization of two variables tmp1 and tmp2 to convert a8-bits binary number I into a integer O.

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Architecture’s Syntax

The structure of the architecture’s syntax is given in the figure 15. The first part betweenarchitecture and begin is the list of declarations:

• Declarations of new type. We are going to see it later in this introduction that it’s possibleto define new type specific and adapted to your implementation.

• Declarations of signals as seen in a previous example.

• Declarations of constants.

• Declarations of components as seen in a previous example. It allows to initialize a com-ponent in the list of statements.

The second part between begin and end architecture is the list of all statements.

Remember that the statements’ order has no influence. All statements operate in parallel(called concurrent statements).

Figure 15: Architecture’s Syntax

4 Sequential Logic and Synchronous Logic

Reminder:Sequential logic: logic circuit whose output depends not only on the present value of the inputsignals but on the sequence of past inputs.Synchronous logic: logic circuit in which the update of some signal’s values are synchronizedwith a clock signal.

Both requires memorization in the logic circuit. The only statement’s type able to implementmemory is the process statement.

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First example: D Flip-Flop

The D Flip-Flop is a synchronous circuit. A clock is required as an input.

• Only clk is in the sensitivity list since we want the process to be executed only duringthe variations of clk.

• The attribute rising edge allows to update the value of q only during a rising edge of clk.

• An else after a if rising edge condition is forbidden. Indeed, it wouldn’t make any sensesince the rising edge takes place in a very short period of time.

Second example: Latch Transparent

In the Latch transparent, q is updated as long as clk is high.

• Condition on clk, no more rising edge detection.

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Third example: Flip-Flop with asynchronous reset

For the Flip-Flop with asynchronous reset, the input rst has to be added to the sensitivity listsince q must be reset at any time if rst is high. For a synchronous reset, rst is removed fromthe sensitivity list and the condition on the reset is inside the rising edge condition.

5 State Machine

A tool widely used in electronics is the state machine. In class, you saw that the design of astate machine required the following steps:

• defining a state diagram,

• transformation of states into binary codes,

• Karnaugh map,

• determination of boolean equations.

In VHDL, all the optimization processes and the determination of the equations are done byQuartus. The only steps required are

• defining a state diagram,

• implementation by describing the operation of the state machine.

Implementation of a state machine

The implementation of a state machine is composed in 3 parts represented in the figure 16:

• a function to calculate the next state,

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• a function to calculate the outputs,

• a memory to store the current state.

The 3 functions can be implemented in the same process or in different statements.

Figure 16: General State Machine

Example

Let’s consider an example of a state machine whose state diagram is shown in the figure 17.There are 4 states (A, B, C, D), one input P and one output R.

Figure 17: State diagram

The implementation of the state machine entity consists in specify the input P, the outputR and the clock.

For the implementation of the state machine, a new type called states is defined. This typeis a enumeration i.e. the possible values are enumerated in the parenthesis. A signal namedstate of type states is declared and initialized to the value A.

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The implementation of the architecture consists in 2 statements:

• a process statement called update state. In this process, at each rising edge of clk, thestate is updated according to the input P and the previous state.

• a assignment statement to compute the output R in function of the state.

6 Simulation

A simulator is available with Quartus called Modelsim. As the simulator runs on a processorwhile the code is implemented for programmable logic, the code is analyzed and executedsequentially. The simulation works as follow:

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• define the simulation duration,

• define the evolution of the inputs,

• when an input changes at the simulation time t∗, the values of the signals and outputsare evaluated,

• the modifications of the signals and outputs takes place at time t∗+δ (to take into accountthe gate delay).

Thus, modifications are never executed immediately, but are executed after the complete codeanalysis!

During synthesis, on the other hand, everything is executed in parallel. Therefore, therecan be a difference between synthesis and simulation.

7 Syntax Bases

Identifier

The identifier corresponds to the name of signals, inputs, outputs, processes, entities, etc.

• Alphabetic characters, numbers or underscores can be used for an identifier,

• it has to start with an alphabetical character,

• it cannot end with an underscore,

• it cannot contain two successive underscores,

• it is case insensitive,

• some words are forbidden because they have already a function in VHDL like begin,entity, or, ...

Classes

There are 3 different classes: signals, variables and constants. They are defined and used insidea architecture implementation.Syntax:

class identifier : type [:= initial value] ;

Anything between the brackets is not necessary.

Examples:

• constant number players : integer := 4 ;

• signal done : bit := ’0’ ;

• variable index loop : integer range 0 to 127 := 0 ;

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Type and Subtype

You can define a type or subtype to use it in the architecture implementation for any classes.Syntax:

type/subtype identifier is type/subtype definition;

Examples:

• type numbers is range 0 to 4; Definition of the type numbers whose values are between 0and 4.

• type voltage is -3.3 to 3.3; Definition of the type voltage whose values are decimal numbersbetween -3.3 to 3.3.

• subtype bit index is integer range 0 to 31; Definition of the subtype bit index whosevalues are of the type integer but limited in the range 0 to 31.

The advantage of defining new type is to constraint variables or signals to useful values(better resource utilization) and improve the readability of your code.

Enumeration Type

As seen in the state machine example in a previous section, the type enumeration is very usefulto design signals or variables with finite discrete states/values. Syntax:

type identifier is (name1, name2, ...);

Examples:

• type states is (idle, preamble, data, jam, nosfd, error);

• signal current state : states := idle ;

• type days is (Mon, Tue, Wed, Thu, Fri, Sat, Sun);

• signal today : days ;

Predefined type

Basic types are already defined:

• boolean: type boolean is (false, true);

• bits: type bits is (’0’, ’1’);

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• std logic: type std logic is

(’0’, –logic 0’1’, –logic 1’L’, –Weak signal that should probably go to 0’H’, –Weak signal that should probably go to 1’-’, –Don’t care’Z’, –High Impedance’U’, –Uninitialized, this signal hasn’t been set yet’X’, –Unknown, impossible to determine the value’W’, –Weak signal, can’t tell if it should be 0 or 1);

• integer, signed, unsigned, ...

Array Type

Syntax:

type identifier is array (first index to last index) of elements type ;

Examples:

• type code lock is array (0 to 3) of integer range 0 to 9 ;

• constant my code : code lock := (4, 1, 8, 3) ;

bit vector and std logic vector are aleary available in the basic libraries. For example,

signal vect : std logic vector (2 downto 0) := ”011” ;

In this example, s(2) = ’0’ and s(1) = s(0) = ’1’. The indexing would be reversed if to wasused instead of downto.

Multidimensional Array Type

Syntax:

type identifier is array (1st index of the 1st dim to last index of the 1st dim, 1st index of the2nd dim to last index of the 2nd dim, ...) of elements type ;

Examples:

• type table 16x8 is array (0 to 15, 0 to 7) of bit ;

• signal my table : table 16x8 := (”01100110”, ”10101010”, ...) ;

An other way is to define array of arrays such as

type square matrix is array (0 to 7) of std logic vector(0 to 7) ;

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Loop

There are 3 functions to perform a loop in VHDL in a process statement. They can all do thesame thing, but a judicious choice of the type of loop allows a more concise and readable code.

1st possibility:

[loop identifier : ] loop– sequence of statements ;– exit when condition ;– [next when condition ;]

end loop [loop identifier] ;

2nd possibility:

[loop identifier : ] while condition loop– sequence of statements ;– [exit when condition ;]– [next when condition ;]

end loop [loop identifier] ;

3rd possibility:

[loop identifier : ] for identifier in discrete range loop– sequence of statements ;– [exit when condition ;]– [next when condition ;]

end loop [loop identifier] ;

• exit allows to exit the loop,

• next allows to go to the next iteration without executing the following instructions.

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The code below is an example of a 3 to 8 decoder

case-when statement

A very useful statement is the case-when statement.

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8 Project

The objectives of this project is to familiarize you with a programmable logic device (CPLD) anda hardware description language (VHDL). Moreover, you will have to create a simple electroniccircuit for the inputs and the outputs of your application. Usually, the project consists in therealization of a small game but you are free to do something else.

Deadlines

March 29th or before

An email for each group with a brief description:

• project description (5 lines is enough),

• description of the code structure,

• hardware required.

This description will allow me to see if your project is feasible. If not, I will send you somesuggestions.

May 10th

Project report with:

• description of your code structure (block diagram, pseudo-code, ...)

• description of inputs, output, important signals,

• explanations of how your code is operating,

• electrical schematic,

• any other information you deem necessary (simulations, hardware, ...).

One zip file per group with the report and the VHDL code in the format: ELEN0040 name1 2 3 4.zip

Live demonstration

Presentation of your project remotely or face-to-face depending on the situation for about 25minutes. It will take place before the exam session (the exact date will be scheduled later inthe semester). I may ask questions about

• the code (stucture, signals, processes, ...),

• the hardware and the electrical circuit,

• the report (explanations, clarifications, ...).

No questions about anything else than your project (like VHDL syntax or logic programmable).

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How to start your project ?

Before you start coding in VHDL, I advise you to think about some points of your project.

• Think about the required hardware and the number of inputs/outputs needed,

• Think about the different tasks you need to implement for your application,

• Think about the structure of your code. Is it better to implement a state machine orseveral concurrent statements/processes ? Both of them ?

• Start with something simple than you can test and gradually increase the complexity ofyour code. It’s more difficult to debug a VHDL code than a classical language runningon a processor.

The first application that I invite you to realize is a simple test with a button and a led.

Keep in mind that you are not programming, you are describing a logiccircuit !

Example of a simple project: Simon

Simon is a game where the user must reproduce the sequence of colors whose size is incrementedafter each sequence (see figure 18). This game is forbidden for your project as I’m going to useit as an example.

Figure 18: Simon

Required Hardware

• 4 color leds ⇒ 4 outputs

• 4 buttons for each color + one reset ⇒ 5 inputs

• 2 seven-segment displays to display the length of the sequence so far ⇒ 14 outputs

The number of pins required for this configuration is equal to 23. The electronic card has morethan 23 I/O → OK

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Tasks

Several tasks have to be performed for the proper operation of the game:

• random number generator to increment the length of the sequence,

• display the color sequence,

• interpret user commands,

• check if the user sequence is correct,

• display the score.

Code structure

As the game takes place in different phases, a state machine is well adapted. Maybe a taskabove can be implemented in a concurrent statement ? I let you think about that and the statemachine diagram.

Hardware

In the kit provided by the university, you have

• a cpld,

• jumper wire cables,

• leds,

• three 7-segment displays,

• 15 buttons,

• a 5x7 led matrix (TBC20-11EGWA).

A 5x7 led matrix is a component which has 5 rows of 7 leds as shown in the figure 19.

Figure 19: Led matrix

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A 5x7 led matrix has 35 leds. Therefore, the cpld cannot drive them independently becauseit would require too many pins. However, the electric circuit of led matrices allows to reduceconsiderably the number of required inputs.

Let’s consider the schematic of a 8x8 led matrix shown in the figure 20. As you can see, theleds are not driven independently but the led’s anode of the same row are connected to eachother and the led’s cathode of the same column are connected. This configuration only requires16 pins instead of 64.

The trick to be able to display any configurations is to display pixels column by column (orrow by row) at a frequency too fast for the human eye such as all the columns (or all the rows)seem to be displayed at the same time.

At the beginning, only the leds of the first column can be lit. Therefore, the signal on thefirst column is at the low voltage (PIN13 = ’0’) and all the other column’s signals are at thehigh voltage. The signals of the rows of which the leds of the first column must be lit are at thehigh voltage and all the others are at the low voltage. Then, a short moment later, the secondcolumn is ”activated”. The PIN3 is at the low voltage. All the other column are at the highvoltage and the signals of the rows are updated to lit the desired leds on the second column.This continues until the last column and starts again with the first one.

Figure 20: 8x8 led matrix schematic

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For the 5x7 led matrix, it is the same method. The schematic of the electrical circuit isshown in the figure 21 available in the datasheet. For this led matrix, each pixel is composedin 2 leds to be able to display 3 different colors.

Figure 21: 5x7 led matrix schematic

In addition to the kit components, you will have to buy (or retrieve) a breadboard and a9V battery on your own. For your project, you don’t have to use every components and youare free to use other components if you like.

Random Number Generator

For a lot of games, a random number generator is required. There are 2 main options to create arandom variable. A LSFR can generate a pseudo random sequence thanks to a binary equation(I do not recommend this option). The second method is to use an unpredictable externalsignal. For example, the unpredictable time when the user presses a button can be used asfollows:

• a signal is modified on every rising edges of a high frequency clock signal. The signaltakes all the possible random values.

• when the user presses a button, the value of the signal is read and used as a randomvalue.

This method applied for the game Simon works well. A signal varies between 0 and 3 at everyedges of the clock. When the user completes the sequence, the signal is read and the corre-sponding color is added to the current sequence.

9 Reference

For further information about the VHDL and the programmable logic, you can check this bookhttp://www.textfiles.com/bitsavers/pdf/cypress/warp/VHDL_for_Programmable_Logic_

Aug95.pdf

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