YOUNUS INSTITUTE OF TECHNOLOGY KANNANALLOOR P.O KOLLAM

Name...................................

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

First Series Test September 201308.306 DIGITAL ELECTRONICS

Time: 2 Hours Max. Marks: 50Question code: A

Part – A Answer all questions.

1. Enlist the features of combinational logic circuits?2. Draw the logic symbols, output expression and truth tables of the following gates

a) NAND b) NOR c) EXOR d) OR

3. What is a parallel adder and why it is known as a Ripple Carry adder?

4. Simplify the following expressions using a 4 variable KMAP

a) F(ABCD)=∑m(2,3,6,7,8,10,11,13,14) b) F(ABCD)=∑m(2,4,6,8,10,12,15)

5. Obtain the logic implementation and truth table of a JK flip flop and a D flip flop.

` (5 x 4 = 20 Marks)Part – B

Answer any three

6. Solve the following function F(ABCD)=∑m(0,1,6,7,8,9,13,14,15) using Quine McClusky method and draw its logic implementation

7. Design a full adder, write the expressions for sum and carry and implement it in AOI logic as well as NAND logic.

8. Implement the following functions using an 8:1 MUXa. F(ABCD)= ∑m(0,1,3,4,8,9,15)b. F(ABCD)= ∑m(0,1,2,4,6,9,12,14)

9. Explain VHDL and write the VHDL programs for half adder and full adder. 10. Describe shift registers in detail. Draw the logic implementations of SISO, SIPO, PIPO, PISO using

flipflops

(3 x 10 = 30 Marks)

YOUNUS INSTITUTE OF TECHNOLOGY KANNANALLOOR P.O, KOLLAM

Name...................................

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

First Series Test September 201308.306 DIGITAL ELECTRONICS

Time: 2 Hours Max. Marks: 50Question code: B

Part – A Answer all questions.

1. Write a short note on Binary Codes and explain BCD arithmetic.2. What is a Half Adder? Implement a half adder using AOI logic and NAND logic3. What is meant by race around problem in JK Flip Flops?4. Draw the circuit of a BCD Adder.5. Obtain the logic implementation and truth table of an SR flip flop and a T flip flop

` (5 x 4 = 20 Marks)

Part – B Answer any three

1. Realize the following SOP expressions using K Map simplification(a) F(ABCD)= ∑m(0,1,2,3,4,6,8,9,10,11)(b) F(ABC)= ∑m(1,3,4,5,6,7)(c) F(ABCD)= ∑m(0,1,2,4,6,9,12,14)

2. Simplify the function S=∑m(1,2,4,5,6,8,9,12)+d(3,10,13,15) using Quine MuClusky method and implement it using logic gates.

3. State and prove De Morgan’s theorem and simplify the following expressions using De Morgan’s theorem

(a) (A+BC)(AB+ABC)

(b) AB+A+AB4. Explain VHDL and write the VHDL programs for half adder and full adder.5. Write in Detail

(a) Binary number system(b) Hexadecimal number system(c) Octal number system(d) Decimal Number system

(3 x 10 = 30 Marks)