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Digital Electronics and Computer Interfacing
Tim Mewes
3. Digital Electronics
Digital Electronics and Computer Interfacing 2
3.7 Flip-flops
• A flip-flop is a digital circuit that is capable of serving as a one bit memory
• A flip-flop is constructed using gates
• So how could it possibly work?
• But we said that the output of a gate only depends on its inputs and not on its history?!
1
01
No memory – output remains only as long as the inputs are set
• Somehow create a “loop” – called Feedback
Digital Electronics and Computer Interfacing 3
3.7.1 Set/reset flip-flop (SR flip-flop)
• One possible implementation: NAND gate latch
S
R
Q
Q
Digital Electronics and Computer Interfacing 4
3.7.1 Set/reset flip-flop (SR flip-flop)
• Reset of the flip-flop: S=1, R=0
S
R
Q
Q
S Q Q
0 0 1 0 1 1 1 0 1 1 1 0
R Q Q
0 0 1 0 1 1 1 0 1 1 1 0
0
1
1?
00
1
Digital Electronics and Computer Interfacing 5
3.7.1 Set/reset flip-flop (SR flip-flop)
• Set of the flip-flop: S=0, R=1
S
R
Q
Q
S Q Q
0 0 1 0 1 1 1 0 1 1 1 0
R Q Q
0 0 1 0 1 1 1 0 1 1 1 0
1
0
0
?11
0
Digital Electronics and Computer Interfacing 6
3.7.1 Set/reset flip-flop (SR flip-flop)
• What happens when we now change to: S=1, R=1 ?
S
R
Q
Q
S Q Q
0 0 1 0 1 1 1 0 1 1 1 0
R Q Q
0 0 1 0 1 1 1 0 1 1 1 0
0
0
1
10
11
Flip-flop does not change its output ! (latch)
Digital Electronics and Computer Interfacing 7
3.7.1 Set/reset flip-flop (SR flip-flop)
• What happens for: S=0, R=0 ?
S
R
Q
Q
S Q Q
0 0 1 0 1 1 1 0 1 1 1 0
R Q Q
0 0 1 0 1 1 1 0 1 1 1 0
0
?
?
01
1
Both outputs are 1!Q NOT(Q) !!!
Digital Electronics and Computer Interfacing 8
3.7.1 Set/reset flip-flop (SR flip-flop)
• Summary
S
R
Q
Q
Q
R
S0
1
0
1
0
1
S R Q Q
0 0 1 1 0 1 1 0 1 0 0 1 1 1 no change no change
invalid
Timing diagram
Digital Electronics and Computer Interfacing 9
3.7.2 Gated SR flip-flop
• Sometimes also called: Clocked SR flip-flop
S’
R’
Q
Q
E
The input E is called enable input or clock input
Digital Electronics and Computer Interfacing 10
3.7.2 Gated SR flip-flop
• Reset of the gated SR flip-flop: S’=0, R’=1 and E=1
S’
R’
Q
Q
E
0
1
1
1
1
0
S
R
This corresponds to the Reset case (S=1, R=0) of the SR flip-flop (page 4)
Thus: Q=0 and Q=1
0
1
Digital Electronics and Computer Interfacing 11
3.7.2 Gated SR flip-flop
• Set of the gated SR flip-flop: S’=1, R’=0 and E=1
S’
R’
Q
Q
E
1
1
0
1
0
1
This corresponds to the Set case (S=0, R=1) of the SR flip-flop (page 5)
Thus: Q=1 and Q=0
1
0
S
R
Digital Electronics and Computer Interfacing 12
3.7.2 Gated SR flip-flop
• What happens if we now set E=0?
S’
R’
Q
Q
E
1
0
1
1
1
01
0
00
0
1
With E=0 the flip-flop does not change its outputs!
S
R
Digital Electronics and Computer Interfacing 13
3.7.2 Gated SR flip-flop• Summary
Q
R’
S’0
1
0
1
0
1
Timing diagram
E S ’ R ’ Q Q
0 0 0 no change no change 0 0 1 no change no change 0 1 0 no change no change 0 1 1 no change no change 1 0 0 no change no change 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1
S’
R’
Q
Q
E
E 0
1invalid
