Digital Combi Plus Seq Ckt Design

1EECC341 - ShaabanEECC341 - Shaaban#1 Lec # 6 Winter 2001 12-18-2001

Combinational Circuit Analysis ExampleCombinational Circuit Analysis ExampleGiven this logic circuit we can :

• Find corresponding logic expression from circuit• Create truth table by applying all input combinations:

• From truth table find Canonical Sum/Product Representations• Manipulate logic expression to other forms using theorems.

00001111X

Y

Z

00110011

01010101

Y’

11001100

0000111111001111X+Y’

01000101(X+Y’) . Z

01010101

X’ 11110000

Z

00110011Y

10101010Z’

00100000X’. Y. Z’

01100101

F

corresponding logic expression: F = ((X + Y’) . Z) + (X’.Y. Z’)

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1

Truth Table

From truth table:Canonical SumF = ΣΣ X,Y,Z (1, 2, 5,7)

Canonical ProductF = ΠΠ X,Y,Z (0,3,4,6)


Combinational Circuit Analysis ExampleCombinational Circuit Analysis Example(continued)(continued)

• The previous circuit logic expression F can be transformed into sumof products by multiplying out (Using T8’) and written as :

F = X . Z + Y’. Z + X’.Y. Z’

Realized using a 2-level AND-OR circuit:

F = X . Z + Y’. Z + X’.Y. Z’

X

Y

Z

Y’Y’ . Z

X . Z

X’

X’ . Y . Z’Z’


CombinationalCombinational Circuit Analysis Example Circuit Analysis Example(continued)(continued)

• The logic expression F for the previous circuit canadded out (using T8) and written as:

F = ((X+Y’).Z) + (X’.Y.Z’)

=(X+Y’+X’).(X+Y’+Y).(X+Y’+Z’).(Z+X’).(Z+Y).(Z+Z’)

= 1.1.(X+Y’+Z’).(X’+Z).(Y+Z).1

F = (X+Y’+Z’).(X’+Z).(Y+Z)

Realized using 2-level OR-AND circuit.


Equivalent Symbols of NAND, NOR GatesEquivalent Symbols of NAND, NOR Gates

X

Y(X . Y)’

X

YX’ + Y’

X

Y(X + Y)’

X

YX’ . Y’

NAND Symbols

NOR Symbols

According to DeMorgan’s theorem T13: (X . Y)’ = X’ + Y’

Normal Symbol

Normal NOR Symbol

According to DeMorgan’s theorem T13’: (X + Y)’ = X’ . Y’

Alternate NOR Symbol

Alternate NAND Symbol


• A sum of products logic expression can be realized byNAND gates by replacing all AND gates and the OR GATEin the usual realization with NAND gates as follows:

F = A + B + C + D ...

where A, B, C, …. are product terms of the

input variables e.g. A= x.y.z

F = (A’)’+(B’)’+(C’)’+(D’ )’ + …. from T4

= (A’.B’.C’.D’… )’ (from DeMorgan’s theorem T13)

This is a 2-level NAND representation.

NAND-NAND Logic Circuits for Sum of ProductsNAND-NAND Logic Circuits for Sum of Products


Alternate Sum of Products RealizationsAlternate Sum of Products Realizations (Applying(Applying DeMorgan’s theorem T13 Graphically)

AND-OR

NAND-NAND


NAND-NAND Sum of Products ExampleNAND-NAND Sum of Products Example• The sum of products expression

F = X . Z + Y’. Z + X’.Y. Z’

F = ((X . Z)’)’ + ((Y’. Z)’)’ + ((X’.Y. Z’)’)’ double negate T4

F = [(X . Z)’ . (Y’. Z)’ . (X’.Y. Z’)’]’ DeMorgan’s theorem T13

Can be realized using the 2-level NAND-NAND circuit:

F = [(X . Z)’ + (Y’. Z)’ + (X’.Y. Z’)’]’

X

Y

Z

Y’ (Y’ . Z)’

(X . Z)’

X’

(X’ . Y . Z’)’Z’


NOR-NOR Circuits for Product of Sums

• A product of sums expression can be realized by NORgates by replacing all the OR gates and the AND gatewith NOR gates as follows:

F = A.B.C.D. ….

Where A, B, C are sum terms of the input

variables (e.g. A = x+y+z)

F = (A’)’.(B’)’.(C’)’.(D’)’ …. using T4

= (A’ + B’ + C’ + D’ + …)’

(using Demorgan’s theorem T13’)

This is a 2-level NOR-NOR representation


Alternate Product of Sums RealizationsAlternate Product of Sums Realizations (Applying (Applying DeMorgan’s theorem T13’ Graphically)

OR-AND

NOR-NOR


Combinational Circuit Synthesis

• An example of a combinational circuit description:

Create a logic function in 4 input variables N=N3N2N1N0

whose output is 1 only if the input is a prime number.

• This function is 1 when the input N =1,2,3,5,7,11 can bewritten in the canonical sum of products representationas:

F = Σ Σ N3N2N1N0 (1,2,3,5,7,11,13) (1,2,3,5,7,11,13)

= = N3’N2’N1’N0+ N3’N2’N1N0’+ N3’N2’N1N0

+N3’N2N1’N +N3’N2N1N0+ N3N2’N1N0+ N3N2N1’N0


A Verbal Synthesis Example:An Alarm Circuit

• A verbal logic description:– The ALARM output is 1 if the panic input is 1, or if the ENABLE

input is 1, the EXISTING input is 0, and the house is not secure.

– The house is secure if the WINDOW, DOOR, GARAGE inputs are all 1

• This can be put in logic expressions as follows:

ALARM = PANIC + ENABLE . EXISTING’ . SECURE’

SECURE = WINDOW. DOOR. GARAGE

ALARM = PANIC + ENABLE . EXISTING’. (WINDOW . DOOR . GARAGE)’

In sum of products form as (by using DeMorgan T13 and multiplying out) :ALARM = PANIC + ENABLE. EXISTING’ . WINDOW’

+ ENABLE . EXISTING’. DOOR’+ ENABLE. EXISTING’. GARAGE’

EECC341 - ShaabanEECC341 - Shaaban#1 Lec # 7 Winter 2001 12-20-2001

Combinational Circuit Minimization• Canonical sum and product logic expressions do not provide a

circuit realization with the minimum number of gates.

• Minimization methods reduce the cost of two level AND-OR,NAND-NAND, OR-AND, NOR-NOR circuits in three ways:

1 By minimizing the number of first level gates

2 By minimizing the number of inputs of each first-level gate.

3 Minimizing the inputs of the second level gate

• Most minimization methods are based on the combining theoremsT10, T10’:

given product term.Y + given product term.Y’ = given product term

(given sum term+Y).(given sum term + Y’) = given sum term


KarnaughKarnaugh Maps Maps• A Karnaugh Map or (K-map for short) is a graphical

representation of the truth table of a logic function.

• The K-map for an n-input logic function is an array with 2n cells orsquares, one for each input combination or minterm.

• The rows and columns are labeled so that the input combination forany cell is determined from the row and column headings.

• The row and columns of the map are ordered in such a way thateach cell differs from an adjacent cell in only one input variable:

– Thus for an n-variable K-map, each cell has n adjacent cells.

• The K-map for a function is filled by putting:

– a ‘1’ in the square corresponding to a minterm

– a ‘0’ otherwise (maybe omitted)


2-Variable K-map2-Variable K-mapFor a 2-variable logic function F(X,Y):

Row X Y F Minterm 0 0 0 F(0,0) X’.Y’ 1 0 1 F(0,1) X’.Y 2 1 0 F(1,0) X.Y’ 3 1 1 F(1,1) X .Y

Truth Table: K-map

YX

0 1

0

1

X

Y

0 2

1 3

Example: For the function F(X,Y) = ΣΣ X,Y (1,2,3)

Row X Y F 0 0 0 0 1 0 1 1 2 1 0 1 3 1 1 1

Truth Table: K-map

YX

0 1

0

1

X

Y

0 2

1 3

1

11


3-Variable K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

For a 3-variable logic function F(X,Y,Z):

Truth Table:K-mapRow X Y Z F Minterm

0 0 0 0 F(0,0,0) X’.Y’.Z’ 1 0 0 1 F(0,0,1) X’.Y’.Z 2 0 1 0 F(0,1,0) X’.Y.Z’ 3 0 1 1 F(0,1,1) X’.Y.Z 4 1 0 0 F(1,0,0) X.Y’.Z’ 5 1 0 1 F(1,0,1) X.Y’.Z 6 1 1 0 F(1,1,0) X.Y.Z’ 7 1 1 1 F(1,1,1) X.Y.Z

Example: For the function F(X,Y,Z) = ΣΣ X,Y,Z (1,2,5,7)

Truth Table:K-map

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

51

1

1 1


3-Variable K-map (continued)• There is a horizontal adjacency wrap-around in the 3-variable K-map:

For example:– Cell 0 (minterm 0 = X’.Y’.Z’) is adjacent to:

• cell 4 (minterm 4, = X.Y’.Z’) by wrap-around.

• in addition to being adjacent to cells 1, 2 (minterm 1 = X’.Y’.Zminterm 2, = X’.Y.Z’)

– Cell 1 (minterm 1, X’.Y’.Z) is adjacent to:• cell 5 (minterm 5, X.Y’.Z) by wrap-around.

• in addition to being adjacent to cells 0 , 2 (minterm 0 = X’.Y’.Z’minterm 3 = X’.Y.Z)

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5


4-Variable K-map4-Variable K-mapFor a 4-variable logic function F(W,X,Y,Z):

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

Truth Table: K-map

Row W X Y Z F Minterm

0 0 0 0 0 F(0,0,0,0) W’.X’.Y’.Z’ 1 0 0 0 1 F(0,0,0,1) W’. X’.Y’.Z 2 0 0 1 0 F(0,0,1,0) W’. X’.Y.Z’ 3 0 0 1 1 F(0,0,1,1) W’. X’.Y.Z 4 0 1 0 0 F(0,1,0,0) W’. X.Y’.Z’ 5 0 1 0 1 F(0,1,0,1) W’.X.Y’.Z 6 0 1 1 0 F(0,1,1,0) W’.X.Y.Z’ 7 0 1 1 1 F(0,1,1,1) W’.X.Y.Z 8 1 0 0 0 F(1,0,0,0) W.X’.Y’.Z’ 9 1 0 0 1 F(1,0,0,1) W.X’.Y’.Z 10 1 0 1 0 F(1,0,1,0) W.X’.Y.Z’ 11 1 0 1 1 F(1,0,1,1) W.X’.Y.Z 12 1 1 0 0 F(1,1,0,0) W.X.Y’.Z’ 13 1 1 0 1 F(1,1,0,1) W.X.Y’.Z 14 1 1 1 0 F(1,1,1,0) W.X.Y.Z’ 15 1 1 1 1 F(1,1,1,1) W.X.Y.Z


4-Variable K-map (continued)• There are 2 adjacency wrap-arounds in the 4-variable K-map :

a horizontal wrap-around and a vertical wrap-around.

• Every cell thus has 4 neighbours. For example, cell 0 correspondingto minterm 0 is adjacent to: cells 1, 2, 4, 8

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10


4-Variable K-map Example

For the function F(W,X,Y,Z) = ΣΣ W,X,Y,Z (5,7,12,13,14,15)

Truth Table:

Row W X Y Z F

0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 0 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 0 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

1

1 1

1 1

1

K-map


Minimizing Sum of Products using K-maps

• Each input combination with “1” in a Karnaugh map ortruth table correspond to a minterm in the function’scanonical sum representation.

• Pairs of adjacent “1” cells in the Karnaugh map indicateminterms that differ in only one variable.

• Using the generalization of T10, such adjacent mintermpairs can be combined into a single product term.

• In general, one can simplify a logic function by combiningpairs of adjacent 1-cell minterms and writing a sum ofproducts expression to cover all of the 1-cells.


K-Map Minimization Rules and Definitions• A minimal sum of a logic function F(X1, X2, ..Xn) is a sum-of-

products expression for F such that no other similar expressionfor F has fewer product terms, and other expressions with thesame number of product terms have at least the same numberof literals.

• A set of 2i 1-cells are combined into a single square orrectangle if i variables take all 2i possible combinations withinthe set while the remaining variables have the same value.

• The corresponding product term for the combined cells has n-iliterals.

• Only the variables that have the same value appear in theresulting product term:

– A variable in the resulting product term is complemented ifit appears as 0 in all the 1-cells, and uncomplemented if itappears as 1.


Minimization Using K-maps• Group or combine as many adjacent 1-cells as possible:

– The larger the group is, the fewer the number of literals in theresulting product term.

– Each group of combined adjacent 1-cells must have a number ofcells equal to powers of two: 1, 2, 4, 8, …

– Grouping 2 adjacent 1-cells eliminates 1 variable, grouping 4 1-cells eliminates 2 variables, grouping 8 1-cells eliminates 3variables, and so on. In general, grouping 2n squares eliminatesn variables.

• Select as few groups as possible to cover all the 1-cells(minterms) of the function:

– The fewer the groups, the fewer the number of product terms inthe minimized function.


3-Variable K-map Minimization Example• Using K-map, find a minimal sum of products (SOP) expression

expression for the function:

F(X,Y,Z) = ΣΣ X,Y,Z (1,2,5,7)

Truth Table

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1

1

1 1




F(X,Y,Z) = ΣΣ X,Y,Z (1,2,5,7)

Truth Table

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 0 7 1 1 1 1

K-map

Minimum SOP for F = X’. Y . Z’ + X . Z + Y’ . Z

Z

X

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1

1

1 1

X . Z

X’. Y . Z’

Y’ . Z

0

1




F(X,Y,Z) = ΣΣ X,Y,Z (0,1,4,5, 6)

Truth Table

Row X Y Z F 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1

11

1

1




F(X,Y,Z) = ΣΣ X,Y,Z (0,1,4,5, 6)

Truth Table

Row X Y Z F 0 0 0 0 1 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1

11

1

1

Minimum SOP for F = Y’ + X . Z’

Y’

X . Z’




F(N3,N2,N1,N0) = ΣΣ N3,N2,N1,N0 (1,2,3,5,7,11,13)

Truth Table:Row W X Y Z F

0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0

N1

N3

00

01

11

10

00 01 11 10

N2

N1 N0

N3 N2

N0

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

K-map

1 1

1 1

1

1

1




F(N3,N2,N1,N0) = ΣΣ N3,N2,N1,N0 (1,2,3,5,7,11,13)

Truth Table:Row W X Y Z F

0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0

N1

N3

00

01

11

10

00 01 11 10

N2

N1 N0

N3 N2

N0

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

K-map

1 1

1 1

1

1

1

N3’.N2’.N1

N2 . N1’. N0N3’. N0

N2’ . N1 . N0

Minimum SOP for F = N3’. N0 + N3’. N2’ . N1 + N2’. N1 . N0 + N2 . N1’.N0


K-Map Minimization Rules and Definitions

• A logic function P(X1, X2, ..Xn) implies a logic function F(X1, …, Xn)if for every input combination such that P=1, then F=1 (F includesP , or F covers P).

• A prime implicant of a logic function F(X1, ..Xn) is a normal productterm P(X1, ..Xn) that implies F, such that if any variable is removedfrom P, the the resulting product term does not imply F.

• A minimal sum is a sum of prime implicants (not necessarily all ofthem).

• A distinguished 1-cell of a logic function is an input combination thatis covered by only one prime implicant.

• An essential prime implicant of a logic function is a prime implicantthat covers one or more distinguished 1-cells and must be includedevery minimal sum expression for the function.




F(W,X,Y,Z) = ΣΣ W,X,Y,Z (2,3,4,5,6,7,11,13,15)

• Also identify all prime implicants, distinguished 1-cells and thecorresponding essential prime implicants that cover them.

Y

W

00

01

11

10

00 01 11 10

X

YZ

WX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

1

1

1 1

11

K-map

1

1

1


4-Variable K-map Minimization Example• Using K-map, find a minimal sum of products (SOP) expression expression for the

function: F(W,X,Y,Z) = ΣΣ W,X,Y,Z (2,3,4,5,6,7,11,13,15)

• Also identify all prime implicants, distinguished 1-cells and the correspondingessential prime implicants that cover them.

K-map

Y

W

00

01

11

10

00 01 11 10

X

YZ

WX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

1

1

1 1

11

1

1

1

W’.X

Y . Z

X . Z

W’ . Y

From K-map:

Prime Implicants:

W’. Y W’ . X Y . Z X . Z

Distinguished 1-cells:

Cell 2 covered by W’ . YCell 4 covered by W’ . XCell 11 covered by Y . ZCell 13 covered by X . Z

Here all prime implicants areessential prime implicants and all of them must be included in minimum SOP expression:

F = W’ . Y + W’. X + Y . Z + X . Z


Minimization with Don’t care Input Combinations

• In some cases, the output of a combinational circuitdoesn’t matter for certain input combinations.

• Such combinations are called don’t cares and the outputis represented in the truth table and K-maps as “d”.

• When using K-maps to minimize such functions:

– Allow d’s to be included when circling sets of 1’s tomake the sets as large as possible.

– Do not circle any set that only contains d’s.


• Using K-map, find a minimal sum of products (SOP) expression for prime BCD-digit detector which gives 1 when the input BCD digit is prime,

• Since the values 10-15 do not occur in a BCD digit minterms 10-15 are treated asdon’t cares giving the expression:

F(N3,N2,N1,N0) = ΣΣ N3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15)

4-Variable K-map Minimization Example With Don’t cares4-Variable K-map Minimization Example With Don’t cares

N1

N3

00

01

11

10

00 01 11 10

N2

N1 N0

N3 N2

N0

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

1 1

1 1

d

1

d

d

d

d

d

From K-map:

Prime Implicants:

N3’. N0 N2’. N1 N2 . N0

Distinguished 1-cells:

Cell 1 covered by N3’. N0 Cell 2 covered by N2’. N1

Here not all prime implicants areessential prime implicants thatmust be included minimum SOP expression:

F = N3’ . N0 + N2’ . N1

N2 . N0

N2’. N1

N3’. N0


K-map Minimization of Product of Sums• Similar to K-map minimization of sum of products by

using duality and looking at 0-cells instead of 1-cells.

• A set of 2i 0-cells may be combined if i variables take all 2i

possible combinations within the set while the remainingvariables have the same value.

• In the resulting n-i literals sum term, a variable iscomplemented if it appears as 1 in all the 0-cells, anduncomplemented if it appears as 0.

• A prime implicate of a logic function F(X1, ..Xn), is a normal

sum term S(X1, ..Xn) implied by F, such as if any variable isremoved from S, then the resulting sum term is notimplied by F.

• A minimal product is a product of prime implicates.


K-map Product of Sums Minimization Example 1

• Using K-map, find a minimal product of sums (POS) expressionexpression for the function:

F(X,Y,Z) = ΠΠ X,Y,Z (0,3,4,7)

Truth Table

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

0

0

0

0


K-map Product of Sums Minimization Example 1

• Using K-map, find a minimal product of sums (POS) expressionexpression for the function:

F(X,Y,Z) = ΠΠ X,Y,Z (0,3,4,7)

Truth Table

Row X Y Z F 0 0 0 0 0 1 0 0 1 1 2 0 1 0 1 3 0 1 1 0 4 1 0 0 0 5 1 0 1 1 6 1 1 0 1 7 1 1 1 0

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

0

0

0

0

(Y + Z)

(Y’ + Z’)

Minimum POS for F = (Y + Z) . (Y’ + Z’)


K-map Product of Sums Minimization Example 2• Using K-map, find a minimal product of sums (POS) expression


F(W,X,Y,Z) = ΠΠ W,X,Y,Z (1,3,8,10,12,13,14,15)

W

K-map

Y

00

01

11

10

00 01 11 10

X

YZ

WX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

0 0

0

0

0 0

0

0


K-map Product of Sums Minimization Example 2• Using K-map, find a minimal product of sums (POS) expression


F(W,X,Y,Z) = ΠΠ W,X,Y,Z (1,3,8,10,12,13,14,15)

K-map

W

Y

00

01

11

10

00 01 11 10

X

YZ

WX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

0 0

0

0

0 0

0

0

(W + X + Z’)

(W’ + X’)

(W’ + Z)

Minimum POS for F = (W + X + Z’) . (W’ + Z) . (W’ + X’)


5-variable K-maps• The K-map for a 5-variable logic function F(V,W,X,Y,Z) is

organized as two 4-variable K-maps:

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

V = 0 V = 1

Corresponding squares of each map are adjacent.Can be visualised as being one 4-variable map on top of another 4-variable map.


5-Variable K-map SOP Minimization Example• Using K-map, find a minimal sum of products (SOP) expression


F(V,W,X,Y,Z) = ΣΣ V,W,X,Y,Z (4,5,6,7,9,11,13,15,25,27,29,31)

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

V = 0 V = 1

1

1

1

1

1 1 1

1 11

1

1

K-map


5-Variable K-map SOP Minimization Example• Using K-map, find a minimal sum of products (SOP) expression


F(V,W,X,Y,Z) = ΣΣ V,W,X,Y,Z (4,5,6,7,9,11,13,15,25,27,29,31)

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

V = 0 V = 1

1

1

1

1

1 1 1

1 11

1

1

K-map

V’ . W’. X W . Z

Minimum SOP for F = V’ . W’. X + W . Z


6-variable K-maps K-map for a 6-variable logic function F(U,V,W,X,Y,Z)

is organized as two 5-variable K-maps:

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

16

17

19

18

20

21

23

22

28

29

31

30

24

25

27

26Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

0

1

3

2

4

5

7

6

12

13

15

14

8

9

11

10

U,V = 0,0 U,V = 0,1

Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

48

49

51

50

52

53

55

54

60

61

63

62

56

57

59

58Y

W

00

01

11

10

00 01 11 10

X

YZWX

Z

32

33

35

34

36

37

39

38

44

45

47

46

40

41

43

42

U,V = 1,0 U,V = 1,1


Combinational Logic Circuit Transient Vs. Steady-state Output• Gate propagation delay: The time between an input change and the

corresponding change of the output.

• Circuit steady-state output: The output is evaluated when the inputs havebeen stable for a long time relative to the gate delays.

• Circuit transient output behavior: The circuit output when one or moreinputs change values.

• Example: For an inverter with propagation delay, ∆∆ when input changesfrom 1 to 0:

• The circuit analysis done so far ignores propagation delays and considers onlysteady-state output when all propagation delays have completed though all thecircuit gates.

X X’

1

0

1

0

Time

X

X’

∆∆

((propagation delay)

Steady-state outputTransient output

1 → 0

Timing Diagram


• Output glitch: A momentary unexpected transient output change (shortpulse) when an input changes and usually caused by gate propagationdelays.

• Hazards: A hazard exists in a combinational circuit when it produces anoutput glitch when one or more inputs change.

• Types of combinational logic hazards:

• Static Hazards:– Static-1 Hazard: The output should be 1 but goes momentary to 0 as a result of

an input change. (possible in AND-OR circuits)

– Static-0 Hazard: The output should be 0 but goes momentary to 1 as a result ofan input change. (possible in OR-AND circuits)

• Dynamic Hazards: The output changes more than once as a result of asingle input change (impossible in 2-level circuits).

• Static hazards can be detected and eliminated for 2-level logic circuitsusing K-maps.

Combinational Logic Hazards

11

0

1

0 0

Static-1 HazardStatic-0 Hazard

1

0 0

Dynamic Hazard Example

1


Example: Circuit with Static-1 Hazard• A static-1 hazard exists in the following AND-OR circuit when X = 1, Y = 1

and Z changes from 1 to 0 (assume all gates have propagation delay ∆∆ ):

X

Z

Y

Z’X . Z’

Y . Z

F1 → 0

1

1

0 → 1

1 → 0

Timing Diagram

10

10

Time

Z

Z’∆∆

∆∆Y. Z’

10

10

Y. Z

∆∆10

F

Steady-state output

Circuit

K-map

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1 1

1 1

Y . Z

X . Z’

1 → 0 → 1


Eliminating Static-1 Hazards Using K-maps• A static-1 hazard occurs in AND-OR circuits when an input variable

and its complement are connected to two different AND gates.

• Static-1 hazards are found using k-maps by finding adjacent 1 cells thatare covered by different product terms.

• To eliminate static-1 hazards, additional product terms (primeimplicants) are needed to cover such cells thus covering the transition ofthe variable causing the hazard.

• For in the previous example the static-1 hazard is eliminated byincluding the additional product term X . Y

Z

X

0

1

00 01 11 10

Y

Z

XY

0

1

2

3

6

7

4

5

1 1

1 1

X. Y

X . Z’

Y . Z

New F = X . Z’ + Y . Z + X. Y

X

Z

Y

Z’X . Z’

Y . Z

FX . Y

Circuit with static-1 hazard eliminated


Eliminating Static-0 Hazards Using K-maps

• A static-0 hazard occurs in OR-AND circuits when an input variableand its complement are connected to two different OR gates.

• The procedure to find and eliminate static-0 hazards using K-maps isdone in a dual way to finding static-1 hazards.

• Static-0 hazards are found using k-maps by finding adjacent 0 cells thatare covered by different sum terms.

• To eliminate static-0 hazards, additional sum terms (prime implicates)are needed to cover such cells thus covering the transition of thevariable causing the hazard.


Combinational Logic Building Blocks

• Decoders:– Binary n-to-2n decoders.

– Implementing functions usingdecoders.

• Encoders:– 2n -to-n binary decoders.

• Three-State Buffers.

• Multiplexers.

• Demultiplexers


DecodersDecoders• A decoder is a multiple-input, multiple-output logic

circuit that converts coded inputs into coded outputs,where the input and output codes are different.e.g. n-to-2n, BCD decoders.

• Enable inputs must be on for the decoder to function,otherwise its outputs assume a single “disabled” outputcode word.

Decoder

Map

InputCode word

Enableinputs

Output code word


Decoder Example: Seven-Segment Decoders• A seven segment decoder

has 4-bit BCD input and

the seven segment display

code as its output:

• In minimizing the circuits

for the segment outputs all

non-decimal input combinations

(1010, 1011, 1100,1101, 1110,

1111) are taken as don’t-cares

/Bl D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

-- d

on’t

car

e in

pu

ts -

-


Binary n-to-2Binary n-to-2nn Decoders Decoders

• A binary decoder has n inputs and 2n outputs.

• Only the output corresponding to the input value is equalto 1.

: :

ninputs

n to 2n

decoder2n

outputs


2-to-4 Binary Decoder2-to-4 Binary Decoder

• From truth table, circuit for2x4 decoder is:

• Note: Each output is a 2-variable minterm (X'Y', X'Y,XY' or XY)

X Y F0 F1 F2 F30 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

F0 = X'Y'

F1 = X'Y

F2 = XY'

F3 = XY

X Y

Truth Table:

2-to-4Decoder

X

Y

F0

F1

F2

F3


3-to-8 Binary Decoder3-to-8 Binary Decoder

x y z F0 F1 F2 F3 F4 F5 F6 F70 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

F1 = x'y'z

x zy

F0 = x'y'z'

F2 = x'yz'

F3 = x'yz

F5 = xy'z

F4 = xy'z'

F6 = xyz'

F7 = xyz

Truth Table:

3-to-8Decoder

X

Y

F0

F1

F2

F3

F4

F5

F6

F7

Z


Implementing Functions Using Decoders

• Any n-variable logic function, in canonical sum-of-mintermsform can be implemented using a single n-to-2n decoder togenerate the minterms, and an OR gate to form the sum.

– The output lines of the decoder corresponding to the mintermsof the function are used as inputs to the or gate.

• Any combinational circuit with n inputs and m outputs can beimplemented with an n-to-2n decoder with m OR gates.

• Suitable when a circuit has many outputs, and each outputfunction is expressed with few minterms.


Implementing Functions Using Decoders

• Example: Full adder

S(x, y, z) = Σ (1,2,4,7)

C(x, y, z) = Σ (3,5,6,7)

3-to-8Decoder

S2

S1

S0

x

y

z

01234567

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1


Standard MSI Binary Decoders ExampleStandard MSI Binary Decoders Example

74138 (3-to-8 decoder)

(a) Logic circuit.(b) Package pin configuration.(c) Function table.


Encoders• If the a decoder's output code has fewer bits than the

input code, the device is usually called an encoder.

e.g. 2n-to-n, priority encoders.

• The simplest encoder is a 2n-to-n binary encoder, where ithas only one of 2n inputs = 1 and the output is the n-bitbinary number corresponding to the active input.

• For an 8-to-3 binay encoder with inputs I0-I7 the logicexpressions of the outputs Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

.

.

.

.

.

.

2n

inputsn outputs

Binaryencoder


8-to-3 Binary Encoder8-to-3 Binary EncoderAt any one time, only one input line has a value of 1.

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y2

1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

I0

I1

I2

I3

I4

I5

I6

I7Y0 = I1 + I3 + I5 + I7

y1 = I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 + I7


Three State (Tri-State) Buffers• Three state buffers are CMOS and TTL devices whose

outputs may be in one of three states: 0, 1 or Hi-Z (highimpedance, or floating state.

• Have an extra input called “output enable” or “outputdisable”.

• When enables the device transmits the input value or itscomplement to the output.Enable

InputOutput


Multiplexers• A multiplexer (MUX) is a digital switches which

connects data from one of n sources to the output.

• A number of select inputs determine which data source isconnected to the output.

Multiplexer

b bits

b bits

b bits

.

.

Dataoutput

n DataSources

s bitsSelect

Enable EN

SEL

D0

D1

Dn-1

Y

EN

.

.

.

D0

D1

Dn-1

.

.

.

1Y

2Y

bY

SEL


4-to-1 MUXTruth table for a 4-to-1 multiplexer:

mux Y

Inputs

selectS1 S0

I0I1I2I3

I0 I1 I2 I3 S1 S0 Y

d0 d1 d2 d3 0 0 d0

d0 d1 d2 d3 0 1 d1

d0 d1 d2 d3 1 0 d2

d0 d1 d2 d3 1 1 d3

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

4:1MUX

Y

Inputs

select

S1 S0

I0I1I2I3

0123

Output


4-to-1 MUX Circuit

S1 S0

0 1 2 32-to-4

Decoder

I0

I1

I2

I3

Y

S1 S0

I0

I1

I2

I3

Y


Larger Multiplexers

• Larger multiplexers can be constructed from smaller ones.

• An 8-to-1 multiplexer can be constructed from smallermultiplexers as shown:

4:1MUX

I0I1I2I3

S1 S0

4:1MUX

I4I5I6I7

S1 S0

2:1MUX

S2

Y

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7


Larger Multiplexers

• A 16-to-1 multiplexer can beconstructed from five 4-to-1multiplexers:


Standard MSI Standard MSI Multiplexer ExampleExample74151A 8-to-1 multiplexer.


Demultiplexers• Digital switches to connect data from one input source to one

of n outputs.

• Usually implemented by using n-to-2n binary decoders wherethe decoder’s enable line is used for data input of thedemultiplexer.

2X4DecoderSelect

lines

Inputdata (1bit)

Enable

One offour 1-bitoutputsOne of n

DataSourcesselected

s bits

Select

b bits

b bits

b bits

.

.

DataInput

Demux

On

e of

n o

utp

uts

1-bit 4-output demultiplexer using a 2x4 binary decoder.


1-to-4 1-to-4 DemultiplexerDemultiplexer

S1 So Y0 Y1 Y2 Y3

0 0 D 0 0 00 1 0 D 0 01 0 0 0 D 01 1 0 0 0 D

demuxData D

Outputs

select

S1 S0

Y0 = D.S1'.S0'

Y1 = D.S1'.S0

Y2 = D.S1.S0'

Y3 = D.S1.S0

2x4Decoder

D

S1

S0

Y0 = D.S1'.S0'

Y1 = D.S1'.S0

Y2 = D.S1.S0'

Y3 = D.S1.S0E


MuxMux--Demux Demux Application ExampleApplication Example

This enables sharing a single communication lineamong a number of devices.At any time, only one source and one destination canuse the communication line.


Implementing n-variable Functions Using2n-to-1 Multiplexers

• Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single 2n-to-1multiplexer:

– The n input variables are connected to the muxselect lines.

– For each mux data input line Ii ( 0 ≤≤ i ≤ ≤ 2n - 1):• Connect 1 to mux input line Ii if i is a minterm of the

function.

• Otherwise, connect 0 to mux input line Ii (because i isnot a minterm of the function thus the selected inputshould be 0).


Example: 3-variable Function Using 8-to-1 mux

• Implement the function F(X,Y,Z) = ΣΣ(1,3,5,6) usingan 8-to-1 mux.

– Connect the input variables X, Y, Z to mux select lines.

– Mux data input lines 1, 3, 5, 6 that correspond to functionminterms are connected to 1.

– The remaining mux data input lines 0, 2, 4, 7 are connected to 0.

mux

X Y Z

01234567

01010110

F

Mux Select Lines

Mux DataInput Lines


Implementing n-variable Functions Using 2n-1-to-1Multiplexers

• Any n-variable logic function can be implemented using a smaller 2n-1-to-1multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variablefunctions) as follows:– Express function in canonical sum-of-minterms form.– Choose n-1 variables as inputs to mux select lines.

– Construct the truth table for the function, but grouping inputs byselection line values (i.e select lines as most significant inputs).

– Determine multiplexer input line i values by comparing the remaininginput variable and the function F for the corresponding selection linesvalue i:

• Four possible mux input line i values:– Connect to 0 if the function is 0 for both values of remaining variable.

– Connect to 1 if the function is 1 for both values of remaining variable.

– Connect to remaining variable if function is equal to the remainingvariable.

– Connect to the inverted remaining variable if the function is equal tothe remaining variable inverted.


• Implement the function F(X,Y,Z) = ΣΣ(0,1,3,6) using a single 4-to-1mux and an inverter.

– We choose the two most significant inputs X, Y as mux select lines.

– Construct truth table:

Example: 3-variable Function Using 4-to-1 mux

X Y Z F

0 0 0 10 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 0

MuxInput i

1

Z

0

Z’

Select Lines

Value i

0

1

2

3

Select Lines

mux

X Y

0123

1

0 FZ

• We Determine multiplexer input line i values by comparing the remaining inputvariable Z and the function F for the corresponding selection lines value i:

– when XY=00 the function F=1 (for both Z=0, Z=1) thus mux input0 = 1

– when XY=01 the function F=Z thus mux input1 = Z

– when XY=10 the function F=0 (for both Z=0, Z=1) thus mux input2 = 0

– when XY=11 the function F=Z’ thus mux input3 = Z’

Mux Select Lines

Mux DataInput Lines


Example: 4-variable Function Using 8-to-1 mux• Implement the function F(x1,x2,x3,x4) = ∑∑(0,1,2,3,4,9,13,14,15) using

a single 74151A 8-to-1 mux and an inverter.

– We choose the three most significant inputs x1,x2,x3 as mux select lines.

– Construct truth table.

– Determine multiplexer Data input line Di values.


Combinational Arithmetic Circuits

• Addition:– Half Adder (HA).

– Full Adder (FA).

– Carry Ripple Adders.

– Carry Look-Ahead Adders.

• Subtraction:– Half Subtractor.

– Full Subtractor.

– Borrow Ripple Subtractors.

– Subtraction using adders.

• Multiplication:– Combinational Array Multipliers.


Half AdderHalf Adder• Adding two single-bit binary values, X, Y produces a sum S bit and a carry

out C-out bit.

• This operation is called half addition and the circuit to realize it is called ahalf adder.

X0011

Y0101

S0110

C-out 0 0 0 1

Half Adder Truth Table

Inputs Outputs

S(X,Y) = ΣΣ (1,2)S = X’Y + XY’S = X ⊕⊕ Y

C-out(x, y, C-in) = ΣΣ (3)C-out = XY

XY

Sum S

C-out HalfAdder

X

Y

SC-OUT


Full Adder• Adding two single-bit binary values, X,

Y with a carry input bit C-in producesa sum bit S and a carry out C-out bit.

X00001111

Y00110011

S01101001

C-out 0 0 0 1 0 1 1 1

C-in 0 1 0 1 0 1 0 1

Full Adder Truth Table

S(X,Y, C-in) = ΣΣ (1,2,4,7)C-out(x, y, C-in) = ΣΣ (3,5,6,7)

Inputs Outputs

Sum S

C-in

X

0

1

00 01 11 10

Y

C-in

XY

0

1

2

3

6

7

4

5

1

1 1

1

C-in

X

0

1

00 01 11 10

Y

C-in

XY

0

1

2

3

6

7

4

5

1

11 1

Carry C-out

S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)S = X ⊕ Y ⊕ (C-in)

C-out = XY + X(C-in) + Y(C-in)


Full Adder Circuit Using AND-OR

XY

YC-in

C-outXC-in

X

X

Y

C-in

Y

C-in

Y Y’Y

X X’X

C-in C-in’C-in

X’Y’C-in

XY’C-in’

Sum SX’YC-in’

XYC-in

X’

X’

X

X

Y’

Y

Y

C-in

Y

C-in’

C-in’

C-in’

Full Adder

X Y

S

C-inC-out


Full Adder Circuit Using XOR

Full Adder

X Y

S

C-inC-out XY

YC-in

C-outXC-in

X

X

Y

C-in

Y

C-in

Sum S

X

Y

C-in


n-bit Carry Ripple Addersn-bit Carry Ripple Adders• An n-bit adder used to add two n-bit binary numbers can built by

connecting in series n full adders.

– Each full adder represents a bit position j (from 0 to n-1).

– Each carry out C-out from a full adder at position j is connected to thecarry in C-in of the full adder at the higher position j+1.

• The output of a full adder at position j is given by:

Sj = Xj ⊕⊕ Yj ⊕⊕ Cj

Cj+1 = Xj . Yj + Xj . Cj + Y . Cj

• In the expression of the sum Cj must be generated by the full adder at thelower position j-1.

• The propagation delay in each full adder to produce the carry is equal totwo gate delays = 2 ∆∆

• Since the generation of the sum requires the propagation of the carry fromthe lowest position to the highest position , the total propagation delay ofthe adder is approximately:

Total Propagation delay = 2 n∆∆


Full Adder

X1 Y1

S1

C-inC-out Full Adder

X0 Y0

S0

C-inC-out C0 =0 Full Adder

X2 Y2

S2

C-inC-out Full Adder

X3 Y3

S3

C-inC-outC1C2C3C4

Data inputs to be added

Sum output

4-bit Carry Ripple Adder4-bit Carry Ripple AdderAdds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3

4-bit Adder

X3X2X1X0

S3 S2 S1 S0

C-inC-outC4

Y3Y2Y1Y0

C0 =0

Inputs to be added

Sum Output

Total Propagation delay = 2 n∆ ∆ = = 8∆∆

or 8 gate delays


Larger Adders• Example: 16-bit adder using 4, 4-bit adders

• Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15)producing a 16-bit Sum S (bits S0 to S15) and a carry out C16from most significant position.

4-bit Adder

C-inC-out 4-bit Adder

C-inC-out C0 =0 4-bit Adder

C-inC-out 4-bit Adder

C-inC-outC4C8C12C16

Data inputs to be added X (X0 to X15) , Y (Y0-Y15)

Sum output S (S0 to S15)

Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0

S3 S2 S1 S0S3 S2 S1 S0S3 S2 S1 S0S3 S2 S1 S0

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n∆∆ = 4 = 4 x 8∆∆ = 32 ∆∆ or 32 gate delays


Carry Look-Ahead AddersCarry Look-Ahead Adders• The disadvantage of the ripple carry adder is that the propagation delay of adder (2 n∆∆ )

increases as the size of the adder, n is increased due to the carry ripple through all thefull adders.

• Carry look-ahead adders use a different method to create the needed carry bits for eachfull adder with a lower constant delay equal to three gate delays.

• The carry out C-out from the full adder at position i or Cj+1 is given by:

C-out = C i+1 = Xi . Yi + (Xi + Yi) . Ci

• By defining:

– Gi = Xi . Yi as the carry generate function for position i (one gate delay)(If Gi =1 C i+1 will be generated regardless of the value Ci)

– Pi = Xi + Yi as the carry propagate function for position i (one gate delay)(If Pi = 1 Ci will be propagated to C i+1)

• By using the carry generate function Gi and carry propagate function Pi , then C i+1 canbe written as:

C-out = C i+1 = Gi + Pi . Ci

• To eliminate carry ripple the term Ci is recursively expanded and bymultiplying out, we obtain a 2-level AND-OR expression for each C i+1


• For a 4-bit carry look-ahead adder the expanded expressionsfor all carry bits are given by:

C1 = G0 + P0.C0

C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0

C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0

C4 = G3 + P3.G2 + P3.P2.G1 + P3 . P2.P1.G0 + P3.P2.P1.P0.C0

where Gi = Xi . Yi Pi = Xi + Yi

• The additional circuits needed to realize the expressions areusually referred to as the carry look-ahead logic.

• Using carry-ahead logic all carry bits are available after threegate delays regardless of the size of the adder.

Carry Look-Ahead AddersCarry Look-Ahead Adders


Carry Look-Ahead CircuitCarry Look-Ahead Circuit

Ci = Gi-1 + Pi-1. Gi-2 + …. + Pi-1.P i-2. …P1 . G0 + P i-1.P i-2. …P0 . C0


Binary Arithmetic OperationsBinary Arithmetic OperationsSubtractionSubtraction

• Two binary numbers are subtracted by subtracting each

pair of bits together with borrowing, where needed.

• Subtraction Example:

0 0 1 1 1 1 1 0 0 Borrow

X 229 1 1 1 0 0 1 0 1

Y - 46 - 0 0 1 0 1 1 1 0

183 1 0 1 1 0 1 1 1


Half Half SubtractorSubtractor• Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces

a difference bit D and a borrow out bit B-out.

• This operation is called half subtraction and the circuit to realize it is calleda half subtractor.

X0011

Y0101

D0110

B-out 0 1 0 0

Half Subtractor Truth Table

Inputs Outputs

D(X,Y) = ΣΣ (1,2)D = X’Y + XY’D = X ⊕⊕ Y

B-out(x, y, C-in) = ΣΣ (1)B-out = X’Y

HalfSubtractor

X

Y

DB-OUT

XY

DifferenceD

B-out


Full Subtractor• Subtracting two single-bit binary values, Y,

B-in from a single-bit value X produces adifference bit D and a borrow out B-out bit.This is called full subtraction.

X00001111

Y00110011

D01101001

B-out 0 1 1 1 0 0 0 1

B-in 0 1 0 1 0 1 0 1

Full Subtractor Truth Table

S(X,Y, C-in) = ΣΣ (1,2,4,7)C-out(x, y, C-in) = ΣΣ (1,2,3,7)

Inputs Outputs

Difference D

B-in

X

0

1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

1 1

1

B-in

X

0

1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

11 1

Borrow B-out

S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)S = X ⊕ Y ⊕ (C-in)

B-out = X’Y + X’(B-in) + Y(B-in)


Full Subtractor Circuit Using AND-OR

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Y Y’Y

X X’X

B-in B-in’B-in

X’Y’B-in

XY’B-in’

Difference DX’YB-in’

XYB-in

X’

X’

X

X

Y’

Y

Y

B-in

Y

B-in’

B-in’

B-in’

Full Subtractor

X Y

D

B-inB-out


Full Subtractor Circuit Using XOR

Difference D

X

Y

B-in

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Full Subtractor

X Y

D

B-inB-out


An n-bit subtracor used to subtract an n-bit number Y from another

n-bit number X (i.e X-Y) can be built in one of two ways:

• By using n full subtractors and connecting them in series,creating a borrow ripple subtractor:– Each borrow out B-out from a full subtractor at position j is connected to

the borrow in B-in of the full subtracor at the higher position j+1.

• By using an n-bit adder and n inverters:

– Find two’s complement of Y by:

• Inverting all the bits of Y using the n inverters.

• Adding 1 by setting the carry in of the least significantposition to 1

– The original subtraction (X - Y) now becomes an addition ofX to two’s complement of Y using the n-bit adder.

n-bit n-bit SubtractorsSubtractors


4-bit Borrow Ripple 4-bit Borrow Ripple SubtractorSubtractor

Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

4-bitSubtractor

X3X2X1X0

D3 D2 D1 D0

B-inB-outB4

Y3Y2Y1Y0

B0 =0

Inputs

Difference Output D

Full Subtractor

X1 Y1

D1

B-inB-out

X0 Y0

D0

B-inB-out B0 =0

X2 Y2

D2

B-inB-out

X3 Y3

D3

B-inB-outB1B2B3B4

Data inputs to be subtracted

Difference output D

Full Subtractor

Full Subtractor

Full Subtractor


4-bit 4-bit Subtractor Subtractor Using 4-bit AdderUsing 4-bit Adder

4-bit Adder

X3 X2 X1 X0

D3 D2 D1 D0

C-inC-outC4

Y3 Y2 Y1 Y0

C0 = 1

Inputs to be subtracted

Difference Output

S3 S2 S1 S0


Binary MultiplicationBinary Multiplication• Multiplication is achieved by adding a list of shifted multiplicands according to the

digits of the multiplier.

• Ex. (unsigned)

11 1 0 1 1 multiplicand (4 bits)

X 13 X 1 1 0 1 multiplier (4 bits)

-------- -------------------

33 1 0 1 1

11 0 0 0 0

______ 1 0 1 1

143 1 0 1 1

---------------------

1 0 0 0 1 1 1 1 Product (8 bits)

• An n-bit X n-bit multiplier can be realized in combinationalcircuitry by using an array of n-1 n-bit adders where is adder isshifted by one position.

• For each adder one input is the multiplied by 0 or 1 (using ANDgates) depending on the multiplier bit, the other input is n partialproduct bits.

X3 X2 X1 X0 x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3_______________________________________________________________________________________________________________________________________________

P7 P6 P5 P4 P3 P2 P1 P0


4x4 Array Multiplier4x4 Array Multiplier


Combinational Comparators• Comparing two binary inputs A, B each n bits for equality (i.e A = B)

is a common operation in computers.

• A single output combinational circuit to accomplish this can beconstructed using n 2-input XNOR gates for bit-wise comparison plusone n-input AND gate. The output = 1 if A = B

• This can also be done by subtraction (A - B) and checking for a zeroresult using a single n-input NOR gate.

• Example: 1-bit comparator: A, B 1-bit each.

– The 1-bit comparison requires a single XNOR gate

Truth table:

A B (A ⊕ B)’0 0 10 1 01 0 01 1 1

Output

(A ⊕⊕ B)’AB

1-bit comparator

Output


Example: 4-bit Comparator

Comparator

Output

A3

B3

Compares A = A3 A2 A1 A0 with B = B3 B2 B1 B0 Output = 1 if A = B

A2

B2

A1

B1

A0

B0


Combinational Shift Circuits• An n-bit shift circuit (shifter) has a single n-bit data input A, and a

single n-bit output R and a number of control inputs to determinethe shift amount (0 to n-1).

• Possible shift operations include:

– Shift left or right:

• Arithmetic right shift (the sign bit is shifted in),

• logic shift (0 is shifted in)

• Rotate left or right.

• Example: Original data input A = 11011

• Shift left by one : 10110

• Logic shift right by one: 01101

• Arithmetic shift right by one: 11101

• Rotate left by one: 10111

• Combinational shift circuits are usually constructed using a numberof levels of multiplexeres.


Example: Combinational 8-Bit Right Shifter

1 0 Mux select S

A B

D

Basic Building Block 2-to-1 Mux

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S2 S1 S0A0A1A2A3A4A5A6A7

R0R1R2R3R4R5R6R7

• Propagation delay: 2 gate delays per level x 3 levels = 6 gate delays

• How many Mux levels for 32-bit shifter? Propagation delay?

S2 S1 S0shift amount from 0 to 7

Connect to:

0 for logicright shiftor to A7for arithmetic right shift

or to A0 - A6for rotate right{

Three levels of Muxes used


Sequential Logic Circuits• Unlike combinational logic circuits, the output of sequential

logic circuits not only depends on current inputs but also on thepast sequence of inputs.

• Sequential circuits are constructed using combinational logicand a number of memory elements with some or all of thememory outputs fed back into the combinational logic forminga feedback path or loop.

• A very simple sequential circuit with no inputs created usinginverters to form a feedback loop:

Q

QN

When this circuit is powered up it randomly outputs Q = 0 or Q =1


Sequential Logic Circuits

Combinationallogic

Memoryelements

Combinationaloutputs Memory outputs

Inputs

Sequential circuit = Combinational logic + Memory Elements

Current State of A sequential Circuit: Value stored in memoryelements (value of state variables).

State transition: A change in the stored values in memory elementsthus changing the sequential circuit from one state to another state.


Sequential Circuit Buliding Blocks:

Generic Memory Elements• A Memory Element: A logic device that can remember a single-bit

value indefinitely, or change its value on command from its inputs.

• The output Q of the memory element represents the value stored in thememory element. This is also called the state variable of the memoryelements. A memory element can be in one of two possible states:

– Q = 0 (the memory element has 0 stored), also said be in state 0.

– Q =1 (the memory element has 1 stored), also said to be in state 1.

• The commands to the memory element formed by its input(s) may include:

– Set: Store 1 (Q=1) in the memory element.

– Reset: Store 0 (Q=0) in the memory element.

– Flip: Change stored value from 0 to 1 or from 1 to 0.

– Hold value: Memory value does not change.

• Memory Element state transition: A change in the stored value from 0 to 1, or from1 to 0 such as that caused by a flip command.

commandMemoryelement

Memory Element Output:

stored single-bit value

Q


The State of A sequential CircuitThe State of A sequential Circuit• A state variable in a sequential circuit represents the

single-bit variable Q stored in a memory element incircuit.– Each memory element may be in state 0 or state 1 depending on

the current value stored in the memory element.

• The State of A sequential Circuit:– The collection of all state variables (memory element stored

values) that at any time contain all the information about thepast necessary to account for the circuit’s future behavior.

– A sequential circuit that contains n memory elements could bein one of a maximum of 2n states at any given time dependingon the stored values in the memory elements.

– Sequential Circuit State transition: A change in the storedvalues in memory elements thus changing the sequential circuitfrom one state to another.


Clock Signals & Synchronous Sequential CircuitsClock Signals & Synchronous Sequential Circuits• A clock signal is a periodic square wave that indefinitely switches

values from 0 to 1 and 1 to 0 at fixed intervals.

• Clock cycle time or clock period: The time interval between twoconsecutive rising or falling edges of the clock.

• Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz)

– Example: Clock cycle time = 1ms clock frequency = 1000Hz

• Synchronous Sequential Circuits: Sequential circuits that have a clocksignal as one of its inputs:

–– All state transitions in such circuits occur only when the clock value isAll state transitions in such circuits occur only when the clock value iseither 0 or 1 or happen at the rising or falling edges of the clock dependingeither 0 or 1 or happen at the rising or falling edges of the clock dependingon the type of memory elements used in the circuit.on the type of memory elements used in the circuit.

Rising edges ofthe clock

Falling edges

of the clock

Clock signal

Clock CycleTime

1

0


Sequential Circuit Memory Elements: Latches, Flip-Flops

• Latches and flip-flops are the basic single-bit memoryelements used to build sequential circuit with one or twoinputs/outputs, designed using individual logic gates andfeedback loops.

• Latches:

– The output of a latch depends on its current inputsand on its previous inputs and its change of statecan happen at any time when its inputs change.

• Flip-Flop:

– The output of a flip-flop also depends on currentand previous input but the change in output(change of state or state transition) occurs atspecific times determined by a clock input.


• Latches:

– S-R Latch

– S-R Latch With Enable

– D-Latch

• Flip-Flops:

– Edge-Triggered D Flip-Flop

– Master/Slave S-R Flip-Flop

– Master/Slave J-K Flip-Flop

– Edge-Triggered J-K Flip-Flop

– T Flip-Flop With Enable

Sequential Circuit Memory Elements: Latches, Flip-Flops


S-R Latch• An S-R (set-reset) latch can be built using two NOR-

gates forming a feedback loop.

• The output of the S-R latch depends on current as well asprevious inputs or state, and its state (value stored) canchange as soon as its inputs change.

R

S

Q

QN

S R Q QN 0 0 last Q Last QN 0 1 0 1 1 0 1 0 1 1 0 0

Function Table

Circuit


S-R Latch With Enable• Since the S-R latch is responsive to its inputs at all times an enable line

C is used to disable or enable state transitions.

• Behaves similar to a regular S-R latch when enable C=1

Q

QN

S

Enable C

R

S R C Q QN 0 0 1 last Q last QN 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 x x 0 last Q last QN

Q

Q

SCR

Function Table

Circuit

Logic Symbol


D-Latch• Similar to S-R latch with an enable line, but both S, R

are generated from one input D (data) and an inverter.

• Stores the value of its input D when enable C =1.

C D Q QN 1 0 0 1 1 1 1 0 0 x Last Q Last QN

Q

QN

D

CQ

Q

D

C

Function Table

Circuit

Logic Symbol


Edge-Triggered D Flip-Flop• Uses a pair of D latches and inverters.

• Similar in behavior to a D latch except that output and state changeshappen at the rising or falling edge of an input clock.

• A D Flip-Flop triggered on the rising edge of the clock is given by:

Q

Q

D

CLK

D CLK Q QN 0 0 1 1 1 0 x 0 Last Q Last QN x x Last Q Last QN

Clock

Q

Q

D

C

Q

Q

D

C

CLK

DQM

Master Latch Slave Latch

Q

QN

Circuit

Logic Symbol

Function Table


Master/Slave S-R Flip-Flop

• S-R latches are substituted for the D latches in thenegative-edge triggered D flip flop

Q

Q

SC

Q

Q

SC

CLK

SQM

Master Latch Slave Latch

Q

QNR R R

Q

Q

SCR

S R C Q QN x x 0 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 undef. undef.

Circuit

Logic Symbol

Function Table


Master/Slave J-K Flip-Flop• Solves the problem in the problem when both S=R=1

• When J=K=1 the last state is inverted.

J K C Q QN x x 0 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q

Q

Q

SCR

Logic Symbol

Function Table

CLK

Q

Q

SC

Q

Q

SCJ

QMMaster Latch Slave Latch

Q

QNK R R

Circuit


Edge Triggered J-K Flip-Flop

• Created from an edge-triggered D flip-flop

Q

Q

j

CLKk

J K C Q QN x x 0 last Q last QN x x 1 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q

Function Table Logic Symbol

Q

Q

D

CLK

Q

QN

J

K

CLK

Circuit


T Flip-Flop With Enable

• Changes state on every clock cycle (rising edge of T).

Q

QCLK

D Q

QN

En

T

Q

Q

j

CLKk

EN Q

QNT

OR

T En Q QN x 0 last Q last QN 1 last QN last Q

Circuit

Function Table


Clocked Synchronous State-Machines• Such machines have the characteristics:

– Sequential circuits designed using flip-flops.

– All flip-flops use a common clock (clocked synchronous).

– A machine using n flip-flops (state memory) has n state variables(the outputs of the flip-flops) and 2n states.

– In general, the next state and output of the machine both dependon the current state of the machine and on the current input:

Next state = F(current state, input)

output = G(current state, input)

This type of state machine is called Mealy Machine

– In some cases the next output depends only on the current stateand not directly on the current input

–

Next state = F(current state, input) output = G(current state)

Such machines are called Moore machines.


Clocked Synchronous State-Machine ModelClocked Synchronous State-Machine Model

Next-stateLogic

F

StateMemory

clock

OutputLogic

G

excitation current state outputs

(Mealy machine)

Moore Machine

State memory:Usually edge-triggeredD or JK flip-flops

inputs

clock


Latch/Flip-Flop Characteristic Equations

• The next output of a flip flop (or next state) can beobtained from the function table of each type of flip-flop.

• This latch/flip-flop next output behavior is expressed in as

a characteristic function which gives the next state interms of the current state and output:

Q* = f (Q , inputs)

(Q* is the next state of Q).

• Vary important in state machine analysis and design.


D latch or flip-flop

present nextinput state state

D Q(t) Q* ________________________________________

0 0 0 0 1 0 1 0 1 1 1 1________________________________________

Characteristic Equation:

Q* = D

S-R latch

S R Q(t) Q* ____________________________________________________

0 0 0 0 0 0 1 1 0 1 X 0 1 0 X 1 1 1 X X __________________________________________________


Q* = S + R’. Q

Characteristic EquationsCharacteristic Equations


Characteristic EquationsCharacteristic Equations

J-K flip-flop

J K Q Q*_______________________________________________________

0 0 0 0 0 0 1 1 = hold 0 1 0 0 0 1 1 0 = reset 1 0 0 1 1 0 1 1 = set 1 1 0 1 1 1 1 0 = flip ______________________________________________________


Q* = J . Q’ + K’. Q

T flip-flop with enable

T Q Q* ________________________________________

0 0 0 0 1 1 1 0 1 1 1 0 ________________________________________


Q* = T. Q’ + T’ .Q


Device Characteristic Equations

S-R latch Q* = S+R’.Q D latch Q* = D Edge-triggered D flip-flop Q* = D Master/Slave S-R flip-flop Q* = S+R’.Q Master/Slave J-K flip flop Q* = J.Q’ + K’.Q Edge Triggered J-K flip-flop Q* = J.Q’ + K’.Q T flip-flop Q* = Q’ T flip-flop with enable Q* = EN.Q’ + EN’.Q

Latch/Flip-Flop Characteristic EquationsLatch/Flip-Flop Characteristic Equations


Clocked Synchronous State-machine AnalysisClocked Synchronous State-machine AnalysisGiven the circuit diagram of a state machine:

1 Analyze the combinational logic to determine flip-flop input (excitation)equations: Di = Fi (Q, inputs)– The input to each flip-flop is based upon current state and circuit

inputs.

2 Substitute excitation equations into flip-flop characteristic equations, giving

transition equations: Qi* = Hi( Di )

3 From the circuit, find output equations: Z = G (Q, inputs)– The outputs are based upon the current state and possibly the inputs.

4 Construct a state transition/output table from the transition and output

equations:– Similar to truth table.– Present state on the left side.– Outputs and next state for each input value on the right side.

– Provide meaningful names for the states in state table, if possible.

5 Draw the state diagram which is the graphical representation of state table.


B

1

0, 1

A0 1

B

1 / 1

0 / 1, 1 / 0

A

0

Moore

Mealy

State Diagram

0/0

Format:Arc = input XNode = state/output Q

Format:Arc = input X / mealy output YNode = state

State

Output

Input

Basic Format:


State Machine Analysis ExampleState Machine Analysis Example

Q1

Q1'

Q0

Q0'

y

x

CP

D Q

Q'

D Q

Q'

Analyze the state machine:1 Input (or excitation) equations:

D0 = Q1’. X

D1 = Q1 . x + Q0 . x

2 Characteristic equations:

Q0* = D0

Q1* = D1

Find State equations:

Q0* = Q1’. x

Q1* = Q1 . x + Q0 . x

3 Output equation:

y = (Q0 + Q1) . x'

This is a Mealy Machine since output = G(current state, input)


4 From the state equations and output equation, construct the statetransition/output table:


State equations:

Q0* = Q1’. x

Q1* = Q1 . x + Q0 . x

Output equation:

y = (Q0 + Q1) . x'

x

Q1 Q0 0 1

0 0 00,0 01,0

0 1 00,1 11,0

1 0 00,1 10,0

1 1 00,1 10,0

Q1* Q0* , yCurrent State

Next State when x =0

Output for current state when x =0



Input


5 Draw the state diagram of the state machine.


x

Q1 Q0 0 1

0 0 00,0 01,0

0 1 00,1 11,0

1 0 00,1 10,0

1 1 00,1 10,0

Q1* Q0* , y

00

01 11

101/0

1/0

1/0

0/1

0/10/0

1/0 0/1

Arc = input x / output yNode = state

state transition/output table state diagram


Clocked Synchronous State-machine AnalysisClocked Synchronous State-machine AnalysisGiven the circuit diagram of a state machine:

1 Analyze the combinational logic to determine flip-flop input (excitation)equations: Di = Fi (Q, inputs)– The input to each flip-flop is based upon current state and circuit

inputs.

2 Substitute excitation equations into flip-flop characteristic equations, giving

transition equations: Qi* = Hi( Di )

3 From the circuit, find output equations: Z = G (Q, inputs)– The outputs are based upon the current state and possibly the inputs.

4 Construct a state transition/output table from the transition and output

equations:– Similar to truth table.– Present state on the left side.– Outputs and next state for each input value on the right side.

– Provide meaningful names for the states in state table, if possible.

5 Draw the state diagram which is the graphical representation of state table.



Q1

Q1'

Q0

Q0'

y

x

CP

D Q

Q'

D Q

Q'

Analyze the state machine:1 Input (or excitation) equations:

D0 = Q1’. X

D1 = Q1 . x + Q0 . x

2 Characteristic equations:

Q0* = D0

Q1* = D1

Find State equations:

Q0* = Q1’. x

Q1* = Q1 . x + Q0 . x

3 Output equation:

y = (Q0 + Q1) . x'

This is a Mealy Machine since output = G(current state, input)




State equations:

Q0* = Q1’. x

Q1* = Q1 . x + Q0 . x

Output equation:

y = (Q0 + Q1) . x'

x

Q1 Q0 0 1

0 0 00,0 01,0

0 1 00,1 11,0

1 0 00,1 10,0

1 1 00,1 10,0

Q1* Q0* , yCurrent State





Input


5 Draw the state diagram of the state machine.


x

Q1 Q0 0 1

0 0 00,0 01,0

0 1 00,1 11,0

1 0 00,1 10,0

1 1 00,1 10,0

Q1* Q0* , y

00

01 11

101/0

1/0

1/0

0/1

0/10/0

1/0 0/1


state transition/output table state diagram


• State Naming:

– Optionally name the states and substitute statenames S for state-variable combinations intransition/output table and in state diagram.

– Example: For a circuit with two flip-flops:

Q1 Q0 State Name

0 0 A

0 1 B

1 0 C

1 1 D

Clocked State-machine Analysis:Clocked State-machine Analysis:State NamingState Naming


Clocked State-machine Analysis Example:Clocked State-machine Analysis Example:Transition/Output Table Using State NamesTransition/Output Table Using State Names

x

Q1 Q0 0 1

0 0 00,0 01,0

0 1 00,1 11,0

1 0 00,1 10,0

1 1 00,1 10,0

Q1* Q0* , y

For the last examplenaming The States:

Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D

Transition/output Table: Transition/output Table using state names:

x

S 0 1

A A,0 B,0

B A,1 D,0

C A,1 C,0

D A,1 C,0

S* , y

A

B

C

D


Clocked State-machine Analysis Example:Clocked State-machine Analysis Example:State Diagram Using State NamingState Diagram Using State Naming

Naming The States:Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D

00

01 11

101/0

1/0

1/0

0/1

0/10/0

1/0 0/1


State Diagram without state naming: State Diagram with state naming:

A

B D

C1/0

1/0

1/0

0/1

0/10/0

1/0 0/1


• The timing diagram for a state machine graphically shows the state machine response interms of state variables and output signals vs. time for given time-varying input signalsand a given initial state.

• State machine timing diagrams can be generated using transition/output tables or statediagrams.

• Timing diagrams can be used to account for both combinational and flip-floppropagation delays.

• Example: For the state machine in the previous example show the timing diagram forthe following input, assuming an initial state A and ignoring propagation delays:

Clocked State-machine Analysis:State Machine Timing Diagram

Clock1

0

Input X

Cycle: 0 1 2 3 4 5 6 7

1

0

Time


State Machine Timing Diagram ExampleState Machine Timing Diagram Example

Clock1

0

Input X

Cycle: 0 1 2 3 4 5 6 7

Q1

Q0

Output Y

1

0

A B D C A A B A

1

0

1

0

Time


State Machine Analysis Example 2State Machine Analysis Example 2Analyze the state machine:

D Q

CLK Q

D Q

CLK Q

D Q

CLK Q

X

YQ2’

Q0

Q1

CLK

D0

D1

D2

Q0

Q1

Q2

Z1

Z2

State MemoryInput Logic F

Output Logic G

Q2’


State Machine Analysis Example 2State Machine Analysis Example 2

Excitation Equations

D0 = X . Y’.Q2

D1 = X . Q0

D2 = Y’ + Q1

State or Transition Equations

Q0* = D0 = X . Y’ . Q2’

Q1* = D1 = X . Q0

Q2* = D2 = Y’ + Q1

Characteristic Equations

Q0* = D0

Q1* = D1

Q2* = D2

Output Equations

Z1 = X . Q0 + Q1’

Z2= (Q1 . Q2)’

1

2

3




state XYname Q2 Q1 Q0 00 01 11 10A 0 0 0 100, 11 000, 11 000, 11 101, 11B 0 0 1 100, 11 000, 11 010, 11 111, 11C 0 1 0 100, 01 100, 01 100, 01 101, 01D 0 1 1 100, 01 100, 01 110, 11 111, 11E 1 0 0 100, 11 000, 11 000, 11 100, 11F 1 0 1 100, 11 000, 11 010, 11 110, 11G 1 1 0 100, 00 100, 00 100, 00 100, 00H 1 1 1 100, 00 100, 00 110, 10 110,10

Q2* Q1* Q0*, Z1 Z2 (Next State, Outputs)

Transition Equations

Q0* = D0 = X . Y’ . Q2’

Q1* = D1 = X . Q0

Q2* = D2 = Y’ + Q1

Output Equations

Z1 = X . Q0 + Q1’

Z2= (Q1 . Q2)’


State-machine Analysis Example 2:State-machine Analysis Example 2:Transition/Output Table Using State NamesTransition/Output Table Using State Names

XY S 00 01 11 10 A E, 11 A, 11 A, 11 F, 11 B E, 11 A, 11 C, 11 H, 11 C E, 01 E, 01 E, 01 F, 01 D E, 01 E, 01 G, 11 H, 11 E E, 11 A, 11 A, 11 E, 11 F E, 11 A, 11 C, 11 G, 11 G E, 00 E, 00 E, 00 E, 00 H E, 00 E, 00 G, 10 G,10

S*, Z1 Z2


State-machine Analysis Example 2:State-machine Analysis Example 2:State Diagram (incomplete)State Diagram (incomplete)

A

E

C

DH

B

F

G

Y (11) (11) X’ Y X Y (11)

X’ Y’(11)

X Y’(11)

X’Y’(11) XY’

(11)

XY’(01)

X’+Y(01)

XY’(11)

X’(01)

XY(11)

Arc: input expression (outputs) = expression (Z1 /Z2)


State Machine Analysis Example 3State Machine Analysis Example 3Analyze the state machine:

J

K

CLK

X

Y

ZQ1

Q2

J1

K1

J2

K2

J

K

Q

Q

Q

Q



Excitation Equations

J1 = X

K1 = X·Y

J2 = X’

K2 = 0


Q1* = X·Q1’ + (X·Y)’ ·Q1 = X·Q1’ + X’·Q1 + Y’·Q1

Q2* = X’·Q2’ + 0’·Q2 = X’·Q2’ + Q2

Characteristic Equations

Q*= J·Q’ + K’·Q

Q1*= J1·Q1’ + K1’·Q1

Q2* = J2·Q2’ + K2’·Q2

Output Equation

Z = X·Q1 + Q2

1

2

3




XY

S Q1 Q2 00 01 11 10

A 0 0 01,0 01,0 10,0 10,0

B 0 1 01,1 01,1 11,1 11,1

C 1 0 11,0 11,0 00,1 10,1

D 1 1 11,1 11,1 01,1 11,1

Q1* Q2*, Z


Q1* = X·Q1’ + X’·Q1 + Y’·Q1

Q2* = X’·Q2’ + Q2

Output Equation

Z = X·Q1 + Q2


State-machine Analysis Example 3:State-machine Analysis Example 3:Transition/Output Table Using State NamesTransition/Output Table Using State Names

XY

S 00 01 11 10

A B,0 B,0 C,0 C,0

B B,1 B,1 D,1 D,1

C D,0 D,0 A,1 C,1

D D,1 D,1 B,1 D,1

S*, Z


State-machine Analysis Example 3:State-machine Analysis Example 3:State DiagramState Diagram

A B

CD00,01,10

1

10

1

00,01

1

00,01

0

11

110,11

0

00,01

0

11

1

10,11

1

Arc Format: inputs xy output z


State Machine Design ProcedureState Machine Design Procedure1. Build state/output table (or state diagram) from word

description using state names.

2. Minimize number of states (optional).

3. State Assignment: Choose state variables and assign bitcombinations to named states.

4. Build transition/output table from state/output table (or statediagram) by substituting state variable combinations insteadof state names.

5. Choose flip-flop type (D, J-K, etc.)

6. Build excitation table for flip-flop inputs from transition table.

7. Derive excitation equations from excitation table.

8. Derive output equations from transition/output table.

9. Draw logic diagram with excitation logic, output logic, andstate memory elements.


State Machine Design Example 1:State Machine Design Example 1:110 Detector110 Detector

• Word description (110 input sequence detector):– Design a state machine with input A and output Y.

– Y should be 1 whenever the sequence 1 1 0 has been detected onA on the last 3 consecutive rising clock edges (or ticks).

– Otherwise, Y = 0

– Note: this is a Moore machine, that is the output, Y, depends onlyon inputs at previous clocks rising edges , not on the currentinput.

• Timing diagram interpretation of word description (onlyrising clock edges are shown):

A

CLK

Y

0 1 1 0 0 1 1 1 0 1 1 1


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep1: Choosing StatesChoosing States

• Possible states (What does the state machine need toremember?):

– Initial : power up, no clocks yet Y = 0

– No1s : first 1 not found Y = 0

– First1 : first 1 found Y = 0

– Two1s : at least 2 consecutive 1s found Y = 0

– ALL : found 1 1 0 Y = 1

• Are all the states needed?– Notice: Initial is equivalent to NO1s

– We can drop the state Initial and replace it with state No1s


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep 1: State/Output Table and Diagram

S

No1s

First1

Two1s

ALL

A0

No1s

No1s

ALL

No1s

1

First1

Two1s

Two1s

First1

Y

0

0

0

1

State Table

S*

NO1s

0

First1

0

Two1s

0

ALL

11

1

1

0

0

0

State DiagramReset

Format:Arc: input ANode: state/output Y

1

0


Step3: State Assignment ConsiderationsStep3: State Assignment Considerations• Why does the choice of state assignment matter?

– Has a big effect on the complexity of excitation and output equationsand thus on the amount of combinational logic needed.

• How to find the best state assignment?

– The only known way is to try all assignments and determine theresulting equations.

• N = 2: (22)! = 4! = 24 assignments for 2 state bits

• N = 3: (23)! = 8! = 40,320 assignments for three state bits.

• N = 4: (24)! = 16! = 20,922,789,888,000assignments for 4 state bits!!!

THIS IS NOT PRACTICAL APPROACH!

∴ Use heuristic guidelines for pretty good assignments.

This is still an active area of research!

• There is no effective way to guarantee a “best” assignment. Theheuristic methods sometimes perform poorly!


State Assignment StrategiesState Assignment Strategies• Simplest Assignment:

– Straight binary, not best; purely arbitrary assignment.

• One Hot Assignment:

– Redundant encoding, each flip-flop is assigned a state.

– Uses the same number of bits as there are states (not useful in largedesigns).

– Simple to assign; simple next state logic (no state decoding required)

– Output logic is simple! One OR gate per Moore output!

• Almost One Hot Assignment:

– Almost same as One Hot, but one less state bit.

– Use all 0’s to represent a state (usually INIT).

– Must now decode state 0 if it is needed.

• Decomposed Assignment:

– Use the “structure” of the state table to simplify next-state and outputlogic.

– An “art” which requires much practice.


Example: State Assignment StrategiesExample: State Assignment Strategies Alternative Assignments AB

Q1..Q4 Q1..Q5 Q1Q2Q3 Q1Q2Q3 S 00 01 11 10 Z

0000 00001 000 000 INIT A0 A0 A1 A1 0

0001 00010 100 001 A0 OK0 OK0 A1 A1 0

0010 00100 101 010 A1 A0 A0 OK1 OK1 0

0100 01000 110 011 OK0 OK0 OK0 OK1 A1 1

1000 10000 111 100 OK1 A0 OK0 OK1 OK1 1

Almost One Decomposed Simplest One Hot Hot

– Example decomposition:• Initial State = all 0’s for easy RESET• INIT state is different, so use Q1 = 1 for non-INIT states; thus D1=1• Z = 1 in only 2 states, so use Q2 =1 for states when Z = 1; thus Z = Q2

• Use Q3 = 1 for state transitions caused by A having the value of 1 (alldestination states cause by A = 1, i.e. states A1 and OK1); thus D3=A

THUS, simpler next state and output logic!


State Assignment Heuristic GuidelinesState Assignment Heuristic GuidelinesStarting from the highest priority to the lowest:

• Choose initial coded state that’s easy to produce at reset: (all 0’sor 1’s)

– This simplifies the initialization circuitry.

• Freely use any of the 2n state codes for best assignment

(i.e.. with s states, don’t just use the first s integers 0,1,…,s-1)

• Define specific bits or fields that have meaning with respect toinput or output variables (decomposed codes).

• Consider using more than minimum number of state variables toallow for decomposed codes.

• Minimize number of state variables that change at each transition

• Simplify output logic.


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep 3: State Assignment

• Choose state variable assignments:– Initial state all 0s

– Q2 = last A, so Q2* = A

– minimize number of transitions

S

No1s

First1

Two1s

ALL

A0

No1s

No1s

ALL

No1s

1

First1

Two1s

Two1s

First1

Y

0

0

0

1

S*

Q1 Q2

0 0

0 1

1 1

1 0


• Step 4: Build transition/output table from state/output table bysubstituting state variable combinations instead of state names.

• Step 5: Choose D Flip-Flops , so Q*= D

• Step 6: Excitation table:– Same as Transition/output table with Q1*=D1, Q2*=D2

State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep 4: Transition/Output Table

A0

00

00

10

00

1

01

11

11

01

Y

0

0

0

1

Q1* Q2*=D1 D2 Step 6

Q1 Q2

0 0

0 1

1 1

1 0


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorSteps 7, 8 : Excitation/Output Equations

• Step 7: Excitation equations: D1, D2 = F (A, Q1, Q2)

• Step 8: Output equation: Y = G (Q1, Q2)

Y = Q1•Q2’ (directly read from transition table)

0 0 1 0

0 1 1 0

Q1 Q2

A 00 01 11 10

0

1

D1 :0 0 0 0

1 1 1 1

Q1 Q2

A 00 01 11 10

0

1

D2 :

D1 = Q1•Q2 + Q2•A

Q1•Q2

Q2•AD2 = A (as planned!)


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep 9: Logic DiagramStep 9: Logic Diagram

D

>

Q

Q

D

>

Q

Q

A

CLK

RESET_L

1

1

YP

P

C

C

Q1

Q2

D1

D2

P = PresetC = ClearBoth active low

CLK

CLK

RESET_L reset to initial state (active low)


• Word description (110/101 input sequence detector):– Design a state machine with input A and output Y.

– Y = 1 when either sequence 1 1 0 or 1 0 1 has been detected oninput A on the last 3 consecutive rising clock edges (or ticks).

– Otherwise Y = 0

– Note: Correct sequences may overlap and still be accepted.


State Machine Design Example 2:State Machine Design Example 2:110/101 Detector110/101 Detector

A

CLK

y

0 1 0 1 0 1 1 0 1 0 0 0


State Machine Design Example 2: 110/101 DetectorState Machine Design Example 2: 110/101 Detector

Step1: Choosing StatesChoosing States• Possible states (What does the state machine need to

remember?):– Idle : Initial state, no starting 1 yet Y = 0

– Got1 : A = 1 on last tick Y = 0

– Got10 : Sequence A = 10 on last two ticks Y = 0

– Got101 : Sequence A = 101 on last three ticks Y = 1

– Got11 : Sequence A = 11 on last two ticks Y = 0

– Got110 : Sequence A = 110 on last three ticks Y = 1

A

CLK

y

Idle

Got1

Got10

Got101

Got11

Got110

Got10

Got101

Got101

Got10

IDLE

0 1 0 1 0 1 1 0 1 0 0 0

Idle



Step 1: State/Output Table

S

IDLE

Got1

Got10

Got101

Got11

Got110

A0

IDLE

Got10

IDLE

Got10

Got110

IDLE

1

Got1

Got11

Got101

Got11

Got11

Got101

Y

0

0

0

1

0

1

S*



Step 1: State Diagram

IDLE

0

Got1

0

Got10

0

Got101

1

Got11

0

Got110

1

0

0

1

0

0

0

0

11

1

1

1


Reset


State Machine Design Example 2: 110/101 DetectorState Machine Design Example 2: 110/101 DetectorSteps 3: Steps 3: State Assignment

• Step 3: Choose state variable assignments :– Initial state all 0s– Q1 = Y– Q3 = last A, so Q3* = A– minimum number of transitions S

IDLE

Got1

Got10

Got101

Got11

Got110

A0

IDLE

Got10

IDLE

Got10

Got110

IDLE

1

Got1

Got11

Got101

Got11

Got11

Got101

Y

0

0

0

1

0

1

S*

Q1 Q2 Q3

0 0 0

0 0 1

0 1 0

1 1 1

0 1 1

1 1 0

From Step 1:



• Step 4: Transition/output table

• Step 5: Choose D Flip-flops

• Step 6: Excitation table

– Same as Transition table

A0

000

010

000

010

110

000

ddd

ddd

1

001

011

111

011

011

111

ddd

ddd

Y

0

0

0

1

0

1

d

d

Q1*Q2* Q3*

=D1 D2 D3

Q1 Q2 Q3

0 0 0

0 0 1

0 1 0

1 1 1

0 1 1

1 1 0

1 0 0

1 0 1Unused states?



Steps 7: Excitation Equations• Step 7: Excitation equations

– D1, D2, D3 = F (A, Q1, Q2, Q3) d

1 1 d

d

1 d

Q1 Q2

Q3 A 00 01 11 10

00

01D1 :

11

10

d

1 1 1 d

1 1 1 d

d

Q1 Q2

Q3 A 00 01 11 10

00

01D3 :

11

10

d

1 1 d

1 1 1 d

1 1 1 d

Q1 Q2

Q3 A 00 01 11 10

00

01

D2 :

11

10

D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A

D2 = Q2•A + Q3

D3 = A (as planned!)



Step 8: Output Equations

• Step 8: Output equation

– Y = Q1 (as planned!)

• Step 9: Logic diagram– (3) D-Flip-flops + (3) 2-input gates + (1) 3-input AND gate +

(1) 4-input AND gate

– Draw the diagram.D1 = Q1’•Q2•Q3•A’ + Q2•Q3’•A

D2 = Q2•A + Q3

D3 = A


State Machine Design ProcedureState Machine Design Procedure1. Build state/output table (or state diagram) from word

description using state names.

2. Minimize number of states (optional).

3. State Assignment: Choose state variables and assign bitcombinations to named states.

4. Build transition/output table from state/output table (or statediagram) by substituting state variable combinations insteadof state names.

5. Choose flip-flop type (D, J-K, etc.)

6. Build excitation table for flip-flop inputs from transition table.

7. Derive excitation equations from excitation table.

8. Derive output equations from transition/output table.

9. Draw logic diagram with excitation logic, output logic, andstate memory elements.


State Machine Design Using J-K Flip-FlopsState Machine Design Using J-K Flip-Flops• State machine design step 6 (building excitation table for

flip-flop inputs from transition table):– When using D flip-flops, since the next state Q* = D, the excitation

table is the same as the transition table with Q* replaced with D.

– In the case of J-K flip-flops, the next state is given by:Q* = J . Q’ + K’. Q

– In this case we cannot rearrange the characteristic equation to findseparate equations for J, K.

– Instead an application (or excitation) table for J-K flip-flops is used toobtain the corresponding values of J, K for a given Q to Q* transition:

Q Q* J K

0 0 0 d0 1 1 d1 0 d 11 1 d 0

J-K Flip-Flop Excitation Table


State Machine Design Example 1:State Machine Design Example 1:110 Detector (Repeated Using J-K Flip-Flops)110 Detector (Repeated Using J-K Flip-Flops)

• Word description (110 input sequence detector):– Design a state machine with input A and output Y.

– Y should be 1 whenever the sequence 1 1 0 has been detected onA on the last 3 consecutive rising clock edges (or ticks).

– Otherwise, Y = 0


A

CLK

Y

0 1 1 0 0 1 1 1 0 1 1 1


State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorStep 1: State/Output Table and Diagram

S

No1s

First1

Two1s

ALL

A0

No1s

No1s

ALL

No1s

1

First1

Two1s

Two1s

First1

Y

0

0

0

1

State Table

S*

NO1s

0

First1

0

Two1s

0

ALL

11

1

1

0

0

0

State DiagramReset


1

0


• Steps 1-4: No change.

• Step 5: Choose J-K Flip-Flops

• Step 6: Excitation table: Use J-KFlip-Flop Excitation Table.

State Machine Design Example 1: 110 DetectorState Machine Design Example 1: 110 DetectorUsing J-K Flip-flops

Q1* Q2*

A0

00

00

10

00

1

01

11

11

01

Y

0

0

0

1

Q1 Q2

0 0

0 1

1 1

1 0

Q Q* J K

0 0 0 d0 1 1 d1 0 d 11 1 d 0

J-K Flip-Flop Excitation Table

Transition Table (step 4):

J1 K1, J2 K2

A0

0d, 0d

0d, d1

d0, d1

d1, 0d

1

0d, 1d

1d, d0

d0, d0

d1, 1d

Y

0

0

0

1

Q1 Q2

0 0

0 1

1 1

1 0

Excitation table (Step 6):


State Machine Design Example 1: 110 Detector Using J-K FFState Machine Design Example 1: 110 Detector Using J-K FFSteps 7, 8 : Excitation/Output Equations

• Step 7: Excitation equations: J1, K1, J2, K2 = F (A, Q1, Q2)

• Step 8: Output equation: Y = G (Q1, Q2)

Y = Q1•Q2’ (directly read from transition table)

0 0 d d

0 1 d d

Q1 Q2

A 00 01 11 10

0

1

J1 :

J1 = Q2•A

d d 0 1

d d 0 1

Q1 Q2

A 00 01 11 10

0

1K1 :

K1 = Q2’

0 d d 0

1 d d 1

Q1 Q2

A 00 01 11 10

0

1J2 :

J2 = A

d 1 1 d

d 0 0 d

Q1 Q2

A 00 01 11 10

0

1

K2 :

K2 = A’


• Registers.

• Shift Registers:– Serial in, serial out shift register

– Serial in, parallel out shift register

– Parallel in, serial out shift register

– Parallel in, parallel out shift register

– Shift Register Applications

• Counters:– Ripple Counters

– Synchronous Counters

– Counter Applications

Registers & CountersRegisters & Counters


RegistersRegisters• An n-bit register is a collection of n D flip-flops with a

common clock used to store n related bits.

D1Q

CLR

Q

Q /1Q

1D

D2Q

CLR

Q

Q /2Q2D

D3Q

CLR

Q

Q /3Q3D

D4Q

CLR

Q

Q /4Q4D

CLK

/CLR

74LS175 Example: 74LS175 4-bit register

CLKCLR

4Q4Q3Q3Q2Q2Q1Q1Q

74LS175

1D

2D

3D

4D


Shift RegistersShift Registers

• Multi-bit register that moves stored data bits left/right( 1 bit position per clock cycle)– Shift Left is towards MSB

0 1 1 1 LSI

Q3 Q2 Q1 Q0

1 1 1 LSI

Q3 Q2 Q1 Q0

RSI 0 1 1 1

Q3 Q2 Q1 Q0

RSI 0 1 1

Q3 Q2 Q1 Q0

– Shift Right (or Shift Up) is towards MSB


Serial In, Serial Out Shift RegisterSerial In, Serial Out Shift Register

D Q

CLK

D Q

CLK

D Q

CLK

•••

SERIN

CLOCK

SEROUT

For a n-bit SRG:Serial Out = Serial In delayedby n clock period

4-bit shift register example:serin: 1 0 1 1 0 0 1 1 1 0serout: - - - - 1 0 1 1 0 0clock:

SRG n>SI SO


Serial In, Parallel Out Shift registerSerial In, Parallel Out Shift register

D Q

CLK

D Q

CLK

D Q

CLK

•••

SERIN

CLOCK

nQ

2Q

1Q

Serial to Parallel Converter

4-bit shift register example:serin: 1 0 1 1 0 0 1 1 1 01Q: - 1 0 1 1 0 0 1 1 12Q: - - 1 0 1 1 0 0 1 13Q: - - - 1 0 1 1 0 0 14Q: - - - - 1 0 1 1 0 0clock:

SRG n>SI 1Q

•••

2Q

nQ (SO)


Parallel In, Serial Out Shift RegisterParallel In, Serial Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

•••

SEROUT

•••

LOAD/SHIFT

1D

2D

ND

S

L

S

L

S

L

1Q

2Q

NQ

Parallel to SerialConverter

Load/Shift=1 Di Qi

Load/Shift=0 Qi Qi+1


Parallel In, Parallel Out Shift RegisterParallel In, Parallel Out Shift Register

SERIN

CLOCK

D Q

CLK

D Q

CLK

D Q

CLK

•••

•••

LOAD/SHIFT

1D

2D

ND

1Q

2Q

NQ

S

L

S

L

S

L

General Purpose:Makes any kind of(left) shift register


BiBi-directional Universal Shift Registers-directional Universal Shift Registers

4-bit Bi-directional Universal (4-bit) PIPO

CLK CLR S1 S0

LIN D QDC QCB QBA QARIN

11

1

10

9

7

6

4

5

3

2

12

13

14

15

74x194Modes:HoldLoadShift RightShift Left

R L

Mode Next state

Function S1 S0 QA* QB* QC* QD*

Hold 0 0 QA QB QC QDShift right/up 0 1 RIN QA QB QCShift left/down 1 0 QB QC QD LINLoad 1 1 A B C D


Universal SR Circuit

RIGHT

CLK

/CLR

LIN

D

(11)

(1)

(7)

(6) D Q

CLK

CLR

10

00

11

01

(12)QD

S1 S0

SL

HO

LD

SR

LEFT

74x194

D Q

CLK

CLR01

11

00

10

(15) QA

S1

S0

A

RIN

(10)

(9)

(3)

(2)


Shift Register ApplicationsShift Register Applications• State Registers

– Shift registers are often used as the state register in a sequentialdevice. Usually, the next state is determined by shifting right andinserting a primary input or output into the next position (i.e. a finitememory machine)

– Very effective for sequence detectors

• Serial Interconnection of Systems– keep interconnection cost low with serial interconnect

• Bit Serial Operations– Bit serial operations can be performed quickly through device

iteration

– Iteration (a purely combinational approach) is expensive (in terms of# of transistors, chip area, power, etc).

– A sequential approach allows the reuse of combinational functionalunits throughout the multi-cycle operation


Shift Register Applications:Shift Register Applications:

Serial Interconnection of Systems Serial Interconnection of Systems

Serial DATAParallel-to-serialconverter

ParallelDatafrom

A-to-Dconverter

Serial-to-parallelconverter

ParallelData toD-to-Aconverter

Control

Circuits

CLOCK

/SYNC

TransmitterControl

Circuits

Receiver

n nOne bit


Shift Register Applications Example:Shift Register Applications Example:

8-Bit Serial Adder 8-Bit Serial Adder

...7 6 5 0>

x7 x6 x5 x0

...7 6 5 0>

y7 y6 y5 y0

...7 6 5 0>

FACout S

Cin A BD Q

CLK

CLR

CLK

CLEAR_Cz7 z6 z5 z0...

CTL Sequential Implementation of:Z[7..0] = X[7..0] + Y[7..0]

V


CountersCounters• Clocked sequential circuit with single-cycle state

diagram– Modulo-m counter = divide-by-m counter

–

– Most Common:

n-bit binary counter, where m = 2n Ù n flip-flops,counts 0 … 2n-1

S3

S2

S1

Sm


Q

Q

T

Q

Q

T

Q

Q

T

Q

Q

T

CLK

Q0

Q1

Q2

Q3

1 bit

divide-by-2

2 bit

divide-by-4

3 bit

divide-by-8

4 bit

divide-by-16

UsesMinimalLogic

4-bit Ripple Counter4-bit Ripple Counter


Ripple Counter TimingRipple Counter Timing

CLK

Q0

Q1

Q2

0 1 2 3 4

1∆

2∆

3∆


Ripple Counter ProblemRipple Counter Problem

n • TCQ for MSB change for n-bit ripple counter => minimum clk period

CLK

Q0

Q1

Q2

7 Should be 0 1 2

1∆

2∆

3∆


Synchronous CountersSynchronous Counters

• All clock inputs connected to common CLKsignal

– All flip-flop outputs change simultaneouslytCQ after CLK

– Faster than ripple countersripple counters

– More complex logic

– Most frequently used type of counter


Synchronous Serial CounterSynchronous Serial Counter

• Flip-flops enabledwhen all lowerflip-flops = 1.

• Enable propagatesserially — limitsspeed

• Requires(n-1) ∆ ∆ t < TCLK

• All outputs changesimultaneously tCQ

after CLK

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

QEN

>T

QEN

>T

QEN

>T

∆ t

∆ t

∆ t


Synchronous Parallel CounterSynchronous Parallel Counter

• Single-level enable logicper flip-flop

• Fastest and mostcomplex type of counter

• Requires ∆ ∆ t < TCLK

• All outputs changesimultaneously tCQ afterCLK

>T

QEN

>T

QEN

>T

QEN

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3


74X163 4-bit Synchronous Parallel Counter74X163 4-bit Synchronous Parallel Counter

>CLK

CLRLDENPENTABCD

QAQBQCQD

RCO

74X163

LSB

MSB

RCO = Ripple Carry Out,when Count = 1111 and ENT= 1

Common ClockSynchronous ClearSynchronous LoadCount Enable = ENP • ENT

Load Data Inputs


74X163 State Table74X163 State Table

Inputs Current State Next State

/CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA*

0 X X X 1 0 X X 1 1 0 X 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

0 0 0 0 D C B A QD QC QB QA QD QC QB QA 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0

ClearLoadHoldHoldCount . . .


>CLK

UP/DNLDENPENTABCD

QAQBQCQD

RCO

74X169 UP/DN = 1 = up Ù RCO = 15

UP/DN = 0 = down Ù RCO = 0

up down up

Ex: 0,1,2, 1,0,15,14, 15,0,1,2

RCO RCO

74X169 Up/Down Counter74X169 Up/Down Counter


Counter ApplicationsCounter Applications• Count the number of times an event takes place

• Control the number of steps in a sequence of fixedactions (a sequencer)

• Generate timing signals (frequency divider, etc.)

ENTER

EXIT>UP

DOWNCOUNTER

# of spaces Comparator< =

LotOpen

LotFull

CLK CTR DIV 6

>

EN

Decoder

124

01

6

2345

7

CLR_RIN_AIN_BEXEEXEOUT_C


• Read Only Memory (ROM)– Structure of diode ROM

– Types of ROMs.

– ROM with 2-Dimensional Decoding.

– Using ROMs for Combinational Logic

• Read/Write Memory

(Random Access Memory, RAM):

– Types of RAM:• Static RAM (SRAM)

• Dynamic RAM (DRAM)

– SRAM Timing

– DRAM Timing

Memory DevicesMemory Devices


Read-Only Memory (ROM)Read-Only Memory (ROM)

• A combinational circuit with n inputs and b outputs:

2n x bROM

AddressinputsA(n-1, ... , 0)

n b DataoutputsD(b-1, ... , 0)

• Programmable values determined by user

• Nonvolatile contents retained without power

• Uniform (Random) Access delay is uniform for all addresses


Read-Only Memory (ROM)Read-Only Memory (ROM)

• Two views of ROM:

– ROM stores 2n words of b bits each, or

– ROM stores an n-input, b-output truth table

Example: A1 A0 D3 D2 D1 D0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0

Stores 4 4-bit words, orstores 4 functions of 2input variables

b = 4 n = 2


Internal Structure of 4Internal Structure of 4×4×4×4×4 Diode ROM Diode ROM

D0

D1

D2

D3

2 to 4Decoder

A1

A0

Bit Lines

/w0

/w1

/w2

/w3

Diode 1

No Diode 0

0101

0001

1000

1111

1 of n Word Lines

R0R1R2R3

+5 V


Types OfTypes Of ROMs ROMs• Mask ROM

– Connections made by the semiconductor vendor

– Expensive setup cost, Several weeks for delivery. High volume only

– Bipolar or MOS technology

• PROM– Programmable ROM

– Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses

– Bipolar technology

– One-time programmable

• EPROM– Erasable Programmable ROM

– Charge trapped on extra “floating gate” of MOS transistors

– Exposure to UV light removes charge. Limited number of erasures (10-100)

• EEPROM (E2ROM)– Electrically Erasable ROM

– Not RAM (relatively slow charge/discharge)

– limited number of charge/discharge cycles (10,000)

• Flash Memory– Electronically erasable in blocks

– 100,000 erase cycles

– Simpler and denser than EEPROM


ROM Type SummaryROM Type Summary

Type

Mask ROM

Mask ROM

PROM

EPROM

EEPROM

FLASH

Technology

NMOS,CMOS

Bipolar

Bipolar

NMOS, CMOS

NMOS

CMOS

Read Cycle

20-200 ns

<100 ns

<100 ns

25-200 ns

50-200 ns

25-200 ns

Write Cycle

4 weeks

4 weeks

5 minutes

5 minutes

10 µµs/byte

10 µµs/block

Comments

Write once; low power

Write once; high power; low density

Write once; high power; no maskcharge

Reusable; low power; no mask charge

10,000 writes/location limit

100,000 erase cycles


Internal Structure of Transistor ROMInternal Structure of Transistor ROM

R0R1R2R3

+5 V

/D3 /D2 /D1 /D0

Transistor 1

No transistor 0

w3

• Replace diodes with MOS transistors

• Change decoder to active-high outputs

1000


VDD

Floating gate

Active-highword lines

Active-lowbit lines

EPROM and EEPROM StructureEPROM and EEPROM Structure


Almost square chip

3 to 8Decoder

/w0

/w1

/w7

+5 V

0 78 to 1 mux

A5

A3

A2

A0

D0

•••

• • •

8 x 8 Diode Array

64 x 1 ROM with 2-Dimensional Decoding64 x 1 ROM with 2-Dimensional Decoding


Rowdecoder

Poweron

Storagearray

Columnmultiplexer

A0

A1

Am-1

Am

Am+1

An-1

/CS

/OE

Db-1 Db-2 D0

Poweron

Poweron

Internal 2Internal 2nn x b ROM Structure x b ROM Structure


UsingUsing ROMs ROMs for for Combinational Combinational Logic LogicExample A 3-input, 4-output combinational logic function:

Function: 2-to-4 Decoder with Polarity ControlA2 = Polarity (0 = active Low, 1= active High)A1, A0 = I1, I0 (2-bit input )D3...D0 = Y3...Y0 (4-bit decoded output)

Inputs Outputs

A2 A1 A0 D3 D2 D1 D0

0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0

8 × 4 ROM

A0 D0A1 D1A2 D2 D3

Y0 I1

POL Y1 Y2 Y3

I0


Read/Write Memory (RWM / RAM)Read/Write Memory (RWM / RAM)• RWM = RAM (Random Access Memory)

• Highly structured like ROMs

• Can store and retrieve data at (relatively) the same speed

• Static RAM (SRAM) retains data in latches (while powered)

• Dynamic RAM (DRAM) stores data as capacitor charge; allcapacitors must be recharged periodically (refresh).

• Volatile Memory: Both Static and Dynamic RAM

• Nonvolatile Memory: Data retained when power lost= ROMs, NVRAM (w/battery), Flash Memory


Basic Structure of SRAMBasic Structure of SRAM

• Address/Control/Data Out lines like a ROM (Reading)

+ Write Enable (WE) and Data In (DIN)(Writing)

2n x b RAMA0

A1

An-1

DIN0DIN1

WEOECS

DINb-1 DOUTb-1

DOUT1

DOUT0


One Bit of SRAMOne Bit of SRAM

• SEL and WR asserted → → IN data stored in D-latch (Write)

• SEL only asserted → → D-latch output enabled (Read)

• SEL not asserted → → No operation

D Q

/WR/SEL

IN OUT INSELWR

OUT

C


INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

3-to-8Decoder

/WE/CS

/OE DOUT3 DOUT2 DOUT1 DOUT1

0

1

2

3

4

5

6

7

210

A2A1A0

DIN3 DIN2 DIN1 DIN0

8 x 4SRAM


SRAM TimingSRAM Timing• During READ, outputs are combinational functions of ADDR,

CS, OE (like ROM)

– Inputs can freely change without problems (except forpropagation delay from last input change to output)

• During WRITE, data stored in latches, NOT FF’s.

– Thus, Setup & Hold on Data IN relative to trailing edge of/WR

• Address must be stable

– for setup time before /WR asserted, and

– for hold time after /WR deasserted

• to prevent “spraying” data to multiple rows

• /WR asserted when BOTH /CS and /WE asserted

• /WR deasserted when EITHER /CS or /WE deasserted


ADDR

/CS

/OE

DOUT

stable stable stable

valid valid valid

tAA t OZ tOEtOZ tOE

tOH

≥tAA

tACS

max(tAA, tACS)

Primary Spec for SRAMs

READ Timing (SRAM)READ Timing (SRAM)


WRITE Timing (SRAM)WRITE Timing (SRAM)

ADDR

/CS

/WE

DIN

stable stable

valid

tDS tDHtDS tDH

valid

tWPtAS tAH

tCSWtAStCSW

(WE-controlled write) (CS-controlled write)

tWP tAH


INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

INSELWR

OUT

2-to-4Decoder

/WE/CS

/OE

0

1

2

3

10

A1A0

4-to-1 MuxES

2-to-4Decoder

A3-A2

DO

Example: 16 x 1 SRAM Example: 16 x 1 SRAM → → → → 4 x 4 Array4 x 4 ArrayD1


9 to 512Decoder

A

A

9

7

512 512 ×128

128to 1Mux

• ••

• • •

D0 D1 D7

512 ×128

512 ×128

512 ×1024Array

128to 1Mux

128to 1Mux

128 128 128

64K x 8 RAM with 2-D Decoding64K x 8 RAM with 2-D Decoding


Classic DRAM OrganizationClassic DRAM Organization


Logical Diagram of A Typical DRAMLogical Diagram of A Typical DRAM


64K x 1 DRAM64K x 1 DRAMword line

bit line

1-bit DRAM cell

Rowdecoder

256 x 256array

Row register,Data mux/demux

ADDRControl

/8

/RAS/CAS

/WE

Col ADDR

Row ADDR

Control

ADDR

Din

Dout

RASCASWE

/8

64K x 1 DRAM


Standard Asynchronous DRAM Read TimingStandard Asynchronous DRAM Read Timing

Valid Data

tRAC: Minimum time from RAS (Row Access Strobe) line falling to the valid data output.Usually quoted as the nominal speed of a DRAM chip. For a typical 4Mb DRAM tRAC = 60 ns

tRC: Minimum time from the start of one row access to the start of the next.tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns


Four Key DRAM Timing ParametersFour Key DRAM Timing Parameters• tRAC: Minimum time from RAS (Row Access Strobe) line falling to the valid data output.

– Usually quoted as the nominal speed of a DRAM chip

– For a typical 4Mb DRAM tRAC = 60 ns

• tRC: Minimum time from the start of one row access to the start of the next.

– tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns

• tCAC: minimum time from CAS (Column Access Strobe) line falling to valid data output.

– 15 ns for a 4Mbit DRAM with a tRAC of 60 ns

• tPC: minimum time from the start of one column access to the start of the next.

– About 35 ns for a 4Mbit DRAM with a tRAC of 60 ns


Simplified Asynchronous DRAM Read TimingSimplified Asynchronous DRAM Read Timing

Source: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html


Modern DRAM TimingModern DRAM Timing

• Fast-Page Mode, FPM DRAM (One RAS, multiple CAS)– Multiple bits of a row can be written before rewrite

– Complex control, but much faster

• Extended Data Out, EDO DRAM (One RAS, multiple CAS)– Latches the column address so that the next address can be prepared

while the output is read

– Saves ~10ns/read, and increase of 10-15%

– Even more complex control.

• SDRAM - Synchronous DRAM– Unlike normal DRAM, SDRAM is clocked.

– Multiple signals and banks (row-address registers) allow “pipelined”operation


Page Mode DRAM: MotivationPage Mode DRAM: Motivation


Fast Page Mode DRAM: OperationFast Page Mode DRAM: Operation


Simplified Asynchronous Fast Page ModeSimplified Asynchronous Fast Page Mode(FPM) DRAM Read Timing(FPM) DRAM Read Timing

Typical timing at 66 MHZ : 5-3-3-3For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 3 = 176 Mbytes/sec


FPM DRAM speed rated using tRAC ~ 50-70ns


• Extended Data Out DRAM operates in a similar fashion to Fast Page ModeDRAM except the data from one read is on the output pins at the same timethe column address for the next read is being latched in.

Simplified Asynchronous Extended Data Out (EDO)Simplified Asynchronous Extended Data Out (EDO)DRAM Read TimingDRAM Read Timing


Typical timing at 66 MHZ : 5-2-2-2For bus width = 64 bits = 8 bytes Max. Bandwidth = 8 x 66 / 2 = 264 Mbytes/sec

EDO DRAM speed rated using tRAC ~ 40-60ns


SynchronousSynchronousDynamic RAMDynamic RAM(SDRAM)(SDRAM)OrganizationOrganization

SDRAM speed is rated at max.clock speed supported:66MHZ = PC66100MHZ = PC100133MHZ = PC133150MHZ = PC150


Simplified SDRAM Read TimingSimplified SDRAM Read Timing

Typical timing at 133 MHZ (PC133 SDRAM) : 4-1-1-1For bus width = 64 bits = 8 bytes Max. Bandwidth = 133 x 8 = 1064 Mbytes/sec



RAM SummaryRAM SummarySRAM:

• Fast

• Simple Interface

• Moderate bit density (4 gates → → 4 to 6transistors)

• Moderate cost/bit

DRAM (Dynamic RAM):

• moderate speed

• complex interface

• High bit density (1 transistor cell)

• Low cost/bit

Small systemsor

very fastapplications

(cache memory)

Large Memories:PC’s

Mainframes

Documents

Digital Combi Plus Seq Ckt Design