Digital Back-end for KATDigital Back-end for KAT

Alan LangmanAlan Langman

June 2006June 2006

OutlineOutline

Overview of the Karoo Array TelescopeOverview of the Karoo Array Telescope LocationLocation PerformancePerformance OperationOperation

Requirements for Digital Back-endRequirements for Digital Back-endDigital Back-end architectureDigital Back-end architectureImplementationImplementation HardwareHardware FirmwareFirmware

Karoo Array TelescopeKaroo Array Telescope

KAT System OverviewKAT System Overview

Cluster Horn (7 HV)

Dish

Positioner

Front-end receiver

Station array

Station Processor

(20 antennasX7(HV) beams)

Karoo Site Operations centre

User (Scientist)

Cape Town Site

Remote

Observation data

Data products

Station Controller

RF/Cntrl

X

Kat Reference DesignKat Reference Design

ParameterParameter RequirementRequirement UnitsUnits

Collecting areaCollecting area 20 x 15m dishes (0.4% SKA)20 x 15m dishes (0.4% SKA)

SensitivitySensitivity 4545 m^2/Km^2/K

Operating freq: upper limitOperating freq: upper limit 17501750 MHzMHz

Operating freq: lower limitOperating freq: lower limit 12001200 MHzMHz

Instantaneous bandwidth (max)Instantaneous bandwidth (max) 256256 MHzMHz

Freq channelsFreq channels 6553665536

Polarization purityPolarization purity 4040 dBdB

Max baselineMax baseline 1800-30001800-3000 mm

Field of viewField of view 77 deg^2deg^2

Num of beamsNum of beams 77

KAT Operational ModesKAT Operational Modes

DSP StrategyDSP Strategy

Develop a low cost Develop a low cost generic Digital Signal generic Digital Signal ProcessingProcessing Backend for KAT Backend for KAT ScalableScalable and and UpgradeableUpgradeableDesigned for Designed for LogisticLogistic Support (remote operation) Support (remote operation)Develop a signal processing Develop a signal processing frameworkframework that can that can be used for be used for RA DSP algorithmRA DSP algorithm development, development, verification, performance and cost predictionsverification, performance and cost predictions..Strong unifiedStrong unified (algorithm development, hardware (algorithm development, hardware and software implementation) and software implementation) testing framework.testing framework.

Digital Backend RequirementsDigital Backend Requirements

B=B=256MHz256MHz, , 65K65K channels, channels, 88 bit bit CorrelationCorrelation + + BeamformingBeamformingConnected element - Connected element - 190190 Baselines BaselinesTransientTransient Signal support Signal supportRFIRFI mitigation (excision) mitigation (excision)SpectralSpectral and and ContinuumContinuum Imaging Imaging10-60s dump rate10-60s dump rateFX FX (Polyphase) Correlator(Polyphase) CorrelatorCustom hardware, Custom hardware, FPGAFPGA reconfigurable logic reconfigurable logic

Single Beam Digital BackendSingle Beam Digital Backend

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

Design ConsiderationsDesign Considerations

MechanicalMechanical (backplane and cabling) (backplane and cabling)Timing Synchronization - PXIeTiming Synchronization - PXIeADC - ADC - National/AtmelNational/Atmel - Dual 1.5GS/s - Dual 1.5GS/sXilinxXilinx vs vs AlteraAltera <- Possibly support both <- Possibly support both10Ge10Ge vs vs InfinibandInfiniband vs vs MyrinetMyrinetDesign for Design for changingchanging requirements requirementsFirmware Development/DeploymentFirmware Development/DeploymentControl and MonitoringControl and Monitoring

Physical HardwarePhysical Hardware

ConceptualConceptual

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

Digital Receiver ModuleDigital Receiver Module

Digital Receiver in Card CageDigital Receiver in Card Cage

QuickTime™ and aTIFF (LZW) decompressor

are needed to see this picture.

Algorithm DevelopmentAlgorithm Development

Matlab/Simulink System Generator/BEE2Matlab/Simulink System Generator/BEE2 design processdesign process Mathematical Mathematical modelingmodeling Firmware generationFirmware generation TestingTesting Framework linked Matlab/Simulink Framework linked Matlab/Simulink Reusable, rapid applicationReusable, rapid application development development CASPER collaborationCASPER collaboration

Matlab SimulationsMatlab Simulations

Results Polyphase FilteringResults Polyphase Filtering

Embedded SoftwareEmbedded Software

Each board has Each board has PowerPCPowerPC processor processor

Runs Runs Linux/L4 Linux/L4

Management, control, configuration,testingManagement, control, configuration,testing

Simple Simple scriptable telnetscriptable telnet interface interface

RoadmapRoadmap

Experimental Prototype Demonstrator Experimental Prototype Demonstrator ((XDMXDM) ) July 2007July 2007 Single dish 7HVSingle dish 7HV horns link to 26m HartRao horns link to 26m HartRao

Advanced Prototype Demonstrator (Advanced Prototype Demonstrator (ADMADM)) Jan 2008 Jan 2008 Single dish 7HVSingle dish 7HV horns link to 26m HartRao horns link to 26m HartRao

Full KATFull KAT Digital Back-end Digital Back-end Dec 2009 Dec 2009

ConclusionConclusion

Building Digital Backend - 256MHz, 190 Building Digital Backend - 256MHz, 190 baseline, FX, beamformerbaseline, FX, beamformer

Following CASPER group, HERC - Following CASPER group, HERC - focusing on ‘”software” IP delaying focusing on ‘”software” IP delaying optimization of hardwareoptimization of hardware

XDM, ADM, KATXDM, ADM, KAT

Operational Dec 2009Operational Dec 2009