DIGILAB SX V Data Sheet - Altera connector for Altera download cable ... active cooling may be necessary . A 5V DC cooling fan is connect- ... DQ_21 AR15 U32 U44 SRAM_WE AP6 both

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DIGILAB SX V

Stratix V Prototyping Board

General

Description

The DIGILAB SX V is a universal FPGA prototyping platform based on Altera’s Stratix V device family. It can be used for ASIC prototyp-ing, hardware evaluation or as a verification acceleration vehicle

Features � Available with Altera Stratix V device in 1517 Pin FineLine BGA Package- 5SEEBH40C2 (standard)- 5SEE9 (on request)

� 338 user I/Os through- One Altera HSMC connector- Two Samtec QSH-060 (120 contact) connectors- Two 38 pin Mictor connectors- Nine DIL/SIL headers

� 2 MByte (512k x 32-bit) FLASH memory� 2 MByte (512k x 32-bit) SRAM � Configuration

- EPCQ512 non-volatile configuration memory (AS x1 mode)- Push-buttons for reset and configuration- Various LEDs for configuration status

� User Interface- 32 three-state DIP switches

with programmable pull-up/pull-down and32 user LEDs

- 16 two-state DIP switches- 8 push buttons, selectable low- or high active

with programmable pull-up/pull-down� Connector for SD/MMC cards� JTAG connector for Altera download cable� JTAG Multi-ICE connector� Interfaces with monitoring LEDs

- Two RS232 transceivers with 3-driver/3-receiver each- SPI interface connector- USB 1.1 transceiver (USB 2.0 support on request)

� Clocking- 80 MHz Crystal oscillator- 25 MHz Crystal oscillator- 3 SMA clock inputs

� Power supply circuitry� FPGA controlled active heat sink and temperature sensor

November 2014, Version 1.0

DIGILAB SX V - Stratix V Prototyping Board

Preface Environmental Requirements

The development board must be stored between -40°C and 85°C. The recommended operating temperature is between 0°C and 70°C. Please contact El Camino for availability information on DIGILAB SX V boards that support the industrial temperature range of -40°C to 85°C.

The board can be damaged without proper anti-statichandling.Anti-static precautions should be taken before handling the board.

Functional

Description

This section describes the elements of the DIGILAB SX V prototyping board. Figure 1 shows a block diagram of the board.

Figure 1: DIGILAB SX V Block Diagram

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The DIGILAB SX V is a general purpose prototyping platform. Figure 2 shows the basic mechanical setup of the DIGILAB SX V. The measurements can be used to develop and manufacture custom adapter boards. Contact El Camino if you require further details on the mechan-ical dimensions of the board.

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Figure 2: DIGILAB SX V Mechanical Setup - Top View

All measurements are in mm.

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Stratix V Device

The DIGILAB SX V board can be equipped with any Stratix V device in a H40-H1517 FineLine BGA package with 696 IOs. Devices current-ly supported in this package are the 5SEE) and the 5SEEB. Furthermore it is possible to select any speed grade. Pricing and availability of the board will depend on the Stratix V device chosen. The standard device is the 5SEEBH40C2

Disable Unused Resources

When implementing custom user designs it is important to disable un-used resources on the DIGILAB SX V, so that there are no bus conten-tions e.g. on the data bus connected to SRAM and FLASH.

In order to avoid contentions on the various switch and push button inputs it is recommended to either use the design template that is provided with the board or reserve all unused pins „As input tri-stated with weak pull-up resis-

tor“. The board may be damaged if this guideline is not followed.

The SRAM and FLASH devices have pull-up resistors on their active low select lines.

Power Supply

The DIGILAB SX V is meant to be used in a lab environment. It re-quires a 12V DC input and offers two optional power connectors. Power can be supplied through two banana jacks or a coaxial two pin power connector.

Table 1: Disable Unused Resources

Function Signal Stratix V Pin Value

SRAMSRAM_CE1 AN11 ’1’ or ’Z’

SRAM_CE2 AH15 ’1’ or ’Z’

FLASHFLASH_CE1_N AH10 ’1’ or ’Z’

FLASH_CE2_N AV19 ’1’ or ’Z’

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Table 2: Power Supply Options

Option Voltage Connector Description

Banana Jacks 12V DCJ22 (red) +12V

J23 (black) GNDFor use with a Lab power supply

2-Pin Coaxial Connector

12V DC J6For use with a standard power adapter(positive tip polarity)

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The DC input current when unconfigured and during configuration is a approximately 450 mA at 12V DC. The input current while the mainte-nance design is running and during self-test is approximately 550 mA.

Figure 3: DIGILAB SX V Power Supply

Thermal considerations

The total power consumption can vary significantly, depending on the implemented design and the clock fre-quencies. Refer to information from Altera for details on Stratix V power consumption. We strongly recommend to

do a power analysis and/or monitor the Stratix V case temperature dur-ing operation.

Depending on the design implemented and the total power consump-

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tion, active cooling may be necessary. A 5V DC cooling fan is connect-ed to J30. The fan can be controlled from within the FPGA by driving the PWM_FAN signal. Furthermore, the board is equipped with an ac-tive temperature sensor that is mounted with a thermal adhesive to the board in close proximity to the FPGA. The board comes with an en-crypted IP function, that reads the temperature once per second and con-trols the cooling fan. The IP function has the following IO ports and parameters and can be instantiated in a user design. Alternatively the fan control signal PWM_FAN can be left floating or driven high to perma-nently turn on the fan. During configuration the fan will be on, which gives some feedback on the functionality of the fan at each power or configuration cycle.

Figure 4: Fan Control

clk

reset_n

f an_o

ext_temp_o[7..0]

ext_temp_v ld_o

ser_temp_io

f an_control

inst

freq_mhz 80temp_low 60temp_high 75

Parameter Value

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SRAM

U31 and U32 are two 1 MByte (512k x 16) asynchronous SRAM devic-es. They are connected to the Stratix V device so that they can be used by any custom logic in the FPGA or by a Nios II processor as general-purpose memory. The two 16-bit devices can be used in parallel to im-plement a 32-bit wide memory subsystem. The SRAM shares a com-mon bus with the on-board FLASH devices.

A data sheet for the SSRAM devices can be found at:URL: http://www.alliancememory.comType: AS7C38098A

The pinout can be found in the following table or it can be extracted from the netlist, that comes with the board.

CFI Flash Memory

U60 and U44 are two 1 MByte (512k x 16) CFI FLASH memory de-vices that can be used as a general purpose, non-volatile storage. They are connected to the Stratix V device so that they can be used by any custom logic in the FPGA or by a Nios II processor as general-purpose, non-volatile memory. The two 16-bit devices can be used in parallel to implement a 32-bit wide memory subsystem. The FLASH devices share a common bus with the on-board SRAM devices.

A data sheet for the Flash memory devices can be found at:URL: http://www.sst.comType: SST39VF800A

Table 3: Fan Control Ports and Parameters

Name Direction Function

Parameter

freq_mhz in Specifies the clock frequency in MHz. Used to calculate timing for accessing the temperature sensor

temp_low in Temperature in degree Celsius at which the fan will start to receive PWM pulses

temp_high in Temperature in degree Celsius at which the fan will be fully turned on

Ports

clk in Clock input

reset_n in Low active reset input, de-assertion should be synchronized to clk externally

fan_o out Control signal for the fan; should be connected to PWM_FAN on the board

ext_temp_o[7..0] out Actual temperature in degree Celsius (signed), valid while ext_temp_vld_o is high

ext_temp_vld_o out High while ext_temp_o is valid

ser_temp_io inoutInterface to the temperature sensor, connect to SER_TEMP_DATA_PCB through a bi-directional pin

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The pinout can be found in the following table or it can be extracted from the netlist, that comes with the board.

Table 4: Memory Signals - SRAM U31/U32 and FLASH U60/U44

SignalStratix V

U30SRAM FLASH Signal

Stratix IIIU30

SRAM FLASH

DQ_0 AM14 U31 U60 A0 AJ6 both both

DQ_1 AN14 U31 U60 A1 AV8 both both

DQ_2 AH12 U31 U60 A2 AN10 both both

DQ_3 AN12 U31 U60 A3 AG10 both both

DQ_4 AJ12 U31 U60 A4 AW8 both both

DQ_5 AG12 U31 U60 A5 AV10 both both

DQ_6 AL12 U31 U60 A6 AW10 both both

DQ_7 AK12 U31 U60 A7 AV11 both both

DQ_8 AK11 U31 U60 A8 AN8 both both

DQ_9 AH13 U31 U60 A9 AL11 both both

DQ_10 AM13 U31 U60 A10 AR6 both both

DQ_11 AL13 U31 U60 A11 AR9 both both

DQ_12 AM10 U31 U60 A12 AU7 both both

DQ_13 AJ10 U31 U60 A13 AU8 both both

DQ_14 AP12 U31 U60 A14 AT9 both both

DQ_15 AN15 U31 U60 A15 AT17 both both

DQ_16 AP10 U32 U44 A16 AU17 both both

DQ_17 AG9 U32 U44 A17 AT18 both both

DQ_18 AH9 U32 U44 A18 AU9 both both

DQ_19 AN9 U32 U44 A19 AR11 both

DQ_20 AP9 U32 U44 A20 AJ7 both

DQ_21 AR15 U32 U44 SRAM_WE AP6 both

DQ_22 AR14 U32 U44 SRAM_OE AU16 both

DQ_23 AP15 U32 U44 SRAM_CE1 AN11 U31

DQ_24 AU10 U32 U44 SRAM_LB1 AM8 U31

DQ_25 AT11 U32 U44 SRAM_UB1 AM11 U31

DQ_26 AU11 U32 U44 SRAM_CE2 AH15 U32

DQ_27 AT12 U32 U44 SRAM_LB2 AT15 U32

DQ_28 AU12 U32 U44 SRAM_UB2 AU15 U32

DQ_29 AR12 U32 U44 FLASH_OE_N AP18 both

DQ_30 AT14 U32 U44 FLASH_WE_N AV13 both

DQ_31 AU14 U32 U44 FLASH_CE1_N AH10 U60

FLASH_CE2_N AV19 U44

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RS-232 Serial Interfaces

The DIGILAB SX V provides two independent bidirectional RS-232 serial I/O interfaces. The board contains the transceiver (U3, U4), how-ever the logic controller (UART) must be implemented in the Stratix V device.

J17 and J18 are standard RJ45 connectors. These connectors can be used for communication with a host computer using an adapter cable to connected for example to a COM port. In addition, all RS-232 signals are available through J13, a Samtec QSH-30 connector, which allows to connect custom add-on or interface boards.

J17 and J18 can transmit all RS-232 signals. The Stratix V design may use only signals it needs, such as RXD and TXD. LEDs are connected to all RS232 signals, giving a visual indication, whether data is being transmitted or received. The following table shows the pin mapping be-tween the Stratix V device and the RS232 signals.

A data sheet for the RS-232 transceiver can be found at:URL: http://www.maxim-ic.comType: MAX3238

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SPI Interface

The DIGILAB SX V provides an SPI interface through general purpose Stratix V I/O pins. Besides an ESD protection, there are no special buff-ers or level shifters implemented. In order to use the SPI interface, a log-ic controller for SPI must be implemented in the Stratix V device.

The SPI interface is available through J28, a standard dual row 2x5 header. In addition, all SPI signals are available through J13, a Samtec QSH-30 connector, which allows to connect custom add-on or interface boards.

LEDs are connected to all SPI signals, giving a visual indication, when-ever data is being transmitted or received. The following table shows the pin mapping between the Stratix V device and the SPI signals.

Table 5: RS-232 Interfaces

Interface FunctionStratix V - U30

RJ45Connector

Samtec Connectors

J13Signal Pin

J17

RS232_0

DTR USART_DTR_0 AM17 J17 - 1, 2 22

TXD USART_TXD_0 AG16 J17 - 5 8

RTS USART_RTS_0 AU18 J17 - 7 20

DSR USART_DSR_0 AP19 J17 - 3 30

RXD USART_RXD_0 AR19 J17 - 6 6

CTS USART_CTS_0 AR18 J17 - 8 18

Enable USART0_EN AW19 n/a n/a

n/a USART_SCK_0 AV17 n/a 10

J18

RS232_1

DTR USART_DTR_1 AE19 J18 - 1, 2 21

TXD USART_TXD_1 AD18 J18 - 5 7

RTS USART_RTS_1 AD17 J18 - 7 19

DSR USART_DSR_1 AL18 J18 - 3 29

RXD USART_RXD_1 AM19 J18 - 6 5

CTS USART_CTS_1 AN19 J18 - 8 17

Enable USART1_EN AN18 n/a n/a

n/a USART_SCK_1 AA15 n/a 9

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USB Interface

On the board, there is a USB transceiver that complies with USB 1.1, as well as a USB connector and a line protection device. USB 2.0 can be supported with a different, pin-compatible transceiver, that can be mounted on a request basis. The board provides the transceiver (U6), however the USB controller must be implemented in the Stratix V de-vice.

J31 is a standard USB Type B connector. This connector can be used for communication with a host computer using a standard USB cable. In addition, the local signals of the USB transceiver are available through J13, a Samtec QSH-30 connector, which allows to connect custom add-on or interface boards.

LEDs are connected to the USB data signals, giving a visual indication whenever data is being transmitted. Furthermore, there is a LED (D57) that monitors the USB input voltage.

The USB interface has programmable pull-up resistors. They can be controlled through the signals USB_P_PULLUP (monitored through LED D55) and USB_N_PULLUP (monitored through LED D56) from within the FPGA.Furthermore the presence of the USB 5V voltage can be monitored with LED D57 and the FPGA input VUSB.

Table 6: SPI Interface

FunctionStratix V - U30

J282x5 Header

Samtec Connectors

J13Signal Pin

GND n/a n/a 1 n/a

GND n/a n/a 2 n/a

3.3V n/a n/a 3 n/a

SCK SPI_SCK AL16 4 39

MISO SPI_MISO AD16 5 32

MOSI SPI_MOSI AA14 6 31

PCS_2 SPI_PCS_N_2 AW13 7 42

PCS_3 SPI_PCS_N_3 AM16 8 41

PCS_0 SPI_SS_PCS0_N AW17 9 40

PCS_1 SPI_PCS_N_1 AF16 10 43

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A data sheet for the USB transceiver can be found at:URL: http://www.fairchildsemi.comType: USB1T11A (for USB 2.0: USB1T20)

The following table shows the pin mapping between the Stratix V de-vice and the USB signals.

Multi-ICE JTAG Interface

The Multi-ICE JTAG connector allows the connection of a Multi-ICE interface unit to the board. The connection enables debugging of ARM processors implemented inside the Stratix V FPGA. All signals feature ESD protection and are directly connected to standard Stratix V I/O pins. The signal mapping can be found in the following table:

Table 7: USB Interface

FunctionStratix V - U30

Samtec ConnectorsJ13

Signal Pin

VPO USB_TXD AP16 53

VMO USB_EOP AR17 55

OE_N USB_TXOE_N AL10 54

SUSPND USB_ON_N AF10 56

VP USB_RXDP AW14 52

VM USB_RXDM AN16 51

RCV USB_RXD AV14 44

D+ Pull-Up USB_P_PULLUP AV16 n/a

D- Pull-Up USB_N_PULLUP AW16 n/a

VBUS Monitor VUSB AP13 n/a

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DIP Switches (two-state)

The DIGILAB SX V has 16 two-state DIP switches. They switch be-tween GND (when on) and a 10k Ohm pull-up resistor (when off). The following diagram shows the functionality of the two-state switches.

Figure 5: Two-state DIP switches

Table 8: Multi-ICE JTAG Connector

SignalJ1 Connector

SignalStratix V

U30PinPin Pin

3.0V 2 1 3.0V n/a

GND 4 3 ICE_TRST_N AG19

GND 6 5 ICE_TDI AH19

GND 8 7 ICE_TMS AJ19

GND 10 9 ICE_TCK AK18

GND 12 11 ICE_RTCK AH18

GND 14 13 ICE_TDO AJ18

GND 16 15 ICE_SRST_N AF19

GND 18 17 ICE_DBGRQ AG18

GND 20 19 ICE_DBGACK AE18

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The signal mapping for the 2-state DIP switches can be found in the fol-lowing table:

Table 9: DIP Switches (two-state)

DIP Switch SignalStratix V - U30

Pin

J2

1 SW_SEL1 AL29

2 SW_SEL2 AM29

3 SW_SEL3 AK29

4 SW_SEL4 AJ29

J32

1 SW_SEL5 AP28

2 SW_SEL6 AR28

3 SW_SEL7 AL27

4 SW_SEL8 AL28

J33

1 SW_SEL9 AM28

2 SW_SEL10 AN28

3 SW_SEL11 AA26

4 SW_SEL12 AA27

J34

1 SW_SEL13 AA28

2 SW_SEL14 AA29

3 SW_SEL15 AB27

4 SW_SEL16 AC27

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DIP Switches (three-state) and User LEDs

The DIGILAB SX III has a total of 32 three-state DIP switches in four groups of eight.

Figure 6: Three-state DIP switches

The signals driven by these switches are also connected to programma-ble pull-up/down resistors, as well as LEDs through drivers. The FPGA signal SWn_P can be used as an input, driven by the switch and pulled high or low through SWn_P_PU. Alternatively, when the switch is not used, the signal SWn_P can be used as output driven by the FPGA and controlling the LED. The LEDs will show the current status of the line.

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.

Table 10: Three-state DIP switches and LEDs

Switch LED

Signal Pull-Up/Down Resisotr

NameStratix VU30 - Pin


U14

1 LED1 SW1_P AL21 SW1_P_PU AL15

2 LED2 SW2_P AL14 SW2_P_PU AJ15

3 LED3 SW3_P AP22 SW3_P_PU AW22

4 LED4 SW4_P AU23 SW4_P_PU AT23

5 LED5 SW5_P AG23 SW5_P_PU AD22

6 LED6 SW6_P AF23 SW6_P_PU AG22

7 LED7 SW7_P AR22 SW7_P_PU AJ20

8 LED8 SW8_P AL20 SW8_P_PU AJ21

U15

1 LED9 SW9_P AW23 SW9_P_PU AV22

2 LED10 SW10_P AV23 SW10_P_PU AE22

3 LED11 SW11_P AF22 SW11_P_PU AK21

4 LED12 SW12_P AL22 SW12_P_PU AD23

5 LED13 SW13_P AE23 SW13_P_PU AM23

6 LED14 SW14_P AN23 SW14_P_PU AM22

7 LED15 SW15_P AN22 SW15_P_PU AU27

8 LED16 SW16_P AU25 SW16_P_PU AR24

U41

1 LED17 SW17_P AT24 SW17_P_PU AP25

2 LED18 SW18_P AN24 SW18_P_PU AN25

3 LED19 SW19_P AT26 SW19_P_PU AD27

4 LED20 SW20_P AE27 SW20_P_PU AH25

5 LED21 SW21_P AU26 SW21_P_PU AV25

6 LED22 SW22_P AP27 SW22_P_PU AE25

7 LED23 SW23_P AC24 SW23_P_PU AH27

8 LED24 SW24_P AG27 SW24_P_PU AB24

U40

1 LED25 SW25_P AP24 SW25_P_PU AM25

2 LED26 SW26_P AR25 SW26_P_PU AF25

3 LED27 SW27_P AH24 SW27_P_PU AD24

4 LED28 SW28_P AW25 SW28_P_PU AE24

5 LED29 SW29_P AJ27 SW29_P_PU AU24

6 LED30 SW30_P AV26 SW30_P_PU AK27

7 LED31 SW31_P AR27 SW31_P_PU AW26

8 LED32 SW32_P AG25 SW32_P_PU AT27

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Push Buttons

The DIGILAB SX V features 8 user configurable push buttons. Through an 8-bit three-state DIP switch, the push buttons can be set to be active low, active high or disabled. Furthermore there are program-mable pull-up/down resistors for every push button signal. The follow-ing diagram shows the functionality of a single push button.

Figure 7: Push Buttons

Table 11: Push Buttons

Switch

Signal Pull-Up/Down Resisotr



SW

1 SW1 AB25 SW1_PU AJ24

2 SW2 AA25 SW2_PU AG24

3 SWP AC25 SW3_PU AE26

4 SW4 AC26 SW4_PU AD26

5 SW5 AJ26 SW5_PU AN27

6 SW6 AK26 SW6_PU AN26

7 SW7 AF26 SW7_PU AM26

8 SW8 AG26 SW8_PU AL26

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SD/MMC Connector

The DIGILAB SX V features an SD (Secure Digital)/MultiMediaCard (MMC) card connector (U61). This connector can be used to insert stan-dard SD/MMC cards. The SD/MultiMediaCard card is a universal low cost data storage and communication media. It was designed to cover a wide area of applications, such as electronic toys, organizers, PDAs, cameras, smart phones, digital recorders, MP3 players, etc. The SD/MultiMediaCard card communication is based on an advanced 7-pin se-rial bus. All relevant SD/MMC signals are connected directly to the Stratix V device. On the DIGILAB SX V, SD/Multi Media cards may be used as a flexible, non-volatile and mobile storage media. It is up to the user to create an interface between the SD/MMC card and e.g. a NIOS II or custom logic. Contact El Camino for information on avail-ability of ready to use SD/MMC interfaces, NIOS II library functions and drivers.

Table 12: SD/MMC Connector

SD Card Function ConnectorU61Pin

Stratix VU30

SD Mode SPI Mode Signal Pin

CD/DAT3 CS 1 MMC_RSV AB9

CMD DI 2 MMC_CMD AE9

CLK SCLK 5 MMC_CLK AC10

DAT0 DO 7 MMC_DAT AD12

DAT1 8 MMC_DAT2 AD9

DAT2 9 MMC9 AB10

WRITE_PROT_FRONT 12 MMC_WP1 AC9

CARD_DETECT 13 MMC_CDET AB12

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Debug Connectors

The DIGILAB SX V has various, different connectors that can be used to connect debugging logic to the board.

There are two 38 pin AMP/Tyco Matched Impedance Connectors (MICTOR) on the board. More information about these connectors can be found at:URL: www.tycoelectronics.comType: 2-5767004-2

On each of these connectors, there are 32 standard Stratix V user IOs in addition to two PLL clock outputs/user IOs .The signals of MICTOR connector J4 are routed directly to the FPGA and are therefor optimized for high speed. These pins connect to bank 8 of the FPGA which can be switched from 3.0V to 2.5V operation by opening jumper J12. The signals of J5 are also available through stan-dard dual row .100 inch headers (IOs on J24,25,26,27 and clocks on J3/J29) for easy access to individual signals.

The following tables lists the signal names and pin numbers for these connectors.

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Table 13: MICTOR connector J5

HeaderStratix VU30 - Pin

SignalJ5

SignalStratix VU30 - Pin

Header

Con. Pin Pin Pin Pin Con.

N/A N/A N/A GND 1 38 GND N/A N/A N/A

N/A N/A N/A GND 2 37 GND N/A N/A N/A

J3 1 AC30 LA_CLK0_J5_R 3 36 LA_CLK1_J5_R AB30 1 J29

J27

1 AN31 LA_A3_7 4 35 LA_A1_7 AP30 1

J24

3 AT33 LA_A3_6 5 34 LA_A1_6 AJ33 3

5 AL33 LA_A3_5 6 33 LA_A1_5 AK33 5

7 AH33 LA_A3_4 7 32 LA_A1_4 AK32 7

9 AF31 LA_A3_3 8 31 LA_A1_3 AH30 9

11 AH31 LA_A3_2 9 30 LA_A1_2 AR30 11

13 AG31 LA_A3_1 10 29 LA_A1_1 AE31 13

15 AJ32 LA_A3_0 11 28 LA_A1_0 AJ30 15

J26

1 AU32 LA_A2_7 12 27 LA_A0_7 AT32 1

J25

3 AM31 LA_A2_6 13 26 LA_A0_6 AR31 3

5 AW34 LA_A2_5 14 25 LA_A0_5 AV34 5

7 AP31 LA_A2_4 15 24 LA_A0_4 AP33 7

9 AV32 LA_A2_3 16 23 LA_A0_3 AU33 9

11 AW32 LA_A2_2 17 22 LA_A0_2 AR33 11

13 AV31 LA_A2_1 18 21 LA_A0_1 AU34 13

15 AW31 LA_A2_0 19 20 LA_A0_0 AU30 15

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Expansion Connectors

The DIGILAB SX V has various connectors that can be used to connect user logic or custom adapter boards.

There are two 120 pin (J15, J16) as well as one 160 pin (J35) Samtec QSH Hi-Speed connectors on the board. The latter one is based on Al-tera’s HSMC standard.More information about the connectors can be found on the Samtec website at:URL: www.samtec.comType: QSH-060-.../ASP-122953-01

Details on the pinout of these connectors can be found in the schematics or in the netlist, that is provided with the DIGILAB SX V.

Table 14: High-Speed MICTOR connector J4

Stratix VU30 - Pin

SignalJ5

SignalStratix VU30 - Pin

Pin Pin

N/A GND 1 38 GND N/A

N/A GND 2 37 GND N/A

AD30 LA_CLK3_J4 3 36 LA_Q1_CLK_J4 AE30

J25 LA_C1_7 4 35 LA_C3_7 K34

P26 LA_C1_6 5 34 LA_C3_6 J34

N26 LA_C1_5 6 33 LA_C3_5 K33

U25 LA_C1_4 7 32 LA_C3_4 J33

P28 LA_C1_3 8 31 LA_C3_3 G33

K24 LA_C1_2 9 30 LA_C3_2 N33

J26 LA_C1_1 10 29 LA_C3_1 M33

H26 LA_C1_0 11 28 LA_C3_0 U31

M27 LA_C0_7 12 27 LA_C2_7 T31

L27 LA_C0_6 13 26 LA_C2_6 L28

K31 LA_C0_5 14 25 LA_C2_5 K28

J31 LA_C0_4 15 24 LA_C2_4 N28

L31 LA_C0_3 16 23 LA_C2_3 M29

L30 LA_C0_2 17 22 LA_C2_2 R29

R30 LA_C0_1 18 21 LA_C2_1 P29

R31 LA_C0_0 19 20 LA_C2_0 K25

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Clocking

The DIGILAB SX V development board includes an 80 MHz oscillator, as well as an 25 MHz oscillator that drive the Stratix V FPGA. In addi-tion there are three SMA clock inputs, feeding comparators, driving into clock buffers. The clock buffers are driving the FPGA and various ex-pansion connectors. The signal length between A, B and C clocks are closely matched in order to provide minimal skew between the individ-ual, external clocks.

The Stratix V FPGA contains multiple phase locked loops (PLLs) and global clock networks for clock management. Stratix V fractional PLLs offer clock multiplication and division, phase shifting, programmable duty cycle, external clock outputs and more, allowing system-level clock management and skew control on the DIGILAB SX V.The following diagram shows all clock inputs and outputs and how they are connected to the individual PLLs and connectors.

All unused, dual purpose clock inputs are connected to GND on the board. It is important that these pins are either reserved as inputs or reserved as IOs driving ground in the user design.

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Figure 8: Clocking Circuitry

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Table 15: Clock Signals

SignalDir.at

FPGABoard Connection

Stratix VClock Signal

PLLStratix V

Pin

80MHz IN oscillator - U5CLK2PCLK5P

BLBC

AF29AK23

25MHz_A25MHz_B

IN oscillator - U71CLK21PCLK0P

TLBL

D33AV29

PCLKA_FPGA IN

J21(SMA)J15-41J16-41

PCLKA_FPGA1_LAPCLKA_FPGA1

CLK1PCLK13P

BLTR

AV28L6

PCLKB_FPGA IN

J19(SMA)J15-51J16-51

PCLKB_FPGA1_LAPCLKB_FPGA1

CLK3PCLK9P

BLBR

AG28AN6

PCLKC_FPGA IN

J20(SMA)J15-69J16-69

PCLKC_FPGA1 CLK4P BC AH22

PCLKIN_J15 IN J15-79 CLK12P TR G7

PCLKIN_J16 IN J16-79 CLK11P BR AV7

PER1CON_58_CLKIN IN J15-58 CLK14P TR B7

CLKIN_J15_118 IN J15-118 CLK15P TR D7

PER2CON_58_CLKIN IN J16-58 CLK10P BR AR8

CLKIN_J16_118 IN J16-118 CLK8P BR AL7

CLKOUT_J15_9 OUT J15-9 CLKOUT2 TR A3




CLKOUT_J16_9 OUT J16-9 CLKOUT0 BR AT6

CLKOUT_J16_19 OUT J16-19 CLKOUT1 BR AU6

CLKOUT_J16_29 OUT J16-29 CLKOUT3 BR AR7

CLKOUT_J16_89 OUT J16-89 CLKOUT2 BR AP7

MEZ_CLK_IN_P/N IN J35-96/98 CLK23P/N TL R32/P32

MEZ_CLK2_IN_P/N IN J35-156/158 CLK22P/N TL N32/M32

MEZ_CLK_OUT_P/N OUT J35-95/97 TX122P/N - M20/L20

MEZ_CLK2_OUT_P/N OUT J35-155/157 CLKOUT0/1 TL P34/N34

LA_CLK3_J4 OUT J4-3 CLKOUT0 BL AD30

LA_Q1_CLK_J4 OUT J4-36 CLKOUT1 BL AE30

LA_CLK1_J5 OUT J5-36, J29-1 CLKOUT2 BL AB30

LA_CLK0_J5 OUT J5-3, J3-1 CLKOUT3 BL AC30

El Camino GmbH 26


Configuration The DIGILAB SX V uses an Altera EPCQ512 serial configuration de-vice for non-volatile configuration data storage. The FPGA is setup for Standard Active Serial configuration mode. Upon power-up the DIGI-LAB SX V will start configuration from address 0x0 of the serial con-figuration device. A configuration cycle can also be triggered by pushing SW9 (marked as „SW9 Config“) which pulls the nConfig input of the FPGA low.In addition, the FPGA can be programmed through the JTAG interface.

There is a device errata for the EPCQ device which says that x4 mode is currently not supported. Although the EPCQ is wired in x4 mode on the board, the programming files needs to be generated for x1 mode.

JTAG Connector

J14 is a 10-pin JTAG interface connector compatible with current Al-tera ByteBlaster, USB-Blaster and Ethernet-Blaster download cables. The JTAG connection can be used for any of the following purposes:

� Quartus II software can configure the Stratix V device (U30) with a new bitstream (such as .sof) file.

� Quartus II can re-program the serial configuration device EPCQ with a JTAG indirect configuration file (.jic)

� The following Altera JTAG accessible functions can be used:- SignalTap II Logic Analyzer- In-System Memory Content Editor- Logic Analyzer Interface Editor- In-System Sources and Probes- NIOS II Debugging Interface

The JTAG programming interface is not available if the Stratix V has been protected by programming a non-volatile security key.

The JTAG connection is most commonly used to download user config-uration files (such as .sof) to the Stratix V device during logic develop-ment and debugging.

�

�

El Camino GmbH 27

El Camino GmbH 28

Stratix V Prototyping Board

El CaminoTraining - Engineering - Consultancy

El Camino GmbHLandshuter Str. 1D-84048 MainburgGermanyTelefone +49-8751-8787-0Telefax +49-8751-8787-10E-mail: [email protected]://www.elcamino.de

El Camino GmbH Training - Engineering - Consultancy, DIGILAB 10K10, DIGILAB picoMAX,DIGILAB SX IV, DIGIALB SX V and other names of El Camino products, product features and ser-vices are trademarks and/or service marks of El Camino GmbH in Germany and other countries.ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIXand other names of Altera products, product features and services are trademarks and/or service marksof Altera Corporation in the United States and other countries. Other product and company names men-tioned in this document may be the trademarks of their respective owners.No warranties: This documentation is "as is" without any express or implied warranty of any kind inclu-ding warranties of merchantability, no infringement of intellectual property or of fitness for any particu-lar purpose. In no event shall El Camino or its suppliers be liable for any damages whatsoever(including, without limitation, damages for loss of profits, business interruption or loss of information)arising out of the use of or inability to use this documentation, even if El Camino has been advised ofthe possibility of such damages. Because some jurisdictions prohibit the exclusion or limitations of lia-bility for consequential or incidental damages, some of the above limitations may not apply to you.El Camino further does not warrant the accuracy or completeness of the information, text, graphics orother items contained in this document. El Camino may make changes to these materials, or to the pro-ducts described therein, at any time without notice. El Camino makes no commitment to update this do-cument.

Copyright© 2014 El Camino GmbH. All rights reserved

Notes:

A B C D E F G H I J

1

2

3

4

5

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7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

DIGILAB SX V V1.0

DIGILAB SX VPreliminary

STRATIXV_V1_0

9-15-2014_17:54 1

Prel H Stand Proto

1

1

1111

PEKT0805RED

11

1111

1

PEKT0805 RED

PEKT0805RED

1

1

1

NC7NZ34

NC7NZ34

NC7NZ34

1

1

1

1

NC7NZ34

NC7NZ34

NC7NZ34

1

1 1

1

10

23456789

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

DQGND

VDD

DS18S20TO-92_123

1

PEKT0805

PEKT0805

SIGNAL=NC;3,4,5,6,11,12,13,14

SO16WB

DCLK

GNDNCSVCC2

DATA2

EPCQ512SI16N

DATA3

DATA1

DATA0

1

1

1

MMC_FLASH

FPS-009-230-0-0YAMAICHI FPS-009-230-0-0CLK

CMD

DAT2

GND1

GND2

RSV_NC

VDD

8

9

MH

1M

H2

CASE1CASE2

WRITE_PROT_FRONTCARD_DETECT

WR_PR_CARD_DET

CASE

5SEEBH40C2N

RREF_BLRREF_BR

RREF_TLRREF_TR

IO_VREFB8AN0_RZQ_5_DIFFIO_RX_T203N

DNU_8DNU_7DNU_6DNU_5DNU_4DNU_3DNU_2DNU_1

DNU

MSEL2

IO_VREFB4AN0_RZQ_1_DIFFIO_RX_B210P

IO_VREFB3BN0_NPERSTR0_DIFFIO_TX_B29PIO_VREFB3BN0_NPERSTR1_DIFFIO_TX_B29NIO_VREFB3BN0_NPERSTL1_DIFFIO_TX_B27PIO_VREFB3BN0_NPERSTL0_DIFFIO_TX_B27N

IO_VREFB3BN0_PR_ERROR_DIFFIO_TX_B23NIO_VREFB3BN0_PR_READY_DIFFIO_TX_B21PIO_VREFB3BN0_PR_REQUEST_DIFFIO_TX_B21NIO_VREFB3BN0_PR_DONE_DIFFIO_RX_B20P

IO_VREFB3BN0_DATA31_DIFFIO_RX_B20NIO_VREFB3BN0_DATA30_DIFFIO_TX_B19PIO_VREFB3BN0_DATA29_DIFFIO_TX_B19NIO_VREFB3AN0_DATA28_DIFFIO_RX_B18PIO_VREFB3AN0_DATA27_DIFFIO_RX_B18NIO_VREFB3AN0_DATA26_DIFFIO_TX_B17PIO_VREFB3AN0_DATA25_DIFFIO_TX_B17NIO_VREFB3AN0_DATA24_DIFFIO_RX_B16PIO_VREFB3AN0_DATA23_DIFFIO_RX_B16NIO_VREFB3AN0_DATA22_DIFFIO_TX_B15PIO_VREFB3AN0_DATA21_DIFFIO_TX_B15NIO_VREFB3AN0_DATA20_DIFFIO_RX_B14PIO_VREFB3AN0_DATA19_DIFFIO_RX_B14NIO_VREFB3AN0_DATA18_DIFFIO_TX_B13PIO_VREFB3AN0_DATA17_DIFFIO_TX_B13NIO_VREFB3AN0_DATA16_DIFFIO_RX_B12PIO_VREFB3AN0_DATA15_DIFFIO_RX_B12NIO_VREFB3AN0_DATA14_DIFFIO_TX_B11PIO_VREFB3AN0_DATA13_DIFFIO_TX_B11NIO_VREFB3AN0_DATA12_DIFFIO_RX_B10PIO_VREFB3AN0_DATA11_DIFFIO_RX_B10NIO_VREFB3AN0_DATA10_DIFFIO_TX_B9PIO_VREFB3AN0_DATA9_DIFFIO_TX_B9NIO_VREFB3AN0_DATA8_DIFFIO_RX_B8PIO_VREFB3AN0_DATA7_DIFFIO_RX_B8NIO_VREFB3AN0_DATA6_DIFFIO_TX_B7PIO_VREFB3AN0_DATA5_DIFFIO_TX_B7NIO_VREFB3AN0_DATA4_DIFFIO_RX_B6PIO_VREFB3AN0_DATA3_DIFFIO_RX_B6NIO_VREFB3AN0_DATA2_DIFFIO_TX_B5PIO_VREFB3AN0_DATA1_DIFFIO_TX_B5N

AS_DATA0_ASDOAS_DATA1AS_DATA2AS_DATA3

TDOTDITCKTMSTRST

NSTATUSCONF_DONENCONFIG

NCE

IO_VREFB3AN0_INIT_DONE_DIFFIO_TX_B3P

IO_VREFB3AN0_DATA0_DIFFIO_RX_B4P

IO_VREFB3AN0_NCEO_DIFFIO_RX_B4N

IO_VREFB3AN0_CRC_ERROR_DIFFIO_TX_B1PIO_VREFB3AN0_DEV_CLRN_DIFFIO_TX_B3NIO_VREFB3AN0_DEV_OE_DIFFIO_RX_B2P

NCSODCLKIO_VREFB3AN0_CLKUSR_DIFFIO_TX_B1N

MSEL4

MSEL0

MSEL3

MSEL1

VCCBAT

TEMPDIODEP

IO_VREFB3BN0_CVP_CONFDONE_DIFFIO_TX_B23P

TEMPDIODEN

IO_VREFB7AN0_RZQ_4_DIFFIO_RX_T1P

IO_VREFB3AN0_RZQ_0_DIFFIO_RX_B2N

NIO_PULLUP

CONFIG

1

1

1

1

1

1

1

1

Preliminary

lt Internet auf 3/3V3 spezifiziert

led?

Pullups ON

MMC

Pullup an FPGA

Taster

TasterRESET

BOOT

JTAG_Altera

Temp. Sensor

DIGILAB SX V

Serial MEM Config

EnableConfig complete

Clear Reg

Not used -> tie to GND



PCIE HIP Fund. Reset

If NU direct GND

Reference Input OCT Impedance 240R/100R to

VCCPGM

AS

Not used -> as defined in Quartus

NC

GND

LA_A0_0LA_A1_7

LA_A3_7

LA_A3_6LA_A0_4

LA_A2_1

R260 1K8

0402

R259 1K8

0402

R257 1K8

0402R258 1K8

0402

R285 R0402100R

1%GNDGND

GNDGND

R279 R0402100R

1%

+3V0GND

+3V0

+3V0

R121K01%

R61K01%

AW36AW4

B39B1

B34

Y20J19R7AW5AV5AL19AA30AV35AW35

AD8

AK6

AF28AE29AB28AC28

AU29AN29AN30AT30

AU30AP30AR30AH30AJ30AE31AF31AG31AH31AJ32AK32AK33AL33AH33AJ33AV32

AW32AV31

AW31AV34

AW34AP31AR31AT32AU32AM31AN31AU33AU34AR33AT33

AB31Y31

AC32AG32

AH34AJ34AA31AT35AM35

AM5AH6

AK35

AC8

AL34

AP33

AN32

AN33AM34AP34

AD32AC31AN34

AH7

AA9

AG8

AA10

AK9

R6

AT29

P5

J6

AR34

AK5

U30

ASDO

ASDO

MMC9MMC_RSVMMC_CMD

MMC_CLK

MMC_DAT

MMC_DAT2

SER_TEMP_DATA_PCB

TMSTCK

TDITDO

INIT_DONENCONFIGCONF_DONENSTATUS

+3V0

MMC_CDET

5

2

7

3

6

1

4

8

9

1011

1617

121314

15U61

GND

DCLK

NCENC

RESETCRC_ERROR

1%10KR46

R1250R1%

GND+3V0

C87100NF

ASD2

ASD3

ASD1

NC

ASD1

GND

16

1072

9

1

8

15

U8

MMC_WP1

D1

GREEN

D3

GREEN

+3V0

R22610K1%

321

U2

NCONFIG

NSTATUS

SW10

SW9

NCGND

+3V0

GND

GND

NCONFIG

+3V0

RESET

TDI

TMS

TCKTDO

29-15-2014_8:31

STRATIXV_V1_0

J14

DEVICE=DIP2X5_SMD

PKG_TYPE=DIP2X5_SMDASSEMBLED=SAMTEC_HTST-105-01-L-DV

R54K71%

R44K71%

JTAG PROGRAMMER/BONDARY SCAN

IMP=NACONNECTION=FLAT CABLE

GND

NCNC NC

+3V0

R123 4K7

PKG_TYPE=0402

DEVICE=R0402+3V0

GND

GNDGND

GND

GND

+3V0

6 2

U45

3 5

U45

1 7

U45

C9100NF

+3V0

R14 1K0INIT_DONE

CONF_DONE R16 1K0

R43 1K0

6 2

U46

3 5

U46

1 7

U46

R45 1K0

R44 1K0

C10100NF

CRC_ERROR

D2

GND

D6GND

1%4K7

R132 GND

+3V0

+3V0

GND

+3V0

GND

NC

+3V0GND

GND

GND

GND

R22710K1%

R22810K1%

R22910K1%

R23010K1%

R23110K1%

R23210K1%

D5

GND

GNDGND

R1510K1%

R1310K1%

R910K1% 1%

10KR8

GND

DCLKNCSO

ASD2ASD3

GND

NCNCNCNCNCNCNCNC

NCSO

GND

GND

NCNCNC

+3V0

+3V0

+3V0

GND+3V0

R280 R0402100R

1%

R281 R0402100R

1%

LA_A1_2

LA_A0_3LA_A0_1LA_A0_2

LA_A0_5

LA_A1_5LA_A1_4

LA_A2_4LA_A2_5

LA_A2_6LA_A2_7

LA_A3_0

LA_A3_1LA_A3_2

LA_A3_3

LA_A3_4LA_A3_5

LA_A0_6LA_A0_7

LA_A1_6

LA_A1_0LA_A1_1

LA_A1_3

LA_A2_0

LA_A2_2LA_A2_3

GND

GNDGND

NC

1

1

1

1

1

MK_2X4_90

1234 5

678

ROHS=OK

1

1

1

1

MK_2X4_90

1234 5

678

ROHS=OK

1

1

1

1

MK_2X4_90

1234 5

678

ROHS=OK

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

3

4

5

6

7

8SIP-8P

1

2

3

4

5

6

7

8SIP-8P

1

2

3

4

5

6

7

8SIP-8P

1

2

3

4

5

6

7

8SIP-8P

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

A B C D E F G H I J

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2

3

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Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1

1

2

3

4

5

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8SIP-8P

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1 23 4

PUSHB180F_309-5861

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

MK_2X4_90

1234 5

678

ROHS=OK

ETD108ETETD108ETDISTRELEC 210370

12345678 AN1

AN2


12345678 AN1

AN2


12345678 AN1

AN2


12345678 AN1

AN2


12345678 AN1

AN2

Preliminary

Taster

FPGA Pullup/Pulldown Select


FPGA Pullup/Pulldown SelectFPGA Pullup/Pulldown Select


2 FPGA Input

2 FPGA Input

2 FPGA Input

2 FPGA Input


LEDs next pageDip Switch

DIGILAB SX V

SW_SEL14SW_SEL13

SW_SEL15SW_SEL16

SW8

SW7

SW6

SW5

SW4

SW3

SW2

SW1

SW5_PUSW6_PUSW7_PUSW8_PU

SW1_PUSW2_PU

SW4_PUSW3_PU

SW32_PSW31_P

SW29_PSW30_P

SW28_P

SW26_PSW27_P

SW25_P

SW16_PSW15_PSW14_PSW13_PSW12_PSW11_P

SW9_PSW10_P

SW23_PSW24_P

SW22_P

SW20_PSW21_P

SW19_PSW18_PSW17_P

SW7_PSW8_P

SW6_PSW5_PSW4_PSW3_PSW2_PSW1_P

SW8_P_PUSW7_P_PUSW6_P_PUSW5_P_PUSW4_P_PUSW3_P_PUSW2_P_PUSW1_P_PU

SW24_P_PUSW23_P_PUSW22_P_PU

SW20_P_PUSW21_P_PU




12345678 10

9

U41

10

12345678

9

U14

10

12345678

9

U15

10

12345678

9

U40

10

12345678

9

U42

+3V0

+3V0

+3V0

+3V0

+3V0

SW_SEL3

SW_SEL1

GND

J34

MULTICOMP MCDP04 F_947-1600

+3V0

R206 10K

R163 10K

R164 10K

R165 10K

R166 10K

R167 10K

R168 10K

R169 10K

R170 10K

R187 10K

R188 10K

R189 10K

R190 10K

R191 10K

R192 10K

R193 10K

R194 10K

R72 1K0

R179 10K

R180 10K

R181 10K

R182 10K

R183 10K

R184 10K

R185 10K

R186 10K

R171 10K

R172 10K

R173 10K

R174 10K

R178 10K

SW8

SW7

SW6

SW5

SW4

SW3

SW2

SW1

J7

R47 1K0

37-17-2014_20:47

STRATIXV_V1_0

R48 1K0

R50 1K0

R49 1K0

R56 1K0

R55 1K0

R54 1K0

R53 1K0

R64 1K0

R63 1K0

R62 1K0

R61 1K0

R60 1K0

R59 1K0

R58 1K0

R57 1K0

R126 1K0

R124 1K0

R120 1K0

R119 1K0

R118 1K0

R117 1K0

R116 1K0

R81 1K0

R71 1K0

R70 1K0

R69 1K0

R68 1K0

R67 1K0

R66 1K0

R65 1K0

J8

J9

J10

J11

R177 10K

R176 10K

R175 10K

R202 10K

R201 10K

R200 10K

R199 10K

R198 10K

R197 10K

R196 10K

R195 10K

R205 10K

R204 10K

J2


R203 10K

SW_SEL4

SW_SEL2

GND

+3V0

+3V0+3V0

R210 10K

R209 10K

R208 10K

J32


R207 10K+3V0

SW_SEL8

SW_SEL6SW_SEL5

SW_SEL7

GND

+3V0

+3V0+3V0

R214 10K

R213 10K

R212 10K

J33


R211 10K+3V0

SW_SEL12

SW_SEL10SW_SEL9

SW_SEL11

GND

+3V0

+3V0+3V0

R218 10K

R217 10K

R216 10K

R215 10K+3V0+3V0

+3V0+3V0

GND

GND

GND

GND

GND

1

10111213141516171819

2

20212223242526272829

3

303132333435363738

39

4

40414243

444546

56789

MICTOR_767004-38

1

10111213141516171819

2

20212223242526272829

3

303132333435363738

39

4

40414243

444546

56789

MICTOR_767004-38

12

12

1

1011 1213 1415 16

23 45 67 89

1

1011 1213 1415 16

23 45 67 89

1

1011 1213 1415 16

23 45 67 89

1

1011 1213 1415 16

23 45 67 89

NC7NZ34

NC7NZ34

NC7NZ34

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

11 1111 11

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

111 111 11

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

1 11 111 11

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

11

1 111

11

NC7NZ34

NC7NZ34

NC7NZ34

3-23-2001_13:17

A1_ELCAFORM

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

PEKT0805RED

NC7NZ34

Preliminary

LEDsGen. IO / LA Interface

High Speed Gen. IO / LA Interface

DIGILAB SX V

6 2

U53

LA_CLK0_J5

LA_CLK1_J5

LA_Q1_CLK_J4LA_CLK3_J4

LA_CLK1_J5LA_CLK0_J5

SW1_P

LED8

GND

GND

6 2

U59

3 5

U59

1 7

U59

3 5

U57

6 2

U57

1 7

U57

3 5

U58

6 2

U58

1 7

U58

6 2

U56

3 5

U56

1 7

U56

3 5

U54

6 2

U54

1 7

U54

3 5

U55

6 2

U55

1 7

U55

3 5

U53

1 7

U53

3 5

U51

6 2

U51

1 7

U51

6 2

U50

3 5

U50

1 7

U50

3 5

U48

6 2

U48

1 7

U48

SW18_P

SW17_P

SW9_P

SW10_P

GND

GND

GND

4

1 7

U52

6 2

U52

3 5

U52

R731K01%

R741K01%

R751K01%

R761K01%

R771K01%

R781K01%

R791K01%

R801K01%

LED1

LED2

LED3

LED4

LED5

LED6

LED7

R191K01%

R201K01%

R221K01%

R171K01%

R181K01%

R231K01%

R241K01%

R211K01%

LED11

LED13

LED14

LED15

LED16

LED9

LED10

LED12

R271K01%

R281K01%

R291K01%

R301K01%

R311K01%

R321K01%

R331K01%

R341K01%LED17

LED18

LED19

LED20

LED21

LED22

LED23

LED24

R351K01%

R361K01%

R371K01%

R381K01%

R391K01%

R401K01%

R411K01%

R421K01%

LED25

LED26

LED27

LED28

LED29

LED30

LED31

LED32

1 7

U49

6 2

U49

3 5

U49

SW24_P

SW23_P

SW22_P

SW21_P

SW20_P

SW19_P

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

SW12_PSW4_P

SW3_P

SW2_P

SW16_P

SW15_P

SW14_P

SW13_P

SW11_P

SW28_P

SW25_P

SW26_P

SW27_P

SW29_P

SW30_P

SW31_P

SW32_P

SW6_P

SW5_P

SW7_P

SW8_P

GND

J25

J27

J26

J24

LA_A0_0

LA_A0_2LA_A0_3LA_A0_4LA_A0_5

LA_A0_7

LA_A0_1

LA_A0_6

LA_A1_0

LA_A1_2LA_A1_3LA_A1_4LA_A1_5LA_A1_6LA_A1_7

LA_A1_1

LA_A2_0


LA_A2_1

LA_A3_0


LA_A3_1

GNDGNDGNDGNDGNDGNDGNDGND




J3S

IP-2P

NA

J29S

IP-2P

NA

GND

GND

45 44

43 42 41 40 39

20212223242526272829303132333435363738

19181716151413121110

987654321

46

J5

LA_A0_6

LA_A3_1


LA_A3_0

LA_A2_1


LA_A2_0

LA_A1_1


LA_A1_0

LA_A0_1

LA_A0_7

LA_A0_5LA_A0_4LA_A0_3LA_A0_2

LA_A0_0

NC

45 44

43 42 41 40 39

20212223242526272829303132333435363738

19181716151413121110

987654321

46

J4

GND

NC

LA_C0_4

LA_C0_6

LA_C1_1

LA_C1_7LA_C1_6LA_C1_5LA_C1_4LA_C1_3LA_C1_2

LA_C1_0

LA_C0_1

LA_C0_7

LA_C0_5

LA_C0_3LA_C0_2

LA_C0_0

LA_C3_1


LA_C3_0

LA_C2_1


LA_C2_0

GNDGND

GNDGND GND

GNDGND

NCNC

NCNC

1

1 1

1 1 1

1

ADJ

OUT3OUT2OUT1

GND2

IN3IN2IN1

LP38500SDLLP8

GND1

1

111

11

1

1

1

1

1

1

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

RJ45_LED

1

2

3

4

5

6

7

8

A1

A2

C1

C2

K1

K2

ZB1

ZB2

1

10

23 45 67 89DIP2X5

RJ45_LED

1

2

3

4

5

6

7

8

A1

A2

C1

C2

K1

K2

ZB1

ZB2

NC7NZ34

NC7NZ34

1

10111213141516171819

2

20

3456789

DIP2X10

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

SOT23CM1218

K2

K1

A

1 1 1 1 1

PEKT0805 RED

PEKT0805 RED

PEKT0805 RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

1 1

1 1 1

1

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

PEKT0805RED

1 1 1

1 1 11 1 1

1 1 1

1

NC7NZ34

NC7NZ34NC7NZ34

NC7NZ34

NC7NZ34

PEKT0805RED

PEKT0805RED

PEKT0805RED

1

GN

DVC

C

INVALIDR1OUTB

R3INR2INR1IN

T5OUTT4OUTT3OUTT2OUTT1OUT

V-V+

FORCEOFF_NFORCEON

R3OUTR2OUTR1OUT

T5INT4INT3INT2INT1IN

C2-C2+

C1-C1+

MAX3238SSOP28

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

GN

DVC

C

INVALIDR1OUTB

R3INR2INR1IN

T5OUTT4OUTT3OUTT2OUTT1OUT

V-V+

FORCEOFF_NFORCEON

R3OUTR2OUTR1OUT

T5INT4INT3INT2INT1IN

C2-C2+

C1-C1+

MAX3238SSOP28

1

1

1

1

1

1

1

1

1

1

1

1

1

NC7NZ34

NC7NZ34

NC7NZ34

Preliminary

JTAG_ICE SPI

RS232_0

RS232_1

DIGILAB SX V

Power RS232

+5V

+3V3

+3V0

1 7

U26

3 5

U26

6 2

U26

+3V3USART_DSR_1

C90

50V

220NF

10%C91

50V

220NF

10%

C88

50V

220NF

10%

C89

50V

220NF

10%

C95

50V

220NF

10%C92

50V

220NF

10%

C94

50V

220NF

10%

C93

50V

220NF

10%

RTS_0RXD_0TXD_0

CTS_0

USART_CTS_1USART_RXD_1

USART_DSR_0USART_RXD_0USART_CTS_0

R244330R1%

R941K01%

R1061K01%

USART_DSR_0USART_RXD_0USART_CTS_0

USART_CTS_1

USART_DSR_1USART_RXD_1

+3V3

+3V3

RTS_1

C97220NF

C96220NF

2 26

1516

1198

1210765

427

1413

182021

1719222324

31

2528

U3



59-15-2014_8:31

STRATIXV_V1_0

2 26

1516

1198

1210765

427

1413

182021

1719222324

31

2528

U4

R105560K1%

D40

D47

D46

3 5

U23

6 2

U19

6 2

U20

6 2

U22

6 2

U21

R951K01%

R841K01%

R831K01%

R821K01%

R871K01%

R861K01%

R851K01%

R931K01%

R921K01%

R911K01%

R901K01%

R891K01%

R881K01%

D39

D38

D37

D35

D36

D34

D45

D44

D43

D42

D41

D51

R1041K01%R102

1K01%

R1011K01%

R1001K01%

R1081K01%

R1071K01%

D54

D53

D52

D50

D49

D48

R9610K1%

R9710K1%

R9810K1%

R9910K1%

R10310K1%

2

1

3

U18

2

1

3

U34

2

1

3

U10

J1

1 7

U19

3 5

U19RS232CONNECTION=CABLE

RS232CONNECTION=CABLE

J17

ASSEMBLED=F_473-9528 / B_73F6730

J28

J18

ASSEMBLED=F_473-9528 / B_73F6730

3 5

U20

1 7

U20

3 5

U21

1 7

U21

3 5

U22

1 7

U22

1 7

U23

6 2

U23

6 2

U24

3 5

U24

1 7

U24

6 2

U25

3 5

U25

1 7

U25

2

1

3

U33

2

1

3

U35

2

1

3

U36

2

1

3

U37

2

1

3

U38

2

1

3

U39

GND

GND

ICE_DBGACK

SPI_PCS_N_3

SPI_SS_PCS0_N

USART_SCK_1

SPI_PCS_N_1

SPI_PCS_N_2

USART_SCK_0

ICE_TCKICE_TMSICE_TDI

+3V0

SPI_SS_PCS0_N

GNDGND

GND

+3V0

SPI_SCK

NCGND

SPI_MISO

USART_CTS_1

USART_RXD_1

USART_DSR_1

USART_RTS_1

USART_TXD_1

USART_DTR_1

USART_CTS_0

USART_RXD_0

USART_DSR_0

+3V0

USART_RTS_0

USART_TXD_0

USART_DTR_0

USART_RTS_1USART_TXD_1USART_DTR_1

USART_RTS_0USART_TXD_0USART_DTR_0

GND

DTR_0

NC

GND

GND

CTS_1RTS_1RXD_1

DSR_1

GNDDSR_0

+3V0 +3V0

+3V0GNDGND

GNDGNDGND

GNDGNDGNDGNDGNDGND

NCGND

GND

GNDNCDTR_0

DTR_0

GND NCGND

GND

GNDNCDTR_1

DTR_1

TXD_1

GND

USART0_EN

NC

NCNC

CTS_0

DSR_0RXD_0

RTS_0TXD_0

GND

DTR_1

NC

GNDGND

USART1_EN

NC

NCNC

CTS_1

DSR_1RXD_1

TXD_1

+3V0

+3V0

+3V0

+3V0

GND

+3V0

SPI_MOSI

NCGND

NCGND

GND

SPI_SCKICE_TRST_N

GND

ICE_RTCKICE_TDOICE_SRST_NICE_DBGRQ

GND

GND

GND

SPI_PCS_N_1SPI_PCS_N_3SPI_MOSI

GND

GND

SPI_MISOSPI_PCS_N_2

R238 33R

0402R239 33R

0402R240 33R

0402

R241 33R

0402R242 33R

0402R243 33R

0402

GND

R245330R1%

R246330R1%

R249330R1%

R248330R1%

R247330R1%

GND

R253 0R_NB

0402

8

567

9

432

1

U66

R04021%4K7R252

R04021%10KR251

C188100NF

C060350V

C18510UF

C080516V

C18410UF

C080516V

C187100NF

C060350V

R04021%10KR250

+3V3

+3V3

GND

GND GND

GNDGND

+3V3

+3V3

NC

NC

1

1

1

1

1

PEKT0805 RED

1

1

1

A

GND VCC

Y

OE

NC7SZ126SOT23_5

A

GND VCC

Y

OE

NC7SZ126SOT23_5

1

PEKT0805 RED

PEKT0805 RED

1

1

1

0V

11

D+D-VCC

USB_B_90ASSEMBLED=F_370-4191

GND

S1S2

GND2IO2BIO1B

VCC2

GND1IO2IO1VCC1

USB6B1SO8

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1

VCC

DN

VMVP

SUSPNDSPEEDOE_N

VMOVPO

GND

MODEDP

NC

RCV

USB1T11AMTCTSSOP14

1

GN

D

OU

T

TAB

VIN

MIC

5209

_5_0

SO

T223

1 1

1

Preliminary

3V0 ok

USB Con

DIGILAB SX V

Power USB

R140 1K0

0402

R25 1K0

0402

R52

330R

1%

VUSB

2 3

4

1U

1

ASSEMBLED=MIC5209-3.3_BS

VUSB GND

R138 1K0

0402

14

10

54

692

1312

7

111

8

3

U6 USBCONNECTION=CABLE

VUSB

GND

R134 1K5

0603

69-18-2014_8:43

STRATIXV_V1_0

5678

4321

U7

4321

56

J31

C101

10%1NF

C0402

C100

10%100NF

C0603

R135 24R

0402

C99100NF

R139 1K0

0402

D56

D55

C98100NF

2

3 5

4

1U17

2

3 5

4

1U16

R137 1K5

0603

R136 24R

0402

C168

DEVICE=C1206

TOLERANCE=10%VALUE=10UF

UMAX=10V

D57

C11

10%1NF

C0402

R1271K01%

C12100NF

+3V0

VUSB

GND

+3V0

GND

VBUS

GND

VBUS

USB_RXDMUSB_RXDPUSB_TXD

USB_EOP

USB_TXOE_N

USB_ON_N

USB_P_PULLUP

USB_N_PULLUP

USB_N_PULLUP

USB_P_PULLUP GND

USB_DN_CONUSB_DNUSB_DP USB_DP_CON

GND

USB_P_PULLUP_BUF

NC

GND

+3V0GND

GNDGND

GND

USB_N_PULLUP_BUF

GND

USB_RXD

GNDGND

VUSB

GND

GND

GND

R224 470K

0603

R225 470K

0603

GND

VUSB

VUSB

VUSB

VUSB

VUSB

VUSB

GND

VUSB_FPGA

1

1

1

1

1

1

11

1

1

1

1

KOAX_LP

KOAX_LP

KOAX_LP

1

1

1

LT1719SO8

OUT+IN-IN

VEEGND VCC

+VS

SHDN

1

1

1

1

1

1

1

1

1

1

1

11

1

1 1

1

ROHS=OK200MA1000R

FB0603_1000

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1

1

1

1

1

ROHS=OK200MA1000R

FB0603_1000

LT1719SO8

OUT+IN-IN

VEEGND VCC

+VS

SHDN

LT1719SO8

OUT+IN-IN

VEEGND VCC

+VS

SHDN

1

1

1

1

1

1

50PPM

QOSZ_4PKG_TYPE=SXO-0507

GND

OUT

VDD

EN

1

1

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

NC7NZ34

1

50PPMGND

OUT

VDD

EN

50PPM

QOSZ_4PKG_TYPE=SXO-0507

GND

OUT

VDD

EN

Preliminary

SMA CLK_IN

DIGILAB SX V

2

3

4

1

U71

25MHZ

2

3

4

1

U43

80MHZ

R219 33R

GND

20MHZ

6 2

U73

1 7

U73

3 5

U73

6 2

U27

3 5

U27

1 7

U27

6 2

U28

3 5

U28

1 7

U28

6 2

U29

3 5

U29

1 7

U29

+3V0

C116100NF

C117100NF

NC

PCLKB_FPGA1_LA

PCLKA_FPGA1_LA

PCLKC_FPGA1

PCLKB_FPGA1

PCLKA_FPGA1

25MHZ_B

25MHZ_A

+2V5_B8

80MHZ

PCLKC_J15

2

3

4

1

U5

80MHZ

PCLKB_J15

PCLKA_J16

PCLKA_J15

+3V0_CLK

GND

PCLKC_J16

R268 33R

0402PCLKB_J16

R267 33R

0402

R142 33R

0402

R143 33R

0402

R145 33R

0402

R114 33R

GND

PCLK_B

+3V0_CLK

723

45 1

8

6

U12

723

45 1

8

6

U13

USER INTERFACEIMP=50R

CONNECTION=SMAFB5

C19100NF

C111100NF

R141 33R

0402

R144 33R

0402

R146 33R

0402

79-23-2014_11:52

STRATIXV_V1_0

FB2

C107

10%1NF

C0402

C104

10%1NF

C0402

C103

10%1NF

C0402

C105

10%1NF

C0402

C108

10%1NF

C0402

C110

10%1NF

C0402

C115100NF

C231NF

C109

10%1NF

C0402

C106

10%1NF

C0402

C102

10%1NF

C0402

R1311K01%

R1303K31%

R1291K01%

R1283K31%

R1121K01%

R1133K31%

723

45 1

8

6

U11

R11149R9

1%

R11049R9

1%

R10949R9

1%

1

234

5

J21

1

234

5

J20

1

234

5

J19

CP2

10V10UF

PKG_TYPE=TANT-A

DEVICE=TANTA

C118100NF

+3V0_CLK

GND

GND

GND

+3V0

+3V0+3V0_CLK

+3V0

PCLK_C

PCLK_A

GND

GND

GNDGND

GND

GND

GND GND

GND

+3V0

GND

GND

GND GND

GNDGND

GND

NC

GND

GND

GND

+3V0

GND

GND

GND

+3V0

+3V0_CLK

+3V0_CLK

+3V0_CLK

C31NF

+3V0

R269 33R

0402

+3V0

R115 33R

C216100NF

C2081NF

GND

NC

R265 33R

R273 33R

0402

R272 33R

0402

R266 33R

0402

C16100NF

+3V0

GND

GND

DEVICE=TANTA

PKG_TYPE=TANT-A10UF

10V

CP3

R121 NB

1

1

1

1

1

1

1

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1

5SEEBH40C2N

IO_VREFB3BN0_CLK0N_DIFFIO_RX_B22NIO_VREFB3BN0_CLK0P_DIFFIO_RX_B22P




IO_VREFB3BN0_FPLL_BL_CLKOUT0_FPLL_BL_CLKOUTP_FPLL_BL_FB0_DIFFIO_TX_B25PIO_VREFB3BN0_FPLL_BL_CLKOUT1_FPLL_BL_CLKOUTN_DIFFIO_TX_B25N

IO_VREFB3BN0_FPLL_BL_CLKOUT2_FPLL_BL_FBP_FPLL_BL_FB1_DIFFIO_RX_B26PIO_VREFB3BN0_FPLL_BL_CLKOUT3_FPLL_BL_FBN_DIFFIO_RX_B26N

IO_VREFB3DN0_CLK4N_DIFFIO_RX_B76NIO_VREFB3DN0_CLK4P_DIFFIO_RX_B76P


IO_VREFB4AN0_CLK10N_DIFFIO_RX_B202NIO_VREFB4AN0_CLK10P_DIFFIO_RX_B202P



IO_VREFB4AN0_CLK9N_DIFFIO_RX_B206NIO_VREFB4AN0_CLK9P_DIFFIO_RX_B206P IO_VREFB4AN0_FPLL_BR_CLKOUT0_FPLL_BR_CLKOUTP_FPLL_BR_FB0_DIFFIO_TX_B203P

IO_VREFB4AN0_FPLL_BR_CLKOUT1_FPLL_BR_CLKOUTN_DIFFIO_TX_B203N

IO_VREFB4AN0_FPLL_BR_CLKOUT2_FPLL_BR_FBP_FPLL_BR_FB1_DIFFIO_RX_B204PIO_VREFB4AN0_FPLL_BR_CLKOUT3_FPLL_BR_FBN_DIFFIO_RX_B204N



IO_VREFB4DN0_FPLL_BC_CLKOUT0_FPLL_BC_CLKOUTP_FPLL_BC_FB0_DIFFIO_TX_B139PIO_VREFB4DN0_FPLL_BC_CLKOUT1_FPLL_BC_CLKOUTN_DIFFIO_TX_B139N

IO_VREFB4DN0_FPLL_BC_CLKOUT2_FPLL_BC_FBP_FPLL_BC_FB1_DIFFIO_RX_B140PIO_VREFB4DN0_FPLL_BC_CLKOUT3_FPLL_BC_FBN_DIFFIO_RX_B140N

IO_VREFB7AN0_CLK12N_DIFFIO_RX_T3NIO_VREFB7AN0_CLK12P_DIFFIO_RX_T3P




IO_VREFB7AN0_FPLL_TR_CLKOUT0_FPLL_TR_CLKOUTP_FPLL_TR_FB0_DIFFIO_TX_T8PIO_VREFB7AN0_FPLL_TR_CLKOUT1_FPLL_TR_CLKOUTN_DIFFIO_TX_T8N

IO_VREFB7AN0_FPLL_TR_CLKOUT2_FPLL_TR_FBP_FPLL_TR_FB1_DIFFIO_RX_T7PIO_VREFB7AN0_FPLL_TR_CLKOUT3_FPLL_TR_FBN_DIFFIO_RX_T7N

IO_VREFB7DN0_CLK18N_DIFFIO_RX_T69NIO_VREFB7DN0_CLK18P_DIFFIO_RX_T69P


IO_VREFB7DN0_FPLL_TC_CLKOUT0_FPLL_TC_CLKOUTP_FPLL_TC_FB0_DIFFIO_TX_T72PIO_VREFB7DN0_FPLL_TC_CLKOUT1_FPLL_TC_CLKOUTN_DIFFIO_TX_T72N

IO_VREFB7DN0_FPLL_TC_CLKOUT2_FPLL_TC_FBP_FPLL_TC_FB1_DIFFIO_RX_T71PIO_VREFB7DN0_FPLL_TC_CLKOUT3_FPLL_TC_FBN_DIFFIO_RX_T71N




IO_VREFB8AN0_CLK23P_DIFFIO_RX_T193P

IO_VREFB8AN0_FPLL_TL_CLKOUT0_FPLL_TL_CLKOUTP_FPLL_TL_FB0_DIFFIO_TX_T198PIO_VREFB8AN0_FPLL_TL_CLKOUT1_FPLL_TL_CLKOUTN_DIFFIO_TX_T198N

IO_VREFB8AN0_FPLL_TL_CLKOUT2_FPLL_TL_FBP_FPLL_TL_FB1_DIFFIO_RX_T197PIO_VREFB8AN0_FPLL_TL_CLKOUT3_FPLL_TL_FBN_DIFFIO_RX_T197N



IO_VREFB8AN0_CLK23N_DIFFIO_RX_T193N

PLL_BL

PLL_BC

PLL_BR

CLK PLL

PLL_TL

PLL_TC

PLL_TR

1

1

1

1 pCon2

pCon2

B8 2,5V!!!....

B8 2,5V!!!....

LA J4

LA J5LA J5

LA J4

pCon1pCon1

pCon1

Preliminary

DIGILAB SX V

pCon1

B8 2,5V!!!....

B8 2,5V!!!....

B8 2,5V!!!....

B8 2,5V!!!....

MEZ_CLK2_OUT_P

NCNC

MEZ_CLK2_OUT_N

R152 33R

0402R271 33R

0402

CLKOUT_J16_9_RCLKOUT_J16_19_R

R153 33R

0402

R270 33R

0402CLKOUT_J16_89_R

CLKIN_J15_118

CLKIN_J16_118

PCLKC_FPGA1

PCLKB_FPGA1_LA

PCLKB_FPGA1

PCLKA_FPGA1_LA

25MHZ_A

25MHZ_B

80MHZ

20MHZ

PCLKA_FPGA1

LA_CLK0_J5LA_CLK1_J5

LA_CLK3_J4LA_Q1_CLK_J4

MEZ_CLK_IN_NMEZ_CLK_IN_P

NC

PER1CON_58_CLKIN

PER2CON_58_CLKIN

PCLKIN_J15

PCLKIN_J16

CLKOUT_J15_19_R

J23

M23

D34E34

C33D33

N34P34

L34L33

M32N32

K16L16

J17J16

N16P16

T16U15

C7D7

A7B7

A5A6

A4A3

K6L6

G6G7

AE16

AG17

AK17

AH16

AM7

AN7

AP7

AT6

AT8

AW7

AL23

AJ22

AH28

AG30

AW28

AW29

R32P32

L23

J24

AB30

AD30AV28

AV29

AF29

AG28

AH22

AK23

AV7

AR8

AN6

AL7

AF17

AE17

AJ17

AL17

AR7

AU6

AC30

AE30

U30

CLKOUT_J15_19CLKOUT_J15_9

CLKOUT_J15_29

R156 33R

0402

MEZ_CLK2_IN_P

89-17-2014_22:09

STRATIXV_V1_0

MEZ_CLK2_IN_N

R155 33R

0402CLKOUT_J15_9_R

R147 33R

0402CLKOUT_J15_29_R

R148 33R

0402CLKOUT_J15_89CLKOUT_J15_89_R

R158 33R

0402

R133 33R

0402

R157 33R

0402

R159 33R

0402LA_CLK3_J4_R

LA_Q1_CLK_J4_R

LA_CLK0_J5_RLA_CLK1_J5_R

NC

80MHZ

CLKOUT_J16_29_R CLKOUT_J16_29CLKOUT_J16_89


GND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

NCNC

NCNC

NCNC

1

1

1

1111

11

11

11

11

GND2VDD2

IO15IO14IO13IO12IO11IO10

IO9IO8IO7IO6IO5IO4IO3IO2IO1IO0

LBUBOEWECE

A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

VDD1GND1

IS61LV51216TSOP44

1

SST39LF800TSOPI48

A0A1

A10A11A12A13A14A15A16A17A18A19

A2

A20

A3A4A5A6A7A8A9

CE_N

DQ0DQ1

DQ10DQ11DQ12DQ13DQ14DQ15

DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

RESET_NNC4NC5NC6NC7

OE_N

VDDVSS1VSS2

WE_N

MH2MH1

A0A1

A10A11A12A13A14A15A16A17A18A19

A2

A20

A3A4A5A6A7A8A9

CE_N

DQ0DQ1

DQ10DQ11DQ12DQ13DQ14DQ15

DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

RESET_NNC4NC5NC6

OE_N

VDDVSS1VSS2

WE_N

NC7

SST39LF800_MHTSOPI48_SOCKEL

GND2VDD2

IO15IO14IO13IO12IO11IO10

IO9IO8IO7IO6IO5IO4IO3IO2IO1IO0

LBUBOEWECE

A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

VDD1GND1

IS61LV51216TSOP44

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

Adressen FPGA intern ev anders Mapen

10ns AS7C38098A-10TIN Mouser 913-AS7C38098A-10TIN10ns IS61WV51216BLL-10TLI Mouser_870-61WV51216B10TLI

AS6C8016-55ZIN Mouser_913-AS6C8016-55ZIN

IS62WV51216BLL87062WV51216BLL55TLI

2,7-3,6V ok

DIGILAB SX V

Preliminary97-29-2014_13:03

STRATIXV_V1_0

1211

38373635323130291615141310987

39404117

6

2844434227262524232221201918

54321

3334

U32

5049

2524

654321

481716

9

23

10

2221201918

87

26

2931

343639414345

3335384042443032

12131415

28

374627

11

47

U60

2524

654321

4817

232221201918

87

26

2931

343639414345

3335384042443032

1213141547

28

374627

11

169

10

U44

1%10KR220

1211

38373635323130291615141310987

39404117

6

2844434227262524232221201918

54321

3334

U31

C2410NF

C119100NF

C2510NF

C120100NF

C2610NF

C121100NF

C2710NF

C122100NF

C2810NF

C123100NF

C2910NF

C124100NF

1%10KR221

1%10KR222

1%10KR223

FLASH_CE2_N

NC

FLASH_RESET_N

A20

A18

SRAM_LB1SRAM_UB1

GND

+3V0

GND+3V0

DQ_0DQ_1DQ_2DQ_3DQ_4DQ_5DQ_6DQ_7DQ_8DQ_9DQ_10DQ_11DQ_12DQ_13DQ_14DQ_15


GNDGND

NCNCNCNC

NCNCNC

A0A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18


A10A11A12A13A14A15A16A17A18



+3V0

+3V0

GND

GND

+3V0

+3V0

GND

GND

SRAM_WESRAM_OE

SRAM_WESRAM_OESRAM_UB2SRAM_LB2

GND

+3V0

GND

+3V0

GND

+3V0

GND

+3V0

GND

+3V0

GND

+3V0

A17A16A15A14A13A12A11A10


A0

A18A17A16A15A14A13A12A11A10

A9A8A7A6A5A4A3A2A1

FLASH_WE_NFLASH_OE_N

FLASH_WE_NFLASH_OE_N

A19A20

A19

FLASH_RESET_N

NCNC

+3V0

FLASH_CE1_N

+3V0

SRAM_CE1

+3V0

SRAM_CE2

+3V0

1

1

1011 1213 1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

60

61 6263 64

7 89

QSH

-030

-01-

X-D

-A

SAM

TEC

QSH

-030

-01-

X-D

-AH

P1 HP2

1

10

100101 102103 104105 106107 108109

11

110111 112113 114115 116117 118119

12

120

121 122123 124125 126127 128

129

13

130

1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

6061 6263 6465 6667 6869

7

7071 7273 7475 7677 7879

8

8081 8283 8485 8687 8889

9

9091 9293 9495 9697 9899

QSH

-060

-01-

X-D

-AQ

SH-0

60-0

1-X-

D-A

1

10

100101 102103 104105 106107 108109

11

110111 112113 114115 116117 118119

12

120

121 122123 124125 126127 128

129

13

130

1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

6061 6263 6465 6667 6869

7

7071 7273 7475 7677 7879

8

8081 8283 8485 8687 8889

9

9091 9293 9495 9697 9899

QSH

-060

-01-

X-D

-AQ

SH-0

60-0

1-X-

D-A

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

SAM_ASP_122953_01

D7712V_18

D75D73

12V_17D71D69

12V_16D67D65

12V_15D63D61

12V_14D59D57

12V_13D55D53

12V_12D51D49

12V_11D47D45

12V_10D43D41

12V_9D39D37

12V_8D35D33

12V_7D31D29

12V_6D27D25

12V_5D23D21

12V_4D19D17

12V_3D15D13

12V_2D11

D912V_1

D7D5

12VD3

CLKIN0JTAG_TDI

JTAG_TMSSCL

XCVR_RXN0XCVR_RXP0XCVR_RXN1XCVR_RXP1XCVR_RXN2XCVR_RXP2XCVR_RXN3XCVR_RXP3XCVR_RXN4XCVR_RXP4XCVR_RXN5XCVR_RXP5XCVR_RXN6XCVR_RXP6XCVR_RXN7XCVR_RXP7

D78D763V3_18D74D723V3_17D70D683V3_16D66D643V3_15D62D603V3_14D58D563V3_13D54D523V3_12D50D483V3_11D46D443V3_10D42

3V3_9D38D363V3_8D34D323V3_7D30D283V3_6D26D243V3_5D22D203V3_4D18D163V3_3D14D123V3_2D10D83V3_1D6D43V3D2

CLKOUT0JTAG_TDOJTAG_TCK

XCVR_TXN0XCVR_TXP0XCVR_TXN1XCVR_TXP1XCVR_TXN2XCVR_TXP2XCVR_TXN3XCVR_TXP3XCVR_TXN4XCVR_TXP4XCVR_TXN5XCVR_TXP5XCVR_TXN6XCVR_TXP6XCVR_TXN7XCVR_TXP7

SDA

D1D0

D40

D793V3_19 PSNT_N

GND_M1 GND_M7GND_M2 GND_M8GND_M3 GND_M9GND_M4 GND_M10GND_M5 GND_M11GND_M6 GND_M12

MH1 MH2

Signals 2 FPGA

neu

neu

neu

neu

neu

>>> ???

neu

PreliminaryDIGILAB SX V

>>> ??? >>> ???für FPGA auf CLK IN

>>> ???für FPGA RX?

Signals from FPGA

new

old

MEZ_XCVR_P21

F1

5AFUSE_SMD_OMNIBLOCK

MEZ_XCVR_P19MEZ_XCVR_P17

156154152150148146144142140138136134132130128126124122120118116114112110108106104102

10098969492908886848280787674727068666462605856545250484644

40383634

3230282624222018161412108642

157155153151149147145143141139137135133131129127125123121119117115113111109107105103

9997959391898785838179777573716967656361595755535149474543

393735

3129272523211917151311

97531

33

4241

101

158159 160

161 162163 164165 166167 168169 170171 172

173 174

J35

MEZ_XCVR_P1

MEZ_D0

PER2CON_118

PER1CON_116PER2CON_116

CLKIN_J16_118

CLKIN_J16_118CLKIN_J15_118

PER1CON_101

PER1CON_111

PER2CON_101

PER2CON_111

PER2CON_97

PER1CON_110

+3V0PER2CON_16

PER2CON_58_CLKINPER1CON_58_CLKIN

109-13-2014_5:55

STRATIXV_V1_0

MH14

MTHOLE250

MTHOLE250

1

10

100101 102103 104105 106107 108109

11

110111 112113 114115 116117 118119

12

120

121 122123 124125 126127 128

129

13

130

1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

6061 6263 6465 6667 6869

7

7071 7273 7475 7677 7879

8

8081 8283 8485 8687 8889

9

9091 9293 9495 9697 9899

J16

1

10

100101 102103 104105 106107 108109

11

110111 112113 114115 116117 118119

12

120

121 122123 124125 126127 128

129

13

130

1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

6061 6263 6465 6667 6869

7

7071 7273 7475 7677 7879

8

8081 8283 8485 8687 8889

9

9091 9293 9495 9697 9899

J15

1011 1213 1415 1617 1819

2

2021 2223 2425 2627 2829

3

3031 3233 3435 3637 3839

4

4041 4243 4445 4647 4849

5

5051 5253 5455 5657 5859

6

60

61 6263 64

65 66

7 89

1

J13

1%10KR254

PCLKIN_J15

PCLKC_J15

PCLKA_J15

PCLKB_J15

CLKOUT_J16_9

CLKOUT_J16_19

CLKOUT_J16_29

PCLKA_J16

PCLKB_J16

PCLKC_J16

PCLKIN_J16


CLKOUT_J15_29

CLKOUT_J15_19

CLKOUT_J15_9








PER2CON_95




GNDPER2CON_5PER2CON_3

+5V

+5V

+3V0

+3V0

+3V0

+3V0

PER2CON_64+5V

PER2CON_56PER2CON_54PER2CON_52PER2CON_50

+3V0

PER2CON_46PER2CON_44PER2CON_42PER2CON_40PER2CON_38



+12V

PER1CON_23

PER1CON_55







PER1CON_57

+5V

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND

+5V+5V

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND

+5V

+3V0

+3V0

PER1CON_76+3V0

+5V

+3V0

+3V0

+3V0

+3V0

+5V

GND

+5V+5V

GND+3V0+3V0

GND+3V0+3V0

+3V0+3V0GND

+3V0+3V0GND

+5V+5V +5V

+5V

GND+3V0+3V0

GND+3V0+3V0

+3V0+3V0GND

+3V0+3V0GND

+5V+5V

NC

USART_RXD_1 USART_RXD_0USART_TXD_1 USART_TXD_0USART_SCK_1 USART_SCK_0

USART_CTS_1 USART_CTS_0USART_RTS_1 USART_RTS_0USART_DTR_1 USART_DTR_0

USART_DSR_1 USART_DSR_0SPI_MOSI SPI_MISO

SPI_SCK SPI_SS_PCS0_NSPI_PCS_N_3 SPI_PCS_N_2SPI_PCS_N_1 USB_RXD

USB_RXDM USB_RXDPUSB_TXD USB_TXOE_NUSB_EOP USB_ON_N

GNDGNDGND

GND GNDGNDGND

GND GNDGNDGND

NC











GND GNDGNDGND

GND GNDGNDGND

NC

PER1CON_3PER1CON_5


PER1CON_25

PER1CON_37


PER1CON_35

+3V0

+12V_MB

PER2CON_98






PER2CON_110PER2CON_112PER2CON_114

+3V0

+5V+5V

+3V0

+5V

+5V

GND

GND

GND

+5V

GND

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND

+5V+5V

GND

GND

GND

GND

GNDGND

GND

GND

+3V0

CLKOUT_J15_111

CLKOUT_J15_101 CLKOUT_J16_101

CLKOUT_J16_111

PER2CON_101

PER2CON_111

PER1CON_101

PER1CON_111

CLKIN_J15_118

PER1CON_118

NCNC

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

+3V0MEZ_CLK2_IN_N

MEZ_TX8_D40_P

MEZ_D1

NCNCNCNC

MEZ_D2+3V0

MEZ_TX0_D4_PMEZ_TX0_D6_N

+3V0MEZ_TX1_D8_PMEZ_TX1_D10_N







+3V0MEZ_CLK_OUT_PMEZ_CLK_OUT_N

+3V0

MEZ_TX8_D42_N+3V0









+3V0MEZ_CLK2_OUT_PMEZ_CLK2_OUT_N

NCNCNCNC

MEZ_D3+12V_MB

MEZ_RX0_D5_PMEZ_RX0_D7_N

+12V_MBMEZ_RX1_D9_PMEZ_RX1_D11_N







+12V_MBMEZ_CLK_IN_PMEZ_CLK_IN_N

+12V_MB










+12V_MBMEZ_CLK2_IN_P

MEZZANINE_PRESENT

MEZ_XCVR_P3MEZ_XCVR_P5MEZ_XCVR_P7MEZ_XCVR_P9MEZ_XCVR_P11MEZ_XCVR_P13MEZ_XCVR_P15

MEZ_XCVR_P23MEZ_XCVR_P25MEZ_XCVR_P27MEZ_XCVR_P29MEZ_XCVR_P31

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

5SEEBH40C2N

IO_VREFB8AN0_DIFFIO_RX_T205NIO_VREFB8AN0_DIFFIO_RX_T205P



IO_VREFB8AN0_DIFFIO_TX_T194N








IO_VREFB8BN0_DIFFIO_RX_T169P

IO_VREFB8BN0_DIFFIO_RX_T171NIO_VREFB8BN0_DIFFIO_RX_T171P











IO_VREFB8BN0_DIFFIO_TX_T172N











IO_VREFB8CN0_DIFFIO_RX_T145NIO_VREFB8CN0_DIFFIO_RX_T145P



IO_VREFB8CN0_DIFFIO_RX_T151N








IO_VREFB8CN0_DIFFIO_TX_T146N



IO_VREFB8CN0_DIFFIO_TX_T152NIO_VREFB8CN0_DIFFIO_TX_T152PIO_VREFB8CN0_DIFFIO_TX_T154NIO_VREFB8CN0_DIFFIO_TX_T154PIO_VREFB8CN0_DIFFIO_TX_T156NIO_VREFB8CN0_DIFFIO_TX_T156PIO_VREFB8CN0_DIFFIO_TX_T158NIO_VREFB8CN0_DIFFIO_TX_T158PIO_VREFB8CN0_DIFFIO_TX_T160NIO_VREFB8CN0_DIFFIO_TX_T160PIO_VREFB8CN0_DIFFIO_TX_T162NIO_VREFB8CN0_DIFFIO_TX_T162P

IO_VREFB8CN0_DIFFIO_TX_T166NIO_VREFB8CN0_DIFFIO_TX_T166PIO_VREFB8CN0_DIFFIO_TX_T168N

IO_VREFB8DN0_DIFFIO_RX_T121N

IO_VREFB8DN0_DIFFIO_TX_T122NIO_VREFB8DN0_DIFFIO_TX_T122P



IO_VREFB8DN0_DIFFIO_TX_T134P



IO_VREFB8AN0_DIFFIO_RX_T203P

IO_VREFB8BN0_DIFFIO_RX_T169N






IO_VREFB8DN0_DIFFIO_TX_T126PIO_VREFB8DN0_DIFFIO_TX_T126NIO_VREFB8DN0_DIFFIO_TX_T128PIO_VREFB8DN0_DIFFIO_TX_T128N

IO_VREFB8DN0_DIFFIO_TX_T132PIO_VREFB8DN0_DIFFIO_TX_T132N

IO_VREFB8DN0_DIFFIO_TX_T134N








IO_VREFB8CN0_DIFFIO_TX_T168P


IO_VREFB8CN0_DIFFIO_TX_T164PIO_VREFB8CN0_DIFFIO_TX_T164N

IO_VREFB8AN0_DIFFIO_TX_T210P








IO_VREFB8BN0_DIFFIO_TX_T192P















IO_VREFB8CN0_DIFFIO_RX_T151P









IO_VREFB8DN0_DIFFIO_RX_T143P











B8

May be switched to B8


MEZ_CLK_OUT_NMEZ_CLK_OUT_P

NC

NC

NC

MEZ_XCVR_P19

MEZ_XCVR_P23MEZ_RX3_D17_P

MEZ_XCVR_P27

MEZ_XCVR_P31

MEZ_XCVR_P15


MEZ_XCVR_P9

MEZ_XCVR_P7

MEZ_XCVR_P3

LA_C0_7LA_C1_0LA_C1_1

MEZ_D1MEZ_D3

MEZ_D2MEZ_D0

LA_C0_6

LA_C1_3MEZ_RX15_D69_PMEZ_RX15_D71_N

MEZ_TX16_D74_NMEZ_TX16_D72_P

MEZ_RX7_D35_NMEZ_RX7_D33_P


LA_C2_0

LA_C3_7

MEZ_TX4_D22_N

MEZ_TX1_D10_N




MEZ_TX1_D8_PMEZ_TX8_D42_NMEZ_TX8_D40_P









MEZ_RX0_D7_N

MEZ_RX3_D19_N




MEZ_TX6_D30_N

A23B23

A22B22

D22C22

E23F23

G22H22

G23H23

R24T24

M24N24

N23P23K24L24A20B20

D21E21

C21C20F21

G21 G20H20

E20F20

N21N20

N22P22

L21M21

J22K22

L20M20

J21K21

C27C26

A26B26

D27E27

F27G27

H26J26

F26G26 L27

M27J27K27

P28N27

T28U28

R27T27

U27U26

A25B25

C25D25

C24D24

E25E24

G25H25

F24G24

J25K25

L26M26

N26P26

R26R25

T25U25

N25P25

G31H31

E31E30

F30G30

C31D31

C30D30

A31B31

J31K31

J30K30

L30L31

N31P31

R31R30

M30N30

A29B29

A28B28

C28D28

G29H29

G28H28

E28F29

K28L28

J28J29

M29N28

T30U30

P29R29

U29V29

J34K34

G34H34

J33K33

E33F33 G32

G33F32E32

A37A36

C34

A35A34

A32B32

M33N33

T31U31

U30


119-15-2014_17:54

STRATIXV_V1_0

LA_C0_0

LA_C0_2LA_C0_3

LA_C0_5

LA_C0_1

LA_C1_4LA_C1_5LA_C1_6LA_C1_7

LA_C0_4

LA_C2_2LA_C2_3LA_C2_4LA_C2_5LA_C2_6

LA_C2_7

LA_C2_1

LA_C3_0

LA_C3_2

LA_C3_3LA_C3_4LA_C3_5LA_C3_6

LA_C3_1

MEZ_TX4_D20_P

MEZ_TX6_D28_P






MEZ_RX0_D5_P





LA_C1_2


MEZ_XCVR_P29

MEZ_XCVR_P25


NCNCNC

NCNCNCNC

NCNCNCNC

NCNCNCNC

NCNCNCNC

NC

NC

NC

NCNC

NC

NC

NCNC

NC

NCNC

NC

NC

NC

NCNC

NC

NC

IO_VREFB3DN0_DIFFIO_RX_B90N

IO_VREFB3DN0_DIFFIO_TX_B89N





















IO_VREFB3CN0_DIFFIO_RX_B66N

IO_VREFB3CN0_DIFFIO_TX_B65N






















IO_VREFB3BN0_DIFFIO_RX_B42N

IO_VREFB3BN0_DIFFIO_TX_B41N











IO_VREFB3DN0_DIFFIO_TX_B67P

IO_VREFB3DN0_DIFFIO_RX_B68P





















IO_VREFB3BN0_DIFFIO_TX_B31P

IO_VREFB3BN0_DIFFIO_RX_B32P











IO_VREFB3CN0_DIFFIO_TX_B43P

IO_VREFB3CN0_DIFFIO_RX_B44P









IO_VREFB3CN0_DIFFIO_TX_B53NIO_VREFB3CN0_DIFFIO_TX_B53P














5SEEBH40C2N

B3

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH





















IO_VREFB4CN0_DIFFIO_RX_B174PIO_VREFB4CN0_DIFFIO_RX_B174NIO_VREFB4CN0_DIFFIO_TX_B173PIO_VREFB4CN0_DIFFIO_TX_B173NIO_VREFB4CN0_DIFFIO_RX_B172PIO_VREFB4CN0_DIFFIO_RX_B172NIO_VREFB4CN0_DIFFIO_TX_B171PIO_VREFB4CN0_DIFFIO_TX_B171NIO_VREFB4CN0_DIFFIO_RX_B170PIO_VREFB4CN0_DIFFIO_RX_B170NIO_VREFB4CN0_DIFFIO_TX_B169PIO_VREFB4CN0_DIFFIO_TX_B169NIO_VREFB4CN0_DIFFIO_RX_B168PIO_VREFB4CN0_DIFFIO_RX_B168NIO_VREFB4CN0_DIFFIO_TX_B167PIO_VREFB4CN0_DIFFIO_TX_B167NIO_VREFB4CN0_DIFFIO_RX_B166PIO_VREFB4CN0_DIFFIO_RX_B166NIO_VREFB4CN0_DIFFIO_TX_B165PIO_VREFB4CN0_DIFFIO_TX_B165NIO_VREFB4CN0_DIFFIO_RX_B164PIO_VREFB4CN0_DIFFIO_RX_B164NIO_VREFB4CN0_DIFFIO_TX_B163PIO_VREFB4CN0_DIFFIO_TX_B163NIO_VREFB4CN0_DIFFIO_RX_B162PIO_VREFB4CN0_DIFFIO_RX_B162NIO_VREFB4CN0_DIFFIO_TX_B161PIO_VREFB4CN0_DIFFIO_TX_B161NIO_VREFB4CN0_DIFFIO_RX_B160PIO_VREFB4CN0_DIFFIO_RX_B160NIO_VREFB4CN0_DIFFIO_TX_B159PIO_VREFB4CN0_DIFFIO_TX_B159NIO_VREFB4CN0_DIFFIO_RX_B158N
































IO_VREFB4AN0_DIFFIO_TX_B209N













IO_VREFB4AN0_DIFFIO_TX_B199P





IO_VREFB4AN0_DIFFIO_RX_B210N













































5SEEBH40C2N

B4


VUSB_FPGA

NC

NC

NCNCNCNC

NC

NC

SRAM_CE2

PWM_FAN

MMC_DAT

DQ_7

MMC_CMDMMC_DAT2

MMC_RSV

DQ_10

MEZZANINE_PRESENT

SW6_PSW13_P

SW13_P_PU

DQ_5

DQ_2

AV17AW17

AV16AW16

AU17AU16

AR17AT17

AN16AP16

AM17AN17

AF16AG16

AL16AM16

AV19AW19

AT18AU18

AP19AR19

AP18AR18

AN19AN18

AL18AM19

AD18AD17

AE18AE19

AF19AG18

AH18AJ18

AJ19AK18

AG19AH19

AV13AW13AV14AW14AT14AU14AN13AP13AN12AP12AL13AM13AF13AG13AH13AJ13AE14AF14AA12AA13AC14AD14AB13AC13AT15AU15AR14AR15AN15AP15AM14AN14

AK14AL14

AK15AL15

AG15AG14

AH15AJ15

AD15AE15

AA14AA15

AC15AD16

AB16AB15

AU9AU10

AR9AT9

AV10AW10

AN9AP9

AN10AP10

AL10AM10

AH10AJ10

AG9AH9

AF10AG10

AD9AE9

AB10AC10

AB9AC9

AV11AW11

AT11AU11

AT12AU12

AM11AN11

AR11AR12

AK11AL11

AL12AK12

AG12AF11

AH12AJ12

AE10AE11

AD12AE12

AB12AC12

AL6

AJ6AJ7

AN8AM8

AP6AR6

AU7AU8

AV8AW8

U30

DQ_11DQ_14

SW2_P_PU

SW1_P_PU

SPI_MOSISPI_MISO

USB_EOP

USB_RXDM

SW8_PSW8_P_PUSW7_P_PU

SW3_P_PUSW4_P_PUSW4_PSW3_PSW7_P

DQ_23

DQ_21DQ_22

DQ_15

SRAM_UB2SRAM_LB2

DQ_9

SW2_P

USART_SCK_1

SRAM_LB1

USB_ON_N

USB_TXOE_N

SPI_SS_PCS0_N

SER_TEMP_DATA_PCB

SRAM_CE1SRAM_UB1

A19

DQ_8

A20

A8

SRAM_WE

FLASH_WE_N

FLASH_RESET_NA7

A6A5

A4A1

A17

A16A15

SRAM_OE

DQ_31DQ_30

DQ_29

DQ_28

DQ_24

DQ_27

DQ_26DQ_25

A18A14

A10

129-18-2014_8:43

STRATIXV_V1_0

AL20AL21

AJ20AJ21

AK21AL22

AE20AE21

AH21AG21

AD20AD21

AN21AP21

AN20AM20

AR20AR21

AT20AU20

AT21AU21

AV20AW20

AF22AG22

AD22AE22

AF23AG23

AD23AE23

AM23AN23

AM22AN22

AP22AR22

AT23AU23

AV22AW22

AV23AW23

AL25AL24

AJ24AK24

AH24AG24

AD24AE24

AE25AF25

AB24AC24

AN24AP24

AM25AN25

AP25AR25

AR24AT24

AU24AU25

AV25AW25

AG25AH25

AF26AG26

AJ26AK26

AC25AC26

AB25AA25

AD26AE26

AN26AN27

AL26AM26

AP27AR27

AT26AU26

AV26AW26

AT27AU27

AJ27AK27

AG27AH27

AD27AE27

AB27AC27

AA28AA29

AA26AA27

AM28AN28

AL27AL28

AP28AR28

AK29AJ29

AL29AM29

AK30AL30

U30

A9USART0_EN

SW27_P

SPI_PCS_N_3

DQ_12

A0

SPI_SCK

FLASH_CE2_N

USB_TXD

SPI_PCS_N_2FLASH_CE1_N

A3

DQ_13

DQ_17DQ_18

DQ_4

DQ_6

FLASH_OE_NUSART1_EN

USB_P_PULLUPUSB_N_PULLUP

USART_RTS_0

SPI_PCS_N_1USART_TXD_0

SW_SEL16

SW_SEL14SW_SEL13

SW_SEL15

SW_SEL12

SW_SEL10SW_SEL9

SW_SEL11

SW_SEL3

SW_SEL1

SW_SEL4

SW_SEL2

SW_SEL8

SW_SEL6SW_SEL5

SW_SEL7

USART_DTR_0

USART_DSR_0USART_RXD_0

USART_CTS_0

USART_RXD_1

USART_DTR_1USART_TXD_1

USART_CTS_1

USART_DSR_1USART_RTS_1

USART_SCK_0

ICE_DBGACK

ICE_TDO

ICE_TCK

ICE_TDIICE_TMS

ICE_TRST_N

ICE_RTCK

ICE_SRST_NICE_DBGRQ

SW19_P_PU

SW23_P_PUSW29_P

SW24_PSW20_P

SW30_P_PU

SW19_PSW21_PSW22_P

SW31_P_PU

SW31_P

SW32_P_PUSW15_P_PUSW30_P

SW5_PU

SW7_PUSW6_PU

SW8_PU

SW3_PUSW4_PU

SW8SW7SW6SW5SW4SW3SW2SW1

SW28_P

SW16_P

SW17_P

SW26_P

SW25_PSW18_PSW18_P_PU

SW23_P

SW32_P

SW29_P_PU


SW25_P_PU

SW24_P_PU

SW22_P_PU

SW21_P_PUSW20_P_PU

SW17_P_PU

SW16_P_PU

SW1_PUSW2_PU

USB_RXDUSB_RXDP

A11

A12A13

DQ_20DQ_19DQ_16

A2

SW10_PSW9_PSW9_P_PU

SW11_P_PUSW12_P

SW1_P

DQ_1DQ_0

DQ_3

SW14_PSW12_P_PU

SW5_P_PUSW10_P_PU

SW6_P_PUSW11_P

SW14_P_PUSW15_P

SW5_P

MMC_WP1

MMC_CLKMMC9

MMC_CDET

NCNCNC

NC

NC

NCNC

NCNCNC

NC

NCNCNCNCNCNCNC

NC

NC

NC

NCNC

NCNCNCNC

NCNCNC

NCNC

NCNCNC

NCNC

NC

NC

NC

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

5SEEBH40C2N

IO_VREFB7DN0_DIFFIO_TX_T84NIO_VREFB7DN0_DIFFIO_TX_T84PIO_VREFB7DN0_DIFFIO_RX_T83NIO_VREFB7DN0_DIFFIO_RX_T83PIO_VREFB7DN0_DIFFIO_TX_T82NIO_VREFB7DN0_DIFFIO_TX_T82PIO_VREFB7DN0_DIFFIO_RX_T81NIO_VREFB7DN0_DIFFIO_RX_T81PIO_VREFB7DN0_DIFFIO_TX_T80NIO_VREFB7DN0_DIFFIO_TX_T80PIO_VREFB7DN0_DIFFIO_RX_T79NIO_VREFB7DN0_DIFFIO_RX_T79PIO_VREFB7DN0_DIFFIO_TX_T78NIO_VREFB7DN0_DIFFIO_TX_T78PIO_VREFB7DN0_DIFFIO_RX_T77NIO_VREFB7DN0_DIFFIO_RX_T77PIO_VREFB7DN0_DIFFIO_TX_T76NIO_VREFB7DN0_DIFFIO_TX_T76PIO_VREFB7DN0_DIFFIO_RX_T75NIO_VREFB7DN0_DIFFIO_RX_T75PIO_VREFB7DN0_DIFFIO_TX_T74NIO_VREFB7DN0_DIFFIO_TX_T74PIO_VREFB7DN0_DIFFIO_RX_T73NIO_VREFB7DN0_DIFFIO_RX_T73PIO_VREFB7DN0_DIFFIO_TX_T70NIO_VREFB7DN0_DIFFIO_TX_T70PIO_VREFB7DN0_DIFFIO_TX_T68NIO_VREFB7DN0_DIFFIO_TX_T68PIO_VREFB7DN0_DIFFIO_TX_T66NIO_VREFB7DN0_DIFFIO_TX_T66PIO_VREFB7DN0_DIFFIO_RX_T65NIO_VREFB7DN0_DIFFIO_RX_T65PIO_VREFB7DN0_DIFFIO_TX_T64NIO_VREFB7DN0_DIFFIO_TX_T64PIO_VREFB7DN0_DIFFIO_RX_T63NIO_VREFB7DN0_DIFFIO_RX_T63PIO_VREFB7DN0_DIFFIO_TX_T62NIO_VREFB7DN0_DIFFIO_TX_T62PIO_VREFB7DN0_DIFFIO_RX_T61NIO_VREFB7DN0_DIFFIO_RX_T61P

















IO_VREFB7CN0_DIFFIO_RX_T43NIO_VREFB7CN0_DIFFIO_RX_T43PIO_VREFB7CN0_DIFFIO_TX_T42NIO_VREFB7CN0_DIFFIO_TX_T42PIO_VREFB7CN0_DIFFIO_RX_T41NIO_VREFB7CN0_DIFFIO_RX_T41PIO_VREFB7CN0_DIFFIO_TX_T40NIO_VREFB7CN0_DIFFIO_TX_T40PIO_VREFB7CN0_DIFFIO_RX_T39NIO_VREFB7CN0_DIFFIO_RX_T39PIO_VREFB7CN0_DIFFIO_TX_T38NIO_VREFB7CN0_DIFFIO_TX_T38PIO_VREFB7CN0_DIFFIO_RX_T37NIO_VREFB7CN0_DIFFIO_RX_T37P

IO_VREFB7BN0_DIFFIO_TX_T36NIO_VREFB7BN0_DIFFIO_TX_T36PIO_VREFB7BN0_DIFFIO_RX_T35NIO_VREFB7BN0_DIFFIO_RX_T35PIO_VREFB7BN0_DIFFIO_TX_T34NIO_VREFB7BN0_DIFFIO_TX_T34PIO_VREFB7BN0_DIFFIO_RX_T33NIO_VREFB7BN0_DIFFIO_RX_T33PIO_VREFB7BN0_DIFFIO_TX_T32NIO_VREFB7BN0_DIFFIO_TX_T32PIO_VREFB7BN0_DIFFIO_RX_T31NIO_VREFB7BN0_DIFFIO_RX_T31PIO_VREFB7BN0_DIFFIO_TX_T30NIO_VREFB7BN0_DIFFIO_TX_T30PIO_VREFB7BN0_DIFFIO_RX_T29NIO_VREFB7BN0_DIFFIO_RX_T29PIO_VREFB7BN0_DIFFIO_TX_T28NIO_VREFB7BN0_DIFFIO_TX_T28PIO_VREFB7BN0_DIFFIO_RX_T27NIO_VREFB7BN0_DIFFIO_RX_T27PIO_VREFB7BN0_DIFFIO_TX_T26NIO_VREFB7BN0_DIFFIO_TX_T26PIO_VREFB7BN0_DIFFIO_RX_T25NIO_VREFB7BN0_DIFFIO_RX_T25PIO_VREFB7BN0_DIFFIO_TX_T24NIO_VREFB7BN0_DIFFIO_TX_T24PIO_VREFB7BN0_DIFFIO_RX_T23NIO_VREFB7BN0_DIFFIO_RX_T23PIO_VREFB7BN0_DIFFIO_TX_T22NIO_VREFB7BN0_DIFFIO_TX_T22PIO_VREFB7BN0_DIFFIO_RX_T21NIO_VREFB7BN0_DIFFIO_RX_T21PIO_VREFB7BN0_DIFFIO_TX_T20NIO_VREFB7BN0_DIFFIO_TX_T20PIO_VREFB7BN0_DIFFIO_RX_T19NIO_VREFB7BN0_DIFFIO_RX_T19PIO_VREFB7BN0_DIFFIO_TX_T18NIO_VREFB7BN0_DIFFIO_TX_T18PIO_VREFB7BN0_DIFFIO_RX_T17NIO_VREFB7BN0_DIFFIO_RX_T17PIO_VREFB7BN0_DIFFIO_TX_T16NIO_VREFB7BN0_DIFFIO_TX_T16PIO_VREFB7BN0_DIFFIO_RX_T15NIO_VREFB7BN0_DIFFIO_RX_T15PIO_VREFB7BN0_DIFFIO_TX_T14NIO_VREFB7BN0_DIFFIO_TX_T14PIO_VREFB7BN0_DIFFIO_RX_T13NIO_VREFB7BN0_DIFFIO_RX_T13P

IO_VREFB7AN0_DIFFIO_TX_T12NIO_VREFB7AN0_DIFFIO_TX_T10N

IO_VREFB7AN0_DIFFIO_TX_T6NIO_VREFB7AN0_DIFFIO_TX_T6PIO_VREFB7AN0_DIFFIO_TX_T4NIO_VREFB7AN0_DIFFIO_TX_T4PIO_VREFB7AN0_DIFFIO_TX_T2NIO_VREFB7AN0_DIFFIO_TX_T2P

IO_VREFB7AN0_DIFFIO_RX_T1N





















B7


PER2CON_72

PER2CON_116

PER2CON_114


PER2CON_82

PER2CON_107

PER2CON_111


PER2CON_106



PER2CON_95

PER2CON_85


PER2CON_94

PER2CON_92


PER2CON_70



PER2CON_84

PER2CON_80






PER2CON_44



PER2CON_54

PER2CON_52



PER2CON_5

PER2CON_15PER2CON_25PER2CON_23PER2CON_24PER2CON_22PER2CON_20


PER2CON_8

PER2CON_6PER2CON_4

PER2CON_3

PER2CON_32

PER1CON_92

PER2CON_30

PER2CON_28

PER1CON_3PER1CON_4

PER1CON_115



PER1CON_76


PER1CON_56

L19K19J18K18L18M18N19N18P17R16M17N17G19H19F18G18E19E18C19D19C18D18A19B19M15N15R15T15G17H17G16H16E17F17C16D16A16B16A17B17

K15L15

J15J14

M14N14

P14R14

U14T13

U12U13

G14H14

F15G15

E14F14

D15E15

A14B14

C15C14

P13R12

T12U11

N12N13

K13L13

J12K12L12

M12H13J13E12F12G13G12C13D13C12D12A13B13

U9U10P11R11R10T10L11

M11N10P10J11K10A11B11A10B10C10D10E11F11H10J10

G11H11

P8R8R9T9N9N8L9

M9J9K9L8

M8D9E9C9C8B8A8F9

G10G8G9E8F8

E7F6

D6E6N7P7N6M6K7J7

H7

U30


PER1CON_35PER1CON_47PER1CON_23PER1CON_78PER1CON_80PER1CON_82


PER1CON_54


PER1CON_44

PER1CON_94PER1CON_98PER1CON_100PER1CON_102PER1CON_104PER1CON_106PER1CON_110PER1CON_112PER1CON_114PER1CON_116

139-15-2014_8:29

STRATIXV_V1_0


PER1CON_45


PER1CON_34

PER1CON_28


PER1CON_68



PER1CON_70

PER1CON_72



PER1CON_8PER1CON_6

PER1CON_10


NCNC

NC

1

0603

1111

0603

1111

0603

1111

0603

111 1 1

1 1

0603

111 1 1

0603

111 1

0603

111 1

11

0603

1 1

0603

1111

11

0603

1 1

0603

1111

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1111

1111

1111111

0603

1

0603

1111

111111

0603

1

0603

1111

FB1206

2500MA500R1 1 1111111

0603

1 1

0603

1111 1 1 111

0603

11

0603

1

1 1 1 1 1

1

5SEEBH40C2N

VCCIO3AVCCIO3A_1

VCCIO3BVCCIO3B_1

VCCIO3CVCCIO3C_1

VCCIO3DVCCIO3D_1

VCCIO4A

VCCIO4BVCCIO4B_1

VCCIO4CVCCIO4C_1

VCCIO4DVCCIO4D_1

VCCIO7A

VCCIO7BVCCIO7B_1

VCCIO7CVCCIO7C_1

VCCIO7DVCCIO7D_1

VCCIO8A

VCCIO8A_1

VCCIO8BVCCIO8B_1

VCCIO8CVCCIO8C_1

VCCIO8DVCCIO8D_1

VCCPD3ABVCCPD3AB_1

VCCPD3CDVCCPD3CD_1

VCCPD4VCCPD4_1VCCPD4_2



VREFB3AN0VREFB3BN0VREFB3CN0VREFB3DN0




VCCIO

5SEEBH40C2N

GN

D_2

73G

ND

_272

GN

D_2

71G

ND

_270

GN

D_2

69G

ND

_268

GN

D_2

67G

ND

_266

GN

D_2

65G

ND

_264

GN

D_2

63G

ND

_262

GN

D_2

61G

ND

_260

GN

D_2

59G

ND

_258

GN

D_2

57G

ND

_256

GN

D_2

55G

ND

_254

GN

D_2

53G

ND

_252

GN

D_2

51G

ND

_250

GN

D_2

49G

ND

_248

GN

D_2

47G

ND

_246

GN

D_2

45G

ND

_244

GN

D_2

43G

ND

_242

GN

D_2

41G

ND

_240

GN

D_2

39G

ND

_238

GN

D_2

37G

ND

_236

GN

D_2

35G

ND

_234

GN

D_2

33G

ND

_232

GN

D_2

31G

ND

_230

GN

D_2

29G

ND

_228

GN

D_2

27G

ND

_226

GN

D_2

25G

ND

_224

GN

D_2

23G

ND

_222

GN

D_2

21G

ND

_220

GN

D_2

19G

ND

_218

GN

D_2

17G

ND

_216

GN

D_2

15G

ND

_214

GN

D_2

13G

ND

_212

GN

D_2

11G

ND

_210

GN

D_2

09G

ND

_208

GN

D_2

07G

ND

_206

GN

D_2

05G

ND

_204

GN

D_2

03G

ND

_202

GN

D_2

01G

ND

_200

GN

D_1

99G

ND

_198

GN

D_1

97G

ND

_196

GN

D_1

95G

ND

_194

GN

D_1

93G

ND

_192

GN

D_1

91G

ND

_190

GN

D_1

89G

ND

_188

GN

D_1

87G

ND

_186

GN

D_1

85G

ND

_184

GN

D_1

83G

ND

_182

GN

D_1

81

GND_180GND_179GND_178GND_177GND_176GND_175GND_174GND_173GND_172GND_171GND_170GND_169GND_168GND_167GND_166GND_165GND_164GND_163GND_162GND_161GND_160GND_159GND_158GND_157GND_156GND_155GND_154GND_153GND_152GND_151GND_150GND_149GND_148GND_147GND_146GND_145GND_144GND_143GND_142GND_141GND_140GND_139GND_138GND_137GND_136GND_135GND_134GND_133GND_132GND_131GND_130GND_129GND_128GND_127GND_126GND_125GND_124GND_123GND_122GND_121GND_120GND_119GND_118GND_117GND_116GND_115GND_114GND_113GND_112GND_111GND_110GND_109GND_108GND_107GND_106GND_105GND_104GND_103GND_102GND_101GND_100

GND_99GND_98GND_97GND_96GND_95GND_94GND_93GND_92GND_91

GND_90GND_89GND_88GND_87GND_86GND_85GND_84GND_83GND_82GND_81GND_80GND_79GND_78GND_77GND_76GND_75GND_74GND_73GND_72GND_71GND_70GND_69GND_68GND_67GND_66GND_65GND_64GND_63GND_62GND_61GND_60GND_59GND_58GND_57GND_56GND_55GND_54GND_53GND_52GND_51GND_50GND_49GND_48GND_47GND_46GND_45GND_44GND_43GND_42GND_41GND_40GND_39GND_38GND_37GND_36GND_35GND_34GND_33GND_32GND_31GND_30GND_29GND_28GND_27GND_26GND_25GND_24GND_23GND_22GND_21GND_20GND_19GND_18GND_17GND_16GND_15GND_14GND_13GND_12GND_11GND_10GND_9GND_8GND_7GND_6GND_5GND_4GND_3GND_2GND_1GND

5SEEBH40C2NVCC_AUX_5VCC_AUX_4VCC_AUX_3VCC_AUX_2VCC_AUX_1

VCC_AUX

VCCD_FPLL_9VCCD_FPLL_8VCCD_FPLL_7VCCD_FPLL_6VCCD_FPLL_5VCCD_FPLL_4VCCD_FPLL_3VCCD_FPLL_2VCCD_FPLL_1

VCCD_FPLL

VCCA_FPLL_9VCCA_FPLL_8VCCA_FPLL_7VCCA_FPLL_6VCCA_FPLL_5VCCA_FPLL_4VCCA_FPLL_3VCCA_FPLL_2VCCA_FPLL_1

VCCA_FPLL

VCCPGM_1VCCPGM

VCCPT_5VCCPT_4VCCPT_3VCCPT_2VCCPT_1

VCCPT

VCC_44VCC_43VCC_42VCC_41VCC_40VCC_39VCC_38VCC_37VCC_36VCC_35VCC_34VCC_33VCC_32VCC_31VCC_30VCC_29VCC_28VCC_27VCC_26VCC_25VCC_24VCC_23VCC_22VCC_21VCC_20VCC_19VCC_18VCC_17VCC_16VCC_15VCC_14VCC_13VCC_12VCC_11VCC_10VCC_9VCC_8VCC_7VCC_6VCC_5VCC_4VCC_3VCC_2VCC_1VCC

VCC

1

Preliminary

PU 2

PU 3if NU GND or VCC

DIGILAB SX V

config

PU 2

PU 2

PU 3

PU 2PU 1

+0V9

+0V9

+2V5_PLL

+2V5_PLL +2V5

+2V5

+2V5_B8

GND

+2V5_B8

47UF20%

C5

C1210

N29N11J20AK20AG29AG11

Y11AC11Y29AC29H32P21H8AL8AF20AM32

W11AD11W29AD29J32P20J8AK8AG20AL32

AJ9AL31

R28R13P19AE28AE13AD19

Y21Y23Y22Y19Y18Y17

W22W21W20W19W18V23V22V21V19V18V17U22U21U20U18U17T23T22T20T19T18

AB22AB21AB20AB19AB18AB17AA23AA22AA19AA18

R23R21R19R17

AC23AC21AC19AC17

U30

AA20 Y9 Y8 Y32

Y30

Y28

Y27

Y25

Y15

Y12

Y10

W9

W8

W32

W31

W30

W28

W23

W17

W12

W10 V9 V8 V3

2V3

1V3

0V2

8V2

5V2

0V1

5V1

3V1

2V1

1V1

0 U8

U32

U23

U19 T8 T32

T29

T26

T21

T17

T14

T11

R5

R35

R34

R33

R22

R20

R18

P9 P6 P4 P35

P33

P30

P27

P24

P18

P15

P12

N5

N35

M7

M4

M35

M34

M31

M28

M25

M22

M19

M16

M13

M10

L5 L35

K8 K5 K35

K32

K29

K26

K23

K20

K17

K14

K11

J5 J35

H9H6H5H35H33H30H27H24H21H18H15H12G5G35F7F5F35F34F31F28F25F22F19F16F13F10E5E35D8D5D35D32D29D26D23D20D17D14D11C5C35B9B6B5B4B38B37B36B35B33B30B3B27B24B21B2B18B15B12AV9AV6AV33AV30AV27AV24AV21AV18AV15AV12AU5AU35AT7AT4AT36AT34AT31AT28AT25AT22AT19AT16AT13AT10AR5AR35AP8AP5AP35AP32AP29

AP26AP23AP20AP17AP14AP11AN5

AN35AM9AM6AM4

AM36AM33AM30AM27AM24AM21AM18AM15AM12

AL9AL5

AL35AK7AK4

AK36AK34AK31AK28AK25AK22AK19AK16AK13AK10

AJ5AJ35AH8AH5

AH35AH32AH29AH26AH23AH20AH17AH14AH11AG7AG5

AG35AG33

AF9AF8

AF32AF30AF27AF24AF21AF18AF15AF12AE8

AE32AD31AD28AD25AD13AD10AC7

AC33AC22AC20AC18AC16

AB8AB32AB29AB26AB23AB14AB11

AA8AA32AA21AA17AA11

A38A2M5

AT5

U30

+0V9

+0V9

AU31AW33

AU28AW30

AW24AW27

AU22AW21

AW6

AW12AW9

AU13AW15

AU19AW18

C6

A9C11

A12A15

A18C17

A33

C32

A30C29

A24A27

A21C23

AR29AR32

AR23AR26

AR10AR13AR16

E10E13E16

E22E26E29

AJ31AJ28AJ25AJ23

AJ8AJ11AJ14AJ16

L7L10L14L17

L32L29L25L22

U30

+0V9

+3V0

+3V0+3V0

GND

+3V0

+2V5+2V5

+1V5

+3V0

47UF20%

C2

C1210

C51560PF

C52560PF

C53560PF

C54560PF

C55560PF

10V1UF

10%

C133C451NF

C132

10%1UF

10V

C431NF

C4210NF

C4010NF

C411NF

C134100NF

C4410NF

C131100NF

C130100NF

C164

10%1UF

10V

47UF20%

C1

C1210

C127

10%1UF

10V

C128100NF

C331NF

C3210NF

C126100NF

C311NF

C3010NF

C125100NF

C3410NF

C351NF

GND

FB3

C661NF

C6510NF

C145100NF

C144

10%1UF

10V

C143

10%1UF

10V

C641NF

C6310NF

C142100NF

C621NF

C6110NF

C141100NF

C721NF

C7110NF

C150100NF

C149

10%1UF

10V

C148

10%1UF

10V

C701NF

C6910NF

C147100NF

C681NF

C6710NF

C146100NF

+3V0

47UF20%

C6

C1210

C741NF

C7310NF

C151100NF 47UF

20%

C7

C1210

C801NF

C7910NF

C156100NF 47UF

20%

C8

C1210

+2V5_PLL

+2V5_PLL

149-12-2014_10:30

STRATIXV_V1_0

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

+2V5_PLL+2V5_PLL+2V5_PLL+2V5_PLL+2V5_PLL+2V5_PLL

+2V5_PLL+2V5_PLL

+2V5+2V5

GND

+3V0

GND

C781NF

C7710NF

C155100NF

C154

10%1UF

10V

C761NF

C153

10%1UF

10V

C7510NF

C152100NF

+3V0

GND

C841NF

C8310NF

C160100NF

C159

10%1UF

10V

C821NF

C158

10%1UF

10V

C8110NF

C157100NF

GND

GND

C2110NF

C201NF

C56100NF

C47

10%1UF

10VGND

C4610NF

C221NF

C58100NF

C57

10%1UF

10VGND

47UF20%

C59

C1210

C8610NF

C851NF

C129100NF

C114

10%1UF

10VGND

C11310NF

C1121NF

GND

47UF20%

C137

C1210

C13910NF

C1381NF

C165100NF

C140

10%1UF

10VGND

GND

GND

+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+1V5+1V5+1V5+1V5+1V5+1V5+1V5+1V5+1V5

+1V5+1V5+1V5+1V5+1V5+1V5

+2V5+2V5

+3V0+3V0

GNDGNDGNDGND

GNDGNDGNDGND

GNDGNDGNDGND

GNDGNDGNDGND

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0+3V0

+3V0

+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9+0V9

+0V9

+0V9 +0V9

+2V5_B8

+2V5_B8+2V5_B8

+2V5_B8+2V5_B8

+2V5_B8+2V5_B8

C2101NF

C20910NF

C220100NF

C219

10%1UF

10VGND

C2121NF

C21110NF

C222100NF

C221

10%1UF

10V

+2V5_B8

GND

C2141NF

C21310NF

C224100NF

C223

10%1UF

10V

+2V5_B8

GND

+2V5_B8+2V5_B8+2V5_B8

C50560PF

1

11

1

1

1

1

1 1

11

111

1 1

1 1

1 1

1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1

0R 1%

23 1

0R 1%

23 1

6,88

UHF38

LTC3415

BSELCLKIN

CLK

OU

T

FVB

ITH

ITH

M

MGN

MODE

NC1 NC2

PG

ND

1P

GN

D2

PG

ND

3P

GN

D4

PG

ND

5P

GN

D6

PGOOD

PHMODE

PLLPFPVIN1PVIN2

PVIN3PVIN4

PVIN

5PV

IN6

RU

N

SGND

SVIN

SW1SW2SW3SW4

SW5SW6SW7SW8

TRACK

PG

ND

7

PG

ND

8

0R 1%

23 1

1

6,88

UHF38

LTC3415

BSELCLKIN

CLK

OU

T

FVB

ITH

ITH

M

MGN

MODE

NC1 NC2

PGN

D1

PGN

D2

PGN

D3

PGN

D4

PGN

D5

PGN

D6

PGOOD

PHMODE

PLLPFPVIN1PVIN2

PVIN3PVIN4

PVIN

5PV

IN6

RU

N

SGND

SVIN

SW1SW2SW3SW4

SW5SW6SW7SW8

TRACK

PGN

D7

PGN

D8

1

1

1

TBD

1

TBD

1

1

6,88

UHF38

LTC3415

BSELCLKIN

CLK

OU

TFVB

ITH

ITH

M

MGN

MODE

NC1 NC2

PGN

D1

PGN

D2

PGN

D3

PGN

D4

PGN

D5

PGN

D6

PGOOD

PHMODE

PLLPFPVIN1PVIN2

PVIN3PVIN4

PVIN

5PV

IN6

RU

N

SGND

SVIN

SW1SW2SW3SW4

SW5SW6SW7SW8

TRACK

PGN

D7

PGN

D8

1

1

1

1

1

1

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

1

1

1

Preliminary

0°

spread spectrum optional

default

DIGILAB SX V

0v9 17APU 1

+5V

R06031%13K7R312

R06031%27K0R305

R311 R040233R

1%

NC

+5V

POW_GOOD_+0V9

+0V9

CLK_MASTER

CLK_MASTER

CLK_MASTER2

159-1-2014_16:50

STRATIXV_V1_0

L10

0U25WE_HC2

100PF10%

C313

C0402

R297 R040210K

1%

10PF10%

C314

C0402

100PF10%

C315

C0402

R300 R040210K

1%

10PF10%

C316

C0402

2111

3829

3233

20

10

1 31

13 14 15 16 17 18

22

12

345

2827

353637

2

346789

26252423

30

19 39

U69

R11 R0402NB

1%

NB10%

C39

C0402

NB10%

C38

C0402

1NF10%

C37

C0402

R10 R040210K

1%

100PF10%

C36

C0402

2111

38

29

3233

20

10

1 31

13 14 15 16 17 18

22

12

345

2827

353637

2

34

6789

26252423

30

19 39

U70

R301 R040210K

1%

R3

R06

03D

OU

BLE 2111

38

29

3233

20

10

1 31

13 14 15 16 17 18

22

12

345

2827

353637

2

34

6789

26252423

30

19 39

U68

R1

R06

03D

OU

BLE

R2

R06

03D

OU

BLE

_+80/-20%

C39410UF

C1206

_+80/-20%

C40110UF

C1206

_+80/-20%

C40210UF

C1206

_+80/-20%

C40310UF

C1206

47UF20%

C277

C1210

47UF20%

C282

C1210

_+80/-20%

C40810UF

C1206

_+80/-20%

C40910UF

C1206

_+80/-20%

C41010UF

C1206

_+80/-20%

C41110UF

C1206

47UF20%

C281

C1210

47UF20%

C280

C1210

_+80/-20%

C40410UF

C1206

_+80/-20%

C40510UF

C1206

_+80/-20%

C40610UF

C1206

_+80/-20%

C40710UF

C1206

100NF10%

C418

C0603

22UF20%

C398

C1210

22UF20%

C397

C1210

22UF20%

C396

C1210

22UF20%

C395

C1210

22UF20%

C400

C1210

22UF20%

C399

C1210

100NF10%

C266

C0603

100NF10%

C264

C0603

100NF10%

C263

C0603

100NF10%

C267

C0603

100NF10%

C419

C0603

100NF10%

C270

C0603

100NF10%

C268

C0603

R310 R040233R

1%

L11

0U25WE_HC2

R298 R040210K

1%

R296 R040210K

1%

100NF10%

C420

C0603

47UF20%

C278

C1210

L9

0U25WE_HC2

47UF20%

C279

C1210

ITH

+0V9PSW3

+5V

+5V

+5VGND

+5V+5V

+5V

+5V

GND

NC

GND

GND

GND

GND

+5V

PSW2

GND

GND

PSW2PSW2

PSW3PSW3PSW3PSW3

PSW3PSW3PSW3PSW3

+5V

PSW2

PSW2

PSW2

PSW2

PSW2PSW2

GND

+5V

GND

NC

GND

+5V+5V

NC

NC

GND

PSW1PSW1PSW1PSW1

NC

PSW1PSW1PSW1PSW1

NCNC

GND

+5V

NCGND

NC

GND

+5V+5V

NC

NC

GND

GND

+5V

GND

GNDGND

GNDGND

GND

PSW1

GND

GND

+5V +5V+5V

GNDGND

GND

GND

+5V

+5V

+5V

+5V

+5V

+5V

GND+5V

+5V

+0V9

R275 R040233R

1%CLK_MASTER3

1

1

1

1111 1 1

11

0R 1%

23 1

1

1

11

1 111

1

0R2

3 1

1 111

1

1

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbHFIDUCIAL_RND

FIDUCIAL_RND

FIDUCIAL_RND

FIDUCIAL_RND

1

1

ON/OFF

R1_C1 R2

VIN VOUT1_C1VOUT2_C1

PKG_TYPE=SUPSOT-6

12

VERS T/R OK

BAS85SOD80C

2

1

1

1

1

6,88

UHF38

LTC3415

BSELCLKIN

CLK

OU

T

FVB

ITH

ITH

M

MGN

MODE

NC1 NC2

PGN

D1

PGN

D2

PGN

D3

PGN

D4

PGN

D5

PGN

D6

PGOOD

PHMODE

PLLPFPVIN1PVIN2

PVIN3PVIN4

PVIN

5PV

IN6

RU

N

SGND

SVIN

SW1SW2SW3SW4

SW5SW6SW7SW8

TRACK

PGN

D7

PGN

D8

1 1 1 1

1

1

1

0R2

31

1

11

SS_TREN

AVIN

PVIN2PVIN1

PPADPGND2PGND1

AGND

SW3SW2SW1

TPS62140

PVQFN16 FB

PG

VOS

DEFFSW

TPS62040L

PVSON10

SW2SW1

GND

VIN2VIN1

PGND2PGND1

PPAD

FB

MODE

EN

1

1

1

1

PU 2

Preliminary

Passermarken

default ON

Montagebohrungen

Messpunkte

DIGILAB SX V

PU 3

1V5 900mA

FAN

+2V5 0,5A

POS 1-3PU 2

+3v0

TP9

+2V5

R06031%12K5R256

R06031%49K9R261 C197

270PF

C040250V

C200100NF

C060350V

+5V78

4

32

910

11

5

6

1

U67

+1V5

913

10

1211

1716156

321

5

4

14

87

U9

C16610UF

C080510V

+5V

C199100NF

C060350V

C1961NF

R26

R7 10K

R06031%10K0R122

R06031%8K7R255

TP2

TP13

22UF20%

C173

C1210

22UF20%

C172

C1210

22UF20%

C170

C1210

22UF20%

C169

C1210

2111

38

29

3233

20

10

1 31

13 14 15 16 17 18

22

12

345

2827

353637

2

34

6789

26252423

30

19 39

U74

POW_GOOD_3V3

POW_GOOD_3V3

+3V0

R06031%27K0R286

R06031%6K8R278

C2011N5

C060350V

POW_GOOD_+0V9

+5V

POW_GOOD_+0V9

CLK_MASTER3

USER INTERFACEIMP=NA

CONNECTION=NO CONTP11

+0V9

GND

GND

D7

ASSEMBLED=B_10 S 7488

GND

MH1

MTHOLE250

MTHOLE250

MH2

MTHOLE250

MTHOLE250

J30S

IP-2P

NA

32

4

5

6 1

U47

DEVICE=FDC6330LR06031%1K0R161

R160 R0402100R

1%

PM4

PM3

PM2

PM1

169-18-2014_8:43

STRATIXV_V1_0

TP12

TP10

TP8

TP7

TP6

TP5

TP4

TP3

MH6

MTHOLE250

MTHOLE250

MH5

MTHOLE250

MTHOLE250

MH4

MTHOLE250

MTHOLE250

MH3

MTHOLE250

MTHOLE250

+3V0

+2V5

NC

GND

+5V

GND

GND

GND

GND

GND

GND

GND

GNDGND

GNDGND

MH8

MTHOLE250

MTHOLE250

MH7

MTHOLE250

MTHOLE250

GND

GND

C13

10%1NF

C0402

+5V

R06031%10K0R162

PWM_FAN

+3V0

MH12

MTHOLE250

MTHOLE250

MH11

MTHOLE250

MTHOLE250

MH10

MTHOLE250

MTHOLE250

MH9

MTHOLE250

MTHOLE250

GNDGND

GNDGND

L3

3U3WE-PD

C4910UF

C080510V

C4810UF

C080510V

C1510UF

C080510V

C1410UF

C080510V

GND

R51

L2

7U4L_SRR6038

C19010UF

C080510V

C18910UF

C080510V

C18610UF

C080510V

C17110UF

C080510V

C16710UF

C080510V

GND

+1V5TP1

22UF20%

C228

C1210

22UF20%

C227

C1210

100PF10%

C230

C0402 R277 R040210K

1%

R27

4R

0603

DO

UB

LE

0603

DO

UB

LE

100NF10%

C233

PKG_TYPE=0603C0603

100NF10%

C232

PKG_TYPE=0603C0603

47UF20%

C218

C1210

47UF20%

C217

C1210

L6

0U25WE_HC2

_+80/-20%

C23710UF

C1206

_+80/-20%

C23610UF

C1206

_+80/-20%

C23510UF

C1206

_+80/-20%

C23410UF

C1206

R276 R040210K

1%

10PF10%

C229

C0402

100NF10%

C231

PKG_TYPE=0603C0603

GND+5V

+3V0PSW4

PSW4PSW4PSW4PSW4

PSW4PSW4PSW4PSW4

NC +5V

+5V

+5V

GND

+5V

NCGND

NC

GND

GND

+5V+5V

NC

NC

+5V

GND

GNDGNDGND

GND

+2V5_B8

+3V3

GND

+5V

1 111

1 1

1

1

0R2

3 1

TPS62040L

PVSON10

SW2SW1

GND

VIN2VIN1

PGND2PGND1

PPAD

FB

MODE

EN

1

1

11

1 11

1

1

1

D G

S1S2S3

BSC050NTDSON-8

1

D G

S1S2S3

BSC050NTDSON-8

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

B_35F234 / 236BANANE_LP180

B_35F234 / 236BANANE_LP180

11

1

1

AJ210B

LG

ILIM

SW

BST

VCC

HG

PGND2PGND1SGND2

VIN

SGND1

EN

SS

RON

FB

LM3150

TSSOP14_P

12

1

1

1

POS 1-3

Preliminary

4A max

POWER PLUGs

DIGILAB SX V

+2V5 / 3V0PU 2

Switch 3V0/2V5 (open for 2V5)

+2V5_B8

R06031%49K9R284

R06031%10K0R283

R06031%2K5R287

GND

J12S

IP-2P

NA

13

8

10

12

1

11

1514

9

2

5

3

6

7

4

U62

32

1

J6

SW

+12V_D

L1

4UH7WE_HCI

R237 R06031K5

1%

C177270PF

C040250V

R06031%1M0R234

R06031%75K0R236

+12V

+12VNC

GND

A KV1

MBRS4201 SMC

USER INTERFACEIMP=NA

CONNECTION=FLOPPY

J23

J22

GNDGND

179-5-2014_10:19

STRATIXV_V1_0

+12V+12V

5 4

123

U64

C18310%470NF

C1206

CP6C_100UF_50V100UF

5 4

123

U63

C17510UF

C121050V

R04021%10KR233

R06031%150KR235

C17410UF

C121050V

C182100NF

C060350V

C181100NF

C060350V

C180100NF

C060350V

C1791UF

C060325V

C1761NF

C040250V

C178100NF

C060350V

GND

GND

GND

GND

GND

GNDGNDGNDGND

GND

GND

78

4

32

910

11

5

6

1

U72

R28

2

C215270PF

C040250V

C2261N5

C060350V

L5

7U4L_SRR6038

C225100NF

C060350V

C20710UF

C080510V

C20610UF

C080510V

C20510UF

C080510V

C20410UF

C080510V

C20310UF

C080510V

POW_GOOD_+0V9

+5V

GND

CP5TANTD47UF

CP4TANTD47UF47UF

TANTD

CP1 CP7TANTD47UF

GND

+5V

A B C D E F G H I J

1

2

3

4

5

6

7

Document Name

Title

Date Sheet

AuthorFH

El Camino GmbH

5SEEBH40C2N

5SEEBH40C2N

NC

_371

NC

_370

NC

_369

NC

_368

NC

_367

NC

_366

NC

_365

NC

_364

NC

_363

NC

_362

NC

_361

NC

_360

NC

_359

NC

_358

NC

_357

NC

_356

NC

_355

NC

_354

NC

_353

NC

_352

NC

_351

NC

_350

NC

_349

NC

_348

NC

_347

NC

_346

NC

_345

NC

_344

NC

_343

NC

_342

NC

_341

NC

_340

NC

_339

NC

_338

NC

_337

NC

_336

NC

_335

NC

_334

NC

_333

NC

_332

NC

_331

NC

_330

NC

_329

NC

_328

NC

_327

NC

_326

NC

_325

NC

_324

NC

_323

NC

_322

NC

_321

NC

_320

NC

_319

NC

_318

NC

_317

NC

_316

NC

_315

NC

_314

NC

_313

NC

_312

NC

_311

NC

_310

NC

_309

NC

_308

NC

_307

NC

_306

NC

_305

NC

_304

NC

_303

NC

_302

NC

_301

NC

_300

NC

_299

NC

_298

NC

_297

NC

_296

NC

_295

NC

_294

NC

_293

NC

_292

NC

_291

NC

_290

NC

_289

NC

_288

NC

_287

NC

_286

NC

_285

NC

_284

NC

_283

NC

_282

NC

_281

NC

_280

NC

_279

NC

_278

NC

_277

NC

_276

NC

_275

NC

_274

NC

_273

NC

_272

NC

_271

NC

_270

NC

_269

NC

_268

NC

_267

NC

_266

NC

_265

NC

_264

NC

_263

NC

_262

NC

_261

NC

_260

NC

_259

NC

_258

NC

_257

NC

_256

NC

_255

NC

_254

NC

_253

NC

_252

NC

_251

NC

_250

NC

_249

NC

_248

NC

_247

NC

_246

NC

_245

NC

_244

NC

_243

NC

_242

NC

_241

NC

_240

NC

_239

NC

_238

NC

_237

NC

_236

NC

_235

NC

_234

NC

_233

NC

_232

NC

_231

NC

_230

NC

_229

NC

_228

NC

_227

NC

_226

NC

_225

NC

_224

NC

_223

NC

_222

NC

_221

NC

_220

NC

_219

NC

_218

NC

_217

NC

_216

NC

_215

NC

_214

NC

_213

NC

_212

NC

_211

NC

_210

NC

_209

NC

_208

NC

_207

NC

_206

NC

_205

NC

_204

NC

_203

NC

_202

NC_201NC_200NC_199NC_198NC_197NC_196NC_195NC_194NC_193NC_192NC_191NC_190NC_189NC_188NC_187NC_186NC_185NC_184NC_183NC_182NC_181NC_180NC_179NC_178NC_177NC_176NC_175NC_174NC_173NC_172NC_171NC_170NC_169NC_168NC_167NC_166NC_165NC_164NC_163NC_162NC_161NC_160NC_159NC_158NC_157NC_156NC_155NC_154NC_153NC_152NC_151NC_150NC_149NC_148NC_147NC_146NC_145NC_144NC_143NC_142NC_141NC_140NC_139NC_138NC_137NC_136NC_135NC_134NC_133NC_132NC_131NC_130NC_129NC_128NC_127NC_126NC_125NC_124NC_123NC_122NC_121NC_120NC_119NC_118NC_117NC_116NC_115NC_114NC_113NC_112NC_111NC_110NC_109NC_108NC_107NC_106NC_105NC_104NC_103NC_102NC_101

NC_100NC_99NC_98NC_97NC_96NC_95NC_94NC_93NC_92NC_91NC_90NC_89NC_88NC_87NC_86NC_85NC_84NC_83NC_82NC_81NC_80NC_79NC_78NC_77NC_76NC_75NC_74NC_73NC_72NC_71NC_70NC_69NC_68NC_67NC_66NC_65NC_64NC_63NC_62NC_61NC_60NC_59NC_58NC_57NC_56NC_55NC_54NC_53NC_52NC_51NC_50NC_49NC_48NC_47NC_46NC_45NC_44NC_43NC_42NC_41NC_40NC_39NC_38NC_37NC_36NC_35NC_34NC_33NC_32NC_31NC_30NC_29NC_28NC_27NC_26NC_25NC_24NC_23NC_22NC_21NC_20NC_19NC_18NC_17NC_16NC_15NC_14NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1NC

DIGILAB SX V

Preliminary

Y7 Y6 Y5 Y4 Y39

Y38

Y37

Y36

Y35

Y34

Y33 Y3 Y26

Y24 Y2 Y16

Y14

Y13 Y1 W7

W6

W5

W4

W39

W38

W37

W36

W35

W34

W33 W

3W

27W

26W

25W

24 W2

W16

W15

W14

W13 W

1 V7 V6 V5 V4 V39

V38

V37

V36

V35

V34

V33 V3 V27

V26

V24 V2 V16

V14 V1 U7

U6

U5

U4

U39

U38

U37

U36

U35

U34

U33 U

3U

24 U2

U16 U

1 T7 T6 T5 T4 T39

T38

T37

T36

T35

T34

T33

T3 T2 T1 R4

R39

R38

R37

R36

R3

R2

R1

P39

P38

P37

P36

P3 P2 P1 N4

N39

N38

N37

N36

N3

N2

N1

M39

M38

M37

M36

M3

M2

M1

L4 L39

L38

L37

L36

L3 L2 L1 K4 K39

K38

K37

K36

K3 K2 K1 J4 J39

J38

J37

J36

J3 J2 J1 H4

H39

H38

H37

H36

H3

H2

H1

G4

G39

G38

G37

G36

G3

G2

G1

F4 F39

F38

F37

F36

F3 F2 F1 E4 E39

E38E37E36E3E2E1D4D39D38D37D36D3D2D1C4C39C38C37C36C3C2C1AW38AW37AW3AW2AV4AV39AV38AV37AV36AV3AV2AV1AU4AU39AU38AU37AU36AU3AU2AU1AT39AT38AT37AT3AT2AT1AR4AR39AR38AR37AR36AR3AR2AR1AP4AP39AP38AP37AP36AP3AP2AP1AN4AN39AN38AN37AN36AN3AN2AN1AM39AM38AM37AM3AM2AM1AL4AL39AL38AL37AL36AL3AL2AL1AK39AK38AK37AK3AK2AK1AJ4AJ39AJ38AJ37AJ36AJ3AJ2AJ1AH4

AH39AH38AH37AH36AH3AH2AH1AG6AG4

AG39AG38AG37AG36AG34

AG3AG2AG1AF7AF6AF5AF4

AF39AF38AF37AF36AF35AF34AF33

AF3AF2AF1AE7AE6AE5AE4

AE39AE38AE37AE36AE35AE34AE33

AE3AE2AE1AD7AD6AD5AD4

AD39AD38AD37AD36AD35AD34AD33AD3AD2AD1AC6AC5AC4

AC39AC38AC37AC36AC35AC34AC3AC2AC1AB7AB6AB5AB4

AB39AB38AB37AB36AB35AB34AB33

AB3AB2AB1AA7AA6AA5AA4

AA39AA38AA37AA36AA35AA34AA33

AA3AA24

AA2AA16

AA1

U30

U30

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

189-3-2014_9:31

STRATIXV_V1_0

Documents

DIGILAB SX V Data Sheet - Altera connector for Altera download cable ... active cooling may be necessary . A 5V DC cooling fan is connect- ... DQ_21 AR15 U32 U44 SRAM_WE AP6 both