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DIGITAL I SPRING 2009LABORATORY ASSIGNMENT 2

The goal for this lab is to introduce the hierarchical design techniqueusing Verilog.

For this lab you will turn in (due 2 weeks from date of lab) a report withthe following:

1. Title page (course, date, team members)2. Introduction describing the tasks3. Simulation only for PART A4. Follow instructions in PARTs B & C5. Conclusion

PART AYou have already seen the Xilinx ISE software and learned the form forVerilog primitives that describe logic gates. For your first task you willsimulate a simple counter circuit that is written in Verilog code. You willcreate a half adder and full adder, then design and build a circuit to dobinary addition of 3-bits.

Start ISE from the Start menu by selecting:Start All Programs Xilinx ISE 9.1i Project Navigator

Create a new project:

1. Select File > New Project...The New Project Wizard appears.2. Type lab_two in the Project Name field.3. Leave the local Project Location for this tutorial.4. Verify that HDL is selected from the Top-Level Source Type list.5. Click Next to move to the device properties page. (Figure on next page.)6. Fill in the properties in the table as shown below:

Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields.7. Click Next to proceed to the Create New Source window in the New Project Wizard.Atthe end of the next section, your new project will be complete.

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Create the top-level Schematic source file for the project as follows:

1. Click New Source in the New Project dialog box.2. Select Verilog Module as the source type in the New Source dialog box.3. Type in the file name counter.4. Verify that the Add to Project checkbox is selected.

5. Click Next.6. Declare the ports for the counter design by filling in the port information as shownbelow:

7. Click Next, then Finish in the New Source Information dialog box to complete thenewsource file template.8. Click Next, then Next, then Finish.

When you choose the counter.v tab you will see the outline of a Verilog module.Notice that it looks somewhat different than the examples in the textbook. Bothmethods of listing inputs and outputs are correct!

Now fill in the code for the counter as shown below you wont recognize all thecommands but for this tutorial just copy what is shown below.

module counter(CLOCK, DIRECTION, COUNT_OUT);input CLOCK;

input DIRECTION;

output [3:0] COUNT_OUT;

reg [3:0] count_int = 0;

always @(posedge CLOCK)

if (DIRECTION)

count_int

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else

count_int

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Leave the default values in the remaining fields.

8. Click Finish to complete the timing initialization.9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the

Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port todefine the input stimulus for the counter design as follows:Click on the blue cell at approximately the 300 ns to assert DIRECTION high sothat the counter will count up.Click on the blue cell at approximately the 900 ns to assert DIRECTION low sothat the counter will count down.

10. Save the waveform.11. In the Sources window, select the Behavioral Simulation view to see that the

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testbench waveform file is automatically added to your project.

Verify that the counter design functions as you expect by performing behaviorsimulation

as follows:1. Verify that Behavioral Simulation and counter_tbw are selected in the Sourceswindow.2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process anddouble-click the Simulate Behavioral Model process.

The ISE Simulator opens and runs the simulation to the end of the test bench.3. To view your simulation results, select the Simulation tab and zoom in on thetransitions.

Note: by selecting COUNT_OUT and right-clicking you can change the hex version todecimal. You can expand COUNT_OUT to see the individual counter bits.

PART B

The Half Adder circuit shown on page 104 of your text is the basic buildingblock of the adder circuits you will be constructing for this lab. The circuit uses2 Verilog primitives, has 2 inputs and 2 outputs. In your lab report include aTruth Table for the Half Adder circuit.

Start a new project and perform a simulation of the Verilog module for the HalfAdder circuit. In your lab report include the simulation with all possiblevalues of inputs a and b.

Leave this project open.

A Full Adder (an adder that accepts a carry-in along with the a and b inputs) isbuilt from 2 Half Adders and an OR gate.

In your open project create a new source (Project > New Source) and create aVerilog module for the Full Adder that uses 2 instantiations of the existing HalfAdder. You may follow the format on page 109 of your text with oneexception. Xilinx requires you to use the I/O designation for a nested modulethat is described on page 115 Figure 4-9. So, for M1 in the example of Figure4.6:

Add_half_0_delay M1 (.sum(w1), .c_out(w2), .a(a), .b(b));

In your lab report include the Truth Table for the Full Adder and thesimulation with all possible values of inputs a, b and c_in. (Be sure toassociate your Full Adder Test Bench Waveform with your Full Adder source.)

PART C

Research and build with Verilog code a 3-bit Ripple Carry Adder (RCA). YourRCA must have carry-in and carry-out bits. The design must be hierarchical

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(i.e. it must be built from half adders and full adders). The lab report mustinclude a full written description of the RCA design with citations. Youmust include your Verilog code with comments and a simulation showingexample computations with both carry-in = 0 and carry-in = 1.

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