Different Commercial FPGAs Are

8/12/2019 Different Commercial FPGAs Are

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Commercial FPGAs are :-

1) Xilinx FPGA

2) Altera FPGA3) QuickLogic FPGA

4) Lattice emi FPGA

!) "icrosemi FPGA

#arious generation $ro%ucts o& Xilinx FPGA:-

C'aracteristics o& %i&&erent Commercial FPGAs

Xilinx

Arc'itecture:- (mmetric Arra(asic Logic lock:- Look *$ +a,le L*+)Programming +ec'nolog( :- .A" ,ase%

Altera

Programming +ec'nolog( :- /P.0" ,ase%asic Logic lock:- Look *$ +a,le L*+)

Arc'itecture:- ierarc'ical PLs

Actel

Arc'itecture :- .o ,ase% FPGA

asic Logic lock:- "ulti$lexer along it' Fli$ Flo$ use% as seuential logic5Programming +ec'nolog( :- Anti&use

Algotronix:-

Arc'itecture:- ea-o&-Gatesasic Logic lock:- "ux an% ,asic gates

Programming +ec'nolog(:- .A"



A":-

Arc'itecture:- ierarc'ical PL

asic Logic lock:- PL ,lock Programming +ec'nolog(:- //P.0"

QuickLogicArc'itecture:- ea o& Gates

asic Logic lock:- 4X1 "ux

Programming +ec'nolog(:- Anti&use

Com$an( Arc'itecture asic Logic lock Programming tec'nolog(

Xilinx (mmetric Arra( Look *$ +a,le L*+) .A"

Altera /P.0" Look *$ +a,le L*+) ierarc'ical PLs

Actel .o ,ase% FPGAAlgotronix

A"QuickLogic

Different Generations of Commercial FPGAs

Xilinx FPGAs

1) Spartan 6

Spartan-6 FPGA Features

Features LX LXT

45nm low power process technology with 6-input LUTs

1080M! cloc" management tiles #$ %&M ' 1 (LL) $ - 6 $ - 6

$0M! *loc" +,M #.its) $16 - 48$4 /6 - 48$4

Memory interace controllers .loc"s 0 - 4 $ - 4

1082.ps Select3 technology

/0M! %S(48,1 slices 8 - 180 8 - 180

$2.ps 2T( transceiers - $ - 8

(&3 7press 7n9point .loc"s - 1

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/lx.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/lxt.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/45nm-low-power-process-technology-with-6-input-luts.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/1080mhz-clock-management-tiles.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/320mhz-block-ram.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/memory-interface-controllers-blocks.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/108gbps-selectio-technology.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/390mhz-dsp48a1-slices.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/32gbps-gtp-transceivers.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/pci-express-endpoint-blocks.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/lxt.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/45nm-low-power-process-technology-with-6-input-luts.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/1080mhz-clock-management-tiles.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/320mhz-block-ram.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/memory-interface-controllers-blocks.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/108gbps-selectio-technology.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/390mhz-dsp48a1-slices.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/32gbps-gtp-transceivers.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/pci-express-endpoint-blocks.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/lx.html



Features LX LXT

7m.e99e9 processing

Low power management mo9es

7nhance9 coniguration an9 .itstream protection

Applications

$) :irte ;

Features(rogramma.le System 3ntegration

Up to $M logic cells< :&= component< ,=3 3(< an9 ,MS integration

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/embedded-processing.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/low-power-management-modes.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/enhanced-configuration-and-bitstream-protection.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/embedded-processing.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/low-power-management-modes.html

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/modals/enhanced-configuration-and-bitstream-protection.html



3ncrease9 System (erormance

Up to $8 T.>s total serial .an9wi9th with up to /6 112 2Ts< up to 16 $8052 2Ts< 5<52M,&s< 68M. *+,M< %%+-1866

*M &ost +e9uction

Up to 40? lower cost than multi-chip solution< 7asy(ath-; cost re9uction path

Total (ower +e9uction

Up to ;0? lower power than multi-chip solution

,ccelerate9 %esign (ro9uctiityScala.le optimi!e9 architecture< comprehensie tools< 3( an9 T%(s

Applications:irte-; @(2,s a99ress the insatia.le 9eman9 or networ"ing inrastructure .an9wi9th an9 logiccapacity or ,S3& prototyping an9 emulation %eice applications inclu9e the ollowingA

,S3& (rototyping $1002 TU4 Transpon9er>Line &ar9 102(B>1027(B LT Line &ar9 10027 Line &ar9 1002 TB Mupon9er

002 3nterla"en *ri9ge 4002 Line &ar9 (orta.le +,%,+ Systems Tera.it Switch @a.ric

) inte ;Features(rogramma.le System 3ntegration

Up to 4;8 L&sC :&= component integration< ,=3 3( an9 ,MS integration


Up to $ 1$52 2Ts< $<845 2M,&s< 4M. *+,M< %%+-1866

*M &ost +e9uction

al the price o similar 9ensity 40nm 9eices< 7asy(ath cost re9uction


50? lower power than preious generation 40nm 9eices

,ccelerate9 %esign (ro9uctiity

Scala.le optimi!e9 architecture< comprehensie tools< 3( an9 *oar9s an9 its



ApplicationsinteD-; @(2,s 9elier high signal processing perormance an9 low power consumption or a.roa9 range o applications inclu9ingA

,ionics L7% *ac"lit @lat (anel %isplays an9 %T:

LT7 *ase.an9 (orta.le Ultrasoun9

Multi-mo9e +a9io (rosumer %igital SL+ &ameras :i9eo oer 3( 2ateway

4) ,rti ;Applications

,rti-; @(2,s 9elier a9antages in lowest cost an9 lowest power< i9eally suite9 or high-olume

applications inclu9ingA

Low &ost Ultrasoun9 Eireless *ac"haul

(rogramma.le Logic &ontroller Sotware %eine9 +a9io

Features

(rogramma.le System 3ntegration

Up to $15 L&sC ,=3 3( an9 ,nalog Mie9 Signal integration


Up to 16 662 2Ts< /0 2M,&>s< 1M. *+,M< 1$2.>s L:%S< %%+-1066

*M &ost +e9uction

Small wire .on9 pac"aging an9 up to F5 analog component saings


65? lower static an9 50? lower power than 45nm generation 9eices

,ccelerate9 %esign (ro9uctiity

Scala.le optimi!e9 architecture< comprehensie tools an9 3(

Microsemi @(2,s

1) 32L$ @(2,sMicrosemiGs 32LD$ @(2,s< targete9 at the cost-optimi!e9 @(2, mar"et< integrate ourth



generation lash-.ase9 @(2, a.ric an9 high perormance communications interaces on a singlechip The 32L$ @(2,s oer a cost optimi!e9 @(2, with .est-in-class eature integrationcouple9 with the lowest power< highest relia.ility an9 most a9ance9 security in the in9ustry

Microsemi Lea9ership in &ost-ptimi!e9 @(2,s ighest num.er o 52 transceiers ighest num.er o 2(3 ighest num.er o (&3 &ompliant : 3> nly @(2, with har9ene9 memory su.system nly non-olatile an9 instant-on mainstream @(2, Microsemi Lea9ership in Low (ower @(2,s = lower static power with no perormance penalties @lashH@ree!e real-time power management $5? lower total power

Microsemi Lea9ership in +elia.le @(2,s nly @(2, with S7U immune a.ric coniguration cells 7ten9e9 temperature support #Up to 1$5& TI) Microsemi Lea9ership in Secure @(2,s *uilt-in state-o-the-art 9esign security or all 9eices

7asy-to-useJ

$) Smart@usion$ So& @(2,sMicrosemiKs net-generation Smart@usionD$ So& @(2,s are the only 9eices that a99ressun9amental reuirements or a9ance9 security< high relia.ility an9 low power in criticalin9ustrial< military< aiation< communications an9 me9ical applications Smart@usion$ integratesan inherently relia.le lash-.ase9 @(2, a.ric< a 166 megahert! #M!) ,+M D &orteTM-Mprocessor< a9ance9 security processing accelerators< %S( .loc"s< S+,M< eB:M< an9 in9ustry-reuire9 high-perormance communication interaces all on a single chip

3n9ustryKs lowest static power ;mE 9uring operation on the 50 LUT 9eice $mE stan9.y power in @lashH@ree!e real-time low power state ,+M &orte-M low power mo9es So& peripheral low power mo9es Lea9ership in Low (ower @(2,s 10= lower static power with same perormance 50? Lower Total (ower Lea9ership in Secure @(2,s State o the art security ena.les root-o-trust applications +a9ically transorms the useulness o @(2,s in security applications Lea9ership in +elia.le @(2,s nly So& @(2, with S7U immune @(2, coniguration cells an9 processor +elia.ility 9esigne9 or saety critical an9 mission critical systems Lea9ership in +eal-Time @(2,s ,+MD &orte-M real-time microcontroller @lashH@ree!e real-time power management

3nstant on real-time aaila.ility

) (ro,S3& @(2,The (ro,S3&D series o low cost< low power @(2,s< which inclu9es (ro,S3&>7< (ro,S3&nano< an9 (ro,S3&L< oers a .rea"through in power< price< perormance< 9ensity< an9 eaturesor to9ayKs most 9eman9ing high-olume applications (ro,S3& 9eices support the ,+M -&orte-M1 sot processor 3( core< oering the .eneits o programma.ility an9 time-to-mar"et at acost as low as F04/ The (ro,S3& amilies are .ase9 on nonolatile lash technology an9support 10<000 to <000<000 gates< up to 6$0 3>s





User-programma.le (LLs can .e programme9 or cloc" reuency multiplication an9 9iision an9can .e use9 to improe 9esign 3> timingSmall orm actor pac"aging

Meets the nee9s o arious .oar9-space constraine9 enironments such as (&M&3,< &ar9.us<an9 Mini (&3< with a ariety o small outline pac"agesther Mature (ro9ucts

$) uic"+,MThe uic"+,MD amily o programma.le 9eices oers a uniue com.ination o +,M eaturesthat are i9eal or 9esigns with etremely high-perormance +,M< +M an9 @3@ reuirementsuic"+,M 9eices em.e9 up to $5<44 .its o S+,M in an array o conigura.le logic< ena.ling+,M an9 +M unctions to run at spee9s oer $00 M! an9 @3@s to run at spee9s o oer 160M!

igh-perormance an9 high-9ensity

%ensities oer 1;5<000 system gates with up to 16 3>sigh-spee9 7m.e99e9 S+,M

Multiple %ual-port +,M mo9ules in user-conigura.le 1<15$-.it .loc"s 5 ns access times< each port in9epen9ently accessi.le @ast an9 eicient or @3@< +,M an9 +M unctions +egistere9 3> cells with in9ii9ually controlle9 cloc"s an9 output ena.les

,9ance9 3> capa.ilities

Multi-olt compati.le 3>s or : an9 5 : system interaces (&3 compati.ility with : an9 50: .uses @ull OT,2 .oun9ary scan +egistere9 3> cells with in9ii9ually controlle9 cloc"s an9 output ena.lers

7asy to use > ast 9eelopment cycles

,.un9ant interconnect ma"es 9eices 100? routa.le with pin-outs loc"e9 :aria.le-grain logic cell proi9es high-perormance an9 100? logic utili!ation &omprehensie 9esign tools inclu9e ast< eicient :erilog>:%L synthesis

7treme lei.ility

%ensity leels range rom 45<000 to 1;5<000 system gates with 3>s rom 8$ to 16respectiely Supports 6418 @3@s at spee9s o oer 160 M! an9 16-.it counters at oer 00 M!

(erect or a wi9e range o high-spee9 memory applications

igh-spee9 9atacom an9 telecom unctions such as ,TM an9 SB7T>S% interaces :i9eo>imaging>graphics applications inclu9ing 9isplay 9riers an9 image processing Test euipment an9 high-spee9 9ata acuisition

) p,S3& The p,S3&D amily o programma.le 9eices range rom 5<000 to ;5<000 system gatesMem.ers o the p,S3& @amily eature : operation with 50 : 3> compati.ility< an9 areaaila.le in commercial< in9ustrial an9 military temperature gra9es



igh-perormance an9 high-9ensity

%ensities up to ;5<000 system gates with up to 16 3>s ,9ance9 3> capa.ilities

Multi-olt compati.le 3>s or : an9 50 : system interaces (&3 compati.ility with : an9 50 : .uses @ull OT,2 .oun9ary scan +egistere9 3> cells with in9ii9ually controlle9 cloc"s an9 output ena.les

7asy to use > ast 9eelopment cycles

,.un9ant interconnect ma"es 9eices 100? routa.le with pin-outs loc"e9 :aria.le-grain logic cell proi9es high-perormance an9 100? logic utili!ation &omprehensie 9esign tools inclu9e ast< eicient :erilog>:%L synthesis

Lattice Semi @(2,s

1) i&740 @(2, @amily3t allows to create ingenious mo.ile pro9ucts while staying well within the cost< power< si!e an9sche9ule targets i&740 9eices allow instant innoation .y customi!ing solutions .ase9 on o-the-shel chips Ehich means maimum pro9uct 9ierentiation with minimum cost an9 eort

,aila.le in three seriesA Low power #L()< low power with em.e99e9 3( #LM) an9 highperormance #=)

7tremely 7asy to Use

er 0 reerence 9esigns 7aluation "its un9er F/ @ree i&7cu.e$ 9eelopment tool

&ustomi!e Pour %esign ,n9 &ustomi!e it ,gain

@ully programma.le ia 9esign sotware Bon-olatile< single-chip solution uic"ly a99 proprietary eatures to your 9esign

Millions Shipping 7ery Eee"

(roen supply Q one .illion units shippe9 oer 10 years Supporting high olume pro9uction runs

Bee9 3nnoationR Bee9 it nowR

Bo waiting or net generation chipsets Q ree9om rom ,SS( an9 chipsets without ,S3&s (rogramma.le i&740 @(2,s let you innoate instantly

%esigne9 with Mo.ile in Min9



3n9ustryKs lowest cost (L%s suita.le or all pro9uction olumes Q rom thousan9s to millions 3n9ustryGs .roa9est range o 05mm - 04mm pitch *2,s it in space-constraine9 applications (ower as low as $5NE to maimi!e .attery lie

$) Mach= @(2, @amily

The Mach=L is LatticeGs newest instant-on< non-olatile< small ootprint @(2,s that usea9ance9 pac"aging technology to ena.le the lowest cost 9eices The amily eatures the latestin small pac"aging< low power< aggressie cost com.ine9 with ast perormance The Mach=Lamily spans rom 640 to 6/00 LUTs 3t is aaila.le in lower power 7 #1$ core) ersion or &#>$5 : core) ersions

,ma!ingly small pac"ages Eaer leel chip scale pac"ages rom $5 $5 mm to 8 8 mm 05 mm space9 .gas that 9elier maimum 3>< small si!e an9 low cost

Bee9 to .ri9ge M3(3 %S3 or &S3-$R &omplete reerence 9esigns aaila.le Low power an9 small si!es allow use in consumer pro9ucts ,llows .ri9ging to > rom legacy interaces

Maimum &ontrol Minimum *oot-up 3nstant-on 1 ms .oot-up Low oltage core 1$ or choose a single >$5 : power supply ysteresis on inputs proi9es noise immunity with slow signals

*uilt in har9 unctions

Timer counter Two 3$& interaces S(3 interace (rogramma.le scillator

) Lattice7&( @(2, @amilyLattice7&( was 9esigne9 rom the groun9 up to oer the .est o an eicient @(2, with the.eneits o S7+%7S Bee9 (&3e< %M3< &(+3< O7S%$04< 2.7 or =,U3R Bo pro.lem Ehenolumes or perormance reuirements are high< an9 si!e< weight or power is constraine9< theLattice7&( proi9es a perect solution ,aila.le in commercial< in9ustrial< an9 automotieersions

7tremely 7asy to Use er 50 3( cores an9 reerence 9esigns Q most with try .eore you .uyG Q accelerate9eelopment time er 5 7aluation "its starting at F// Simple to use %iamon9 9esign sotware with licenses starting at F//&onnect with System

Up to 16 channels 1$5 2.ps (&3 7press< 7thernet #2.7< =,U3< S2M33)< %M3< SM(T7< Serial +api9 3>< &(+3 an9



O7S%$04,>* 800 M.ps %%+< 1 2.ps L:%S Up to 586 programma.le sys3 .uers

&reate 7traor9inary @unctions Up to 150 "LUTs Up to 68 M.its o S+,M $0 1818 multipliers

ugely 7icient< Surprisingly &ompact Ei9e array o pac"ages as small as 1010 mm (ower consumption rom .elow 05 E

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Different Commercial FPGAs Are