GaN HEMT Devices: Experimental Results on Normally-on, Normally-Off and Cascode

Configuration

Giuseppe Sorrentino, Maurizio Melito, Alfonso Patti STMicroelectronics

IPG R&D Catania

Stradale Primosole, 50

Giovanni Parrino, Angelo Raciti DIEEI Department

University of Catania Catania

Viale Andrea Doria, 6

AbstractPower electronics systems play key function in power management and motion control: power consumption and volume reduction are strongly required in new applications oriented to protect environment. Moreover, a switching frequency increase is demanded for microwave and power switching applications, thus reducing passive component and converter volume: however, increasing the switching frequency directly increases switching losses. Also, switching applications are very demanding, because semiconductor switches are required to withstand high voltage in reverse condition and handle large current in forward operation mode. New material and new devices are studied to satisfy such requirements, like SiC and GaN devices. In this work, several 600-V class GaN-on-Si HEMT prototypes are presented. These devices have been designed and developed for power switching converter applications. In order to offer a complete scenario of GaN-on-Si HEMT technology, normally-on, normally-off, and cascode-connected devices have been characterized. Achieved experimental results of static and pulsed measurements are then shown.

I INTRODUCTION Microelectronics today is dominated by silicon. Silicon (Si) power transistors performances have been dramatically improved thanks to technological improvements, but they have almost reached their theoretical limit. In order to overcome the silicon limits, new structures are designed to improve the device performance, such as MOSFET superjunction [1]. However, also these devices are limited in terms of performances respect to the higher performance required (energy saving, cost, size, etc). Hence, new materials have been studied like silicon carbide (SiC) and gallium nitride (GaN) to achieve further advances in power device performance [2]. Thanks to SiC and GaN intrinsic superior physical properties, silicon has reached the end of the road for power electronic devices. Gallium nitride high bandgap energy, high saturation velocity, and high electrical strength are only some of the main reasons for GaN success. Gallium nitride semiconductor devices are then emerging nowadays as attractive candidates in high power applications for carrying large currents and supporting high voltages, while providing very low on-resistance, low device capacitances and fast switching times [3]. GaN bandgap energy, Eg 3.4 eV, is more than three times higher than that of Si (Eg = 1.1 eV). The very large energy bandgap, i.e. the energy required to

ionize atoms and create free electrons, is a fundamental property of GaN, making it extremely attractive for high-power and high-temperature applications; GaN energy bandgap is so large that the material is transparent. Moreover, high charge carrier mobility and high saturation velocity are attractive for high current and high frequency operation in a semiconductor device. Since the probability of intrinsic carrier generation and many other properties depend exponentially on the bandgap energy, a large bandgap is the key factor for high temperature operation and chemical inertness. High bandgap energy also leads to high intrinsic electric breakdown field Ec, 3 MV/cm, ten times higher than that of Si (0.3 MV/cm), thus allowing higher breakdown voltage of GaN devices. As a consequence, GaN high breakdown strength requires thinner layers for a given blocking voltage, thereby reducing the specific on-resistance. High temperature operation with negligible leakage current is also available thanks to GaN large bond energy, reducing cooling requirements. Most important GaN material properties are resumed in table 1 and compared to that of silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC) [4].

Material properties Si (111) GaAs SiC GaN

Eg (eV) 1.1 1.43 2.86 3.39

Ec (MV/cm) 0.3 0.45 2.0 3.33

r 11.9 13.1 9.8 9

(cm2/Vs) 1350 8500 650 1200

vs (107 cm/s) 1 2 2 2.5 Table 1. Important material properties of main used semiconductor materials In order to make a comparison between the possible high-power and high-frequency theoretical performances for different semiconductor materials, several figures-of-merit (FOMs) have been proposed in table 2. These FOMs take into account the most relevant material properties with respect to high-power and high-frequency applications, giving as result a number that roughly expresses material performance possibilities.

978-1-4799-0224-8/13/$31.00 2013 IEEE 816

Table 2. Normalized figures of merit (FOMs) of some materials. Johnsons figure of merit (JFOM) combines the breakdown voltage and saturated electron drift velocity to define a value for high-frequency handling capability. Baligas figures of merit (BFOM and BHFFOM) for low and high frequency give a value based on the relative permittivity, electron mobility, and electric breakdown field, thus resulting as a measure for high-power handling capability. A device chip area figure-of-merit (HCAFOM) has also been proposed: the larger this FOM value, the smaller the chip area needed for similar operation conditions [5].

II GaN-on-Si HEMT

The most famous GaN-based heterostructures are the AlGaN/GaN HEMTs (High Electron Mobility Transistors) or HFETs (hetero-structure field effect transistor): in these structures, a two-dimensional electron gas (2DEG) is formed at the interface between the AlGaN barrier layer and the GaN channel/buffer layer, having a high mobility and large carrier concentration without any doping. The main advantage of a 2DEG channel is then the possibility of increasing device conductivity by increasing the carrier concentration without suffering the mobility degradation effects due to impurity scattering caused by doping [6]. Hence, GaN technology allows to realize higher power density transistors than traditional Si MOSFETs, resulting in smaller devices and therefore smaller absolute gate and drain capacitance values, important parameters for switching performances. However, trapping effects are the main issue to overcome in HEMT device operation: surface and deep buffer traps reduce device performance, thus leading to more consuming and slower HEMTs. Furthermore, many leakage and degradation mechanisms can coexist during device operation [7]. Several materials are available to act as substrate for GaN epitaxial growth, e.g. sapphire, GaN, SiC, and Si. Despite the lattice mismatch between Si and GaN affects quality and flatness of GaN-on-Si wafers, silicon today is considered the best choice since costs of Si substrates and available equipments of existing silicon foundries play a paramount role. GaN-on-Si technology is then able to offer a reasonable market in terms of cost/performance ratio and is rising as the best solution in order to realize new generation electronic devices for power switching applications. Hence, thanks to its large advantages in performances and cost, GaN-on-Si will most likely become the dominant technology over the next decade. Epitaxial structure of characterized devices is shown in fig. 1. GaN HEMTs are normally-on (depletion-mode or d-mode) devices because of spontaneous polarization at the AlGaN/GaN interface: since AlGaN bandgap is larger than that of GaN, at AlGaN/GaN interface energy of conduction band drops below Fermi level thus allowing a potential well to forms very close to interface in the material at lower bandgap as shown in figure 2. However, normally-off (enhancement-mode or e-mode) devices are preferred in power switching applications thanks to their fail-safe nature, circuit complexity and system cost reduction. Several techniques to

produce e-mode GaN HEMTs exist, but each approach has its own drawbacks.

Fig.1 Epitaxial structure of characterized GaN-on-Si HEMT devices

A traditional MOSFET in silicon, can also be used in cascode connection with a normally-on GaN HEMT to achieve a positive threshold voltage, but then device performance is limited by the silicon transistor [8].

Fig. 2 Band diagram of a conventional normally-on AlGaN/GaN HEMT at zero gate voltage (left) and at negative gate voltage applied VGS < VTH < 0 V (right)

III Experimental results

Main purpose of this work is to offer an overview about GaN-on-Si HEMT technology for 600V-class devices in TO-220 package: according to this aim, normally-on, normally-off, and cascode-connected devices by STMicroelectronics have been characterized. Figure 3 shows achieved breakdown voltage (BV) for characterized 40mm normally-off device: avalanche injection phenomenon is clearly visible at BV = 1000 V.

Fig.3 Drain leakage current of a characterized 40mm normally-off devices,

showing achieved breakdown voltage BV = 1000 V Depletion-mode devices with 8mm and 25mm perimeter (active area A = 0.184 mm2 and A = 0.575 mm2, respectively) have been characterized; recessed-gate 20mm (A = 0.460 mm2), 40mm (A = 0.920 mm2) and 80mm (A = 1.840 mm2) enhancement-mode devices have also been analyzed. Cascode-connected devices have the same 8 and 25mm normally-on devices in series with a low-

FOMs Si (111) GaAs SiC GaN

JFOM = Ec vsat /2 1 7.1 260 760

BFOM = Ec3 1 15.6 110 650

BHFFOM = Ec2 1 10.8 16.9 77.8

HCAFOM = 1/2 Ec2 1 4.9 25.7 61.7

817

voltage MOSFET by STMicroelectronics. Breakdown voltages of characterized devices are listed in table 3. Low breakdown voltage values in cascode-connected devices are probably due to the poor cascode internal connection and overheating problems. Output characteristic curves ID vs. VDS for each analyzed devices are presented in figures from 4.1 to 4.6. In normally-on devices (figures 4.1 and 4.2), gate voltage VGS sweeps from -5 V to +3 V.

Fig.4.1 Output characteristics for 8mm Normally-On

Fig.4.2 Output characteristics for 25mm Normally-On

Fig.4.3 Output characteristics for 20mm Normally-On

For normally-off GaN HEMTs VGS sweeps from -2V to 2V (figure 4.3 and 4.4); thanks to MOSFET capability, gate voltage in cascode devices is VGS = [0, + 10 V], (figure 4.5 and 4.6). On-resistance RDS (on) and specific on-resistance RDS (on)A values of characterized devices are listed in table 3. High on-resistance values for cascode devices is due to high RDS (on) value of series-connected MOSFET.

Fig.4.4 Output characteristics for 80mm Normally-Off

Fig.4.5 Output characteristics for 8 mm cascode

Fig.4.6 Output characteristics for 25 mm cascode

818

Typical static figure-of-merit for power switching transistors involves specific on-resistance and breakdown voltage: BV2/RDS (on)A (GW/cm2), where a higher value indicates lower static losses and higher breakdown voltage. This FOM shows how increasing breakdown voltage affects device performances: a high BV can then be achieved by increasing gate-to-drain distance or buffer thickness, or by inserting gate insulators. However, these solutions also increase on-resistance, thus leading to slower and more consuming devices. Table 3 shows also achieved static FOM values for characterized devices; due to low breakdown voltage values in cascode devices, a very low BV2/RDS (on)A value has been achieved.

Device RDSon () A

(mm2) RDSon *A (mcm2)

BV (V)

BV2/RDSon* A (GW/cm2)

8mm D-mode 2.25 0.184 4.14 1100 0.292

25mm D-mode 0.77 0.575 4.42 700 0.111

20 mm E-mode 0.98 0.460 4.50 750 0.125

40mm E-mode 0.44 0.920 4.04 1000 0.248

80mm E-mode 0.28 1.840 5.15 750 0.109

8mm Cascode 4.60 0.184 8.46 380 0.017

25mm Cascode 1.62 0.575 9.31 420 0.019

Table 3. On-resistance and specific on-resistance values for characterized devices. Breakdown voltage and static FOM BV2/RDS (on) A values are also listed. Capacitances vs. drain-source voltage (C-V) measurements are often used in device characterization because they provide useful information about dynamic transistor behavior and switching losses. Input capacitance Ciss = Cgs + Cgd has been evaluated by shortening in AC drain and source and sweeping DC drain-source voltage VDS from 0 V up to 400 V; in a similar way, output capacitance Coss = Cds + Cgd has been measured with gate and source electrodes shorted in AC and increasing DC drain voltage in the same range. Lastly, reverse transfer capacitance Crss = Cgd, also termed as Miller capacitance, is measured: this is a critical non-linear parameter because it provides a feedback loop between circuit output and input.

Fig.5.1 Capacitance versus VDS 8 mm Normall-On

In order to evaluate switching performances for characterized devices, capacitance versus drain voltage curves are shown in figures from 5.1 to 5.5. Because of parasitic contribute, capacitance values do not scale with area ratio; moreover, reverse transfer capacitance low value is almost constant for all characterized devices (Crss3pF) due to measurement tool intrinsic errors. C-V curves for cascode devices have not been evaluated because they refer to GaN HEMT and to Si MOSFET together.

Fig.5.2 Capacitance versus VDS 25 mm Normall-Off

Fig.5.3 Capacitance versus VDS 20 mm Normall-Off

Fig.5.4 Capacitance versus VDS 40mm Normall-Off

819

Fig.5.5 Capacitance versus VDS 80mm Normall-Off

Switching times for power-electronics applications are determined by charge and discharge times of the gate-drain capacitance Cgd, due to the Miller effect. Therefore, switching frequency depends not only on the device structure but also on the gate driving current, which in turn depends on external gate resistance in the gate-drive circuit. Gate charge Qg is then used to discuss switching time and losses. Indeed, gate charge is defined as the charge that must be supplied to the gate to achieve full switching and depends only on device parasitic capacitances [9]. However, due to extremely low parasitic capacitance value in GaN-on-Si HEMTs, a gate charge experimental measurement setup is difficult to design because of parasitic components in polarization circuit. A theoretical method has been proposed [10]: C-V measurement results can be used to determine gate-charge values by using the fundamental equation 1.

Q = I dt = C dV (1)

According to the author, Qg and Qgd values can then be easily extracted by capacitance values. Typically, in gate charge measurements for 600V-class HEMT devices, maximum drain-source voltage VDS (max) = 80% BV = 480 V. On the other hand, VGS (min) and VGS (max) are determined by gate voltage operating range; in this case, VGS (min)= -5 V and VGS (max)=3V for normally-on and normally-off devices. In cascode-connected devices, Ciss and Crss values refer to GaN-HEMT and Si-MOSFET together, hence gate charge value is not relevant. Table 4 shows experimental capacitance values and theoretical gate charge values; furthermore, two dynamic figures-of-merit (FOMs) are calculated to evaluate theoretical GaN HEMTs switching performances. Achieved FOMs results are also compared to a 600V class superjunction Si MOSFET [STP13NM60N]: thanks to low parasitic capacitances, lower RDS (on)Qg and lower RDS (on)Qgd values have been obtained, thus showing better switching performances for GaN HEMTs. In 8mm normally-on characterized device, metal connections and parasitic capacitances make these FOM values higher than expected. Different pulse widths and quiescent points for VGS and VDS have been applied, as they strongly affect device performance due to current collapse phenomena as showed in figures 6.1 6.5. In this work, for all characterized devices, applied pulses were 500 ns long and duty cycle was 0.1% [11]. Gate and drain lag measurements in ID vs. VDS charts for same VGS and different quiescent points allows a trapping-induced dispersion characterization: trapped charge is not available for conduction, hence the maximum drain current is reduced and the device is slower, leading to a larger RDS (on). Due

to temperature dependency of trapping mechanism, self-heating effect has to be made negligible by using a heat sink.

Device CISS (pF) COSS (pF)

CRSS (pF)

Qg (nC)

Qgd (nC)

RDSon *Qg

(nC)

RDSon *Qgd

(nC) 8mm D-mode 27.8 17.4 3.4 1.73 1.4 3.9 3.2

25mm D-mode 63.4 24.2 3.0 2.07 1.4 1.6 1.1

20 mm E-mode 49.3 24.0 2.2 1.58 1.4 1.5 1.4

40mm E-mode 91.6 41.2 3.8 2.07 1.4 0.9 0.6

80mm E-mode 179.8 72.3 2.8 2.27 1.4 0.6 0.4

STP13NM60N 790 60.0 3.6 27.0 14 7.6 3.9 Tab.4 Capacitance and gate charge values

Fig.6.1 Pulsed Id vs. VDS 8mm Normally-On

Pulsed IV measurements in 40mm and 80mm normally-off devices have not been accomplished because of maximum drain current (10A) limitation in Auriga Microwave AU4750 Pulsed IV/RF System.

Fig.6.2 Pulsed Id vs. VDS 25mm Normally-On

Drain current reduction ( 31%) in gate lag measurements occurs in all characterized devices: trapped charges under gate contact make 2DEG density smaller, hence ID is reduced because of gate junction direct polarization. On the contrary, in drain lag measurements ID (max) is larger than in normal device condition (VGSq = 0 V, VDSq = 0 V): this effect might be due to trapped

820

charge density reduction under gate contact. Indeed, drain voltage act as a negative gate voltage with respect to traps discharge under the gate contact.

Fig.6.3 pulsed Id vs. VDS 20mm Normally-Off

Fig.6.4 Pulsed Id vs. VDS 8mm cascode

Fig.6.5 Pulsed Id vs. VDS 25 mm cascode

CONCLUSION GaN semiconductor devices are emerging nowadays as attractive candidates in high power applications for carrying large currents and supporting high voltages, while providing very low on-resistance, low device capacitances, and fast switching times. GaN-on-Si technology is rising as the best solution in order to realize new generation electronic devices for power switching applications. Indeed, thanks to its large advantages in performances and cost, GaN-on-Si will most likely become the dominant technology over the next decade. In this work, 600V-class GaN-on-Si HEMTs have been characterized: normally-on, normally-off, and cascode-connected GaN-HEMTs have been analyzed. Thanks to achieved good results (low on-resistance, high breakdown voltage, and very low drain leakage current), this overview on first generation of 600-V GaN-on-Si HEMTs shows promising results, in order to realize better and better switching devices beyond Si and SiC theoretical limits.

REFERENCES

[1] G. Sorrentino, M. Melito, A. Raciti, SiC Diodes and MDMesh 2nd Generation Devices Improve Efficiency in PFC Applications, CIPS 06, pp. 1-5, 2006.

[2] Kaplar R. J., M. J. Marinella, S. DasGupta, M. A. Smith, S. Atcitty, Characterization and Reliability of SiC- and GaN-Based Power Transistors for Renewable Energy Applications, IEEE Energy Tech 2012, pp. 1-6, 2012.

[3] Limiti E., Colangeli S., Bentini A., Nanni A., Characterization and Modeling of Low Cost, High-Performance GaN-on-Si Technology, MIKON 2012, 19th International Conference on Microwaves, Radar and Wireless Communications, Warsaw, Poland, pp. 599-605, 2012.

[4] Wang H., Wang F., Zhang J., Power Semiconductor Device Figure of Merit for High-Power-Density Converter Design Applications, IEEE Transactions on Electron Devices, vol. 55, no.1, pp. 466-470, 2008.

[5] McCune E., Process- and technology-independent power switching transistor figures of merit, Radio and Wireless Symposium (RWS), pp. 195-198, 2008.

[6] Ikeda N., Niiyama Y., Kambayashi H., Sato Y., Nomura T., Kato S., Yoshida S., GaN Power Transistors on Si Substrates for Switching Applications, Proceedings of the IEEE, vol. 98, no. 7, pp. 1151-1160, 2010.

[7] Meneghesso G., Verzellesi S., Danesin F., Rampazzo F., Zanon F., Tazzoli A., Meneghini M., Zanoni E., Reliability of GaN High Electron Mobility Transistors: State- of- the- art and Perspectives, IEEE Transactions on Device and Materials Reliability, vol. 8, no. 2, pp. 332-341, 2008.

[8] Saito W., Saito Y., Fujimoto H., Yoshioka A., Ohno T., Naka T., Sugiyama T., Switching Controllability of High Voltage GaN-HEMTs and the Cascode Connection, Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, pp. 229-232, 2012

[9] Saito W., Nitta T., Kakiuchi Y., Saito Y., Tsuda K., Omura I., Yamaguchi M., Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure, IEEE Transactions on Electron Devices, vol. 54, no. 8, pp. 1825-1830, 2007

[10] Krishnamurthy V., Gyure A., Francis P., Simple Gate Charge (Qg) Measurement Technique for On-Wafer Statistical Monitoring and Modeling of Power Semiconductor Devices, International Conference on Microelectronics Test Structures, Santa Clara, CA, pp. 98-100, 2012

[11] Jin D., del Alamo J. A., Mechanisms responsible for dynamic ON-resistance in GaN high - voltage HEMTs, Proceedings of the 2012 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, pp. 333-336, 2012

821

Powered by TCPDF (www.tcpdf.org)