Monolithic and Vertically Integrated Pixel Detectors,CERN, 25th November 2008

CMOS Monolithic Active Pixel Sensors

R. TurchettaCMOS Sensor Design Group

Rutherford Appleton Laboratory, Oxfordshire, UK

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CMOS Image Sensors @ RAL

The INMAPS process and its

silicon proof

Conclusions

Outline

Overall view

CMOS image sensor activity started in 1998 (aka Monolithic Active Pixel Sensor; MAPS)

1st tape-out in 2000: test structures for the Star-Tracker in 0.5 and 0.7 m

1st full-scale sensor submitted in May 2001: the Star-Tracker in 0.5 m

Use of technologies down to 0.18 m

Use of CIS (CMOS Image Sensors) technologies

Patented, silicon-proofed INMAPS technologyfor high-end sensors

Pixel size from 2 m upwards

Large pixels IPs

4T pixel Ips

Low noise pixel IPs

Wafer-scale (200mm) sensor capability

Over 40 years of cumulateddesign experience

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The Large Area Sensor (LAS)

Sensors of different

sizes on the same

200mm wafer

0.35 m CMOS

Basic unit 270x270

pixels

X5 1350x1350

X2 540x540

X1 270x270

Wafer-scale possible

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Region of Reset readout

No ROR

Image of a laser point

ROR readoutTint0 = 80, Tint1 = 30, Tint2 = 1

>140dB

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NMOS

P-Well N-Well P-Well

N+ N+

P-substrate (~100s m thick)

N+ N+

N-Well

P+ P+

Diode NMOS PMOS100 %

efficiency

only NMOS

in pixel no

complicated

electronics

Complicated

electronics

NMOS

and

PMOS,i.e.

CMOS low

efficiency

How much CMOS in a CMOS sensor?

NMOS

P-Well N-Well P-Well

N+ N+

P-substrate (~100s m thick)

N+ N+

N-Well

P+ P+

Diode NMOS PMOS

The INMAPS process

Deep P-Well

Standard CMOS with additional deep P-well implant. Quadruple well technology.

100% efficiency and CMOS electronics in the pixel.

Optimise charge collection and readout electronics separately!

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8 INMAPSProof of principle

• Alternative to CALICE Si/W analogue ECAL

• No specific detector concept

• “Swap-in” solution leaving mechanical design unchanged

Tungsten1.4 mm

PCB~0.8 mm

Embedded VFE ASIC

Silicon sensor0.3mm

Diode pad calorimeter MAPS calorimeter

• preShape• Gain 94uV/e• Noise 23e-• Power 8.9uW

• 150ns “hit” pulse wired to row logic

• Shaped pulses return to baseline

Pixel Architectures

preSample• Gain 440uV/e• Noise 22e-• Power 9.7uW

• 150ns “hit” pulse wired to row logic

• Per-pixel self-reset logic 9

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• preShape Pixel• 4 diodes• 160 transistors• 27 unit capacitors• 1 resistor (4Mohm)

• Configuration SRAM– Mask– Comparator trim (4 bits)

• 2 variants: subtle changes to capacitors

Pixel Layouts

preSample Pixel• 4 diodes• 189 transistors• 34 unit capacitors

• Configuration SRAM– Mask– Comparator trim (4 bits)

• 2 variants: subtle changes to capacitors

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Deep p-well

Circuit N-Wells

Diodes

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• 8.2 million transistors• 28224 pixels; 50 microns; 4 variants• Sensitive area 79.4mm2

– of which 11.1% “dead” (logic)

Test Chip Architecture

• Four columns of logic + SRAM– Logic columns serve 42 pixels– Record hit locations & timestamps– Local SRAM

• Data readout– Slow (<5Mhz)– Current sense amplifiers– Column multiplex– 30 bit parallel data output

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Sensor Testing: Overview

Test pixels• preSample pixel variant• Analog output nodes• Fe55 stimulus• IR laser stimulus

Single pixel in array• Per pixel masks• Fe55 stimulus• Laser Stimulus

Full pixel array• preShape (quad0/1)• Pedestals & trim adjustment• Gain uniformity• Crosstalk• Beam test

quad0

quad1

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Charge collection

• Amplitude results

• With/without deep pwell

• Compare

• Simulations “GDS”

• Measurements “Real”

(pixels with full electronics)

F

B

Pixel profiles

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55Fe Source

•55Fe gives 5.9keV photon• Deposits all energy in “point” in silicon; 1640e−

• Sometimes will deposit maximum energy in a single diode and no charge will diffuse

absolute calibration! •Binary readout from pixel array

• Need to differentiate distribution to get signal peak in threshold units (TU)• Differential approximation

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CMOS Active Pixel Sensors are mature for high-end applications

Cost-effective solution for large-scale experiments

Low noise (< 10 e- rms)

Large area: up to 200mm wafer-scale

INMAPS process allows complex in-pixel architectures without degrading

the detection performance

Evaluating possibility of offering access to the INMAPS process to the

community

Conclusions

Acknowledgements

For the Large Area Sensor (work carried out under the MI-3 Multidimensional

Integrated Intelligent Imaging Consortium)

A.T. Clark, N. Guerrini, J.P. Crooks, T. Pickering (Rutherford Appleton Laboratory)

N. Allinson (University of Sheffield)

S.E. Bohndiek (University College London)

For the CALICE-MAPS:

J.P. Crooks, R. Coath, M. Stanitzki, K.D. Stefanov, M. Tyndel, E.G. Villani

(Rutherford Appleton Laboratory)

J.A. Ballin, P.D.Dauncey, A.-M. Magnan, M. Noy (Imperial College

London)

Y. Mikami, N.K. Watson, O. Miller, V. Rajovic, J.A. Wilson (University of

Birmingham)

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