Upload
shen
View
50
Download
4
Embed Size (px)
DESCRIPTION
NSNI – 2010, Mumbai, India. Development of high speed waveform sampling ASICs. Stefan Ritt - Paul Scherrer Institute, Switzerland. Question …. 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ (700kRs). 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ (50kRs) USB Power. - PowerPoint PPT Presentation
Citation preview
Development of high speed waveform sampling ASICs
Stefan Ritt - Paul Scherrer Institute, Switzerland
NSNI – 2010, Mumbai, India
Feb. 25th, 2010 NSNI-2010 Mumbai 2
Question …
4 channels5 GSPS1 GHz BW8 bit (6-7)15k$ (700kRs)
4 channels5 GSPS1 GHz BW8 bit (6-7)15k$ (700kRs)
4 channels5 GSPS1 GHz BW11.5 bits1k$ (50kRs)USB Power
4 channels5 GSPS1 GHz BW11.5 bits1k$ (50kRs)USB Power
Feb. 25th, 2010 NSNI-2010 Mumbai 3
Switched Capacitor Array
Shift RegisterClock
IN
Out
“Time stretcher” GHz MHz“Time stretcher” GHz MHz
Waveform stored
Inverter “Domino” ring chain0.2-2 ns
FADC 33 MHz
Feb. 25th, 2010 NSNI-2010 Mumbai 4
Switched Capacitor Array
•Cons
• No continuous acquisition
• Limited sampling depth
• Nonlinear timing
•Pros
• High speed (up to 5 GSPS) high resolution (13 bit SNR)
• High channel density (16 channels on 5x5 mm2)
• Low power (10-40 mW / channel)
• Low cost (~ 10$ / channel)
t t t t t
Goal: Minimize Limitations
Feb. 25th, 2010 NSNI-2010 Mumbai 5
• CMOS process (typically 0.35 … 0.13 m) sampling speed
• Number of channels, sampling depth, differential input
• PLL for frequency stabilization
• Input buffer or passive input
• Analog output or (Wilkinson) ADC
• Internal trigger
Design Options
PLL
ADC
Trigger
Write CircuitryHow to sample the input signal
Feb. 25th, 2010 NSNI-2010 Mumbai 7
Simple inverter chain
1 0 0 0 0 0
0 0 0 0 00
1 0
0 0 0 0 00
1
0
10 0 0
1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1 1
11
1 0 0 0 0 0
0 0 0 0 00
0
0 0 0 0 00
0
0 0 0
1
1
1
0 0 00
0 0 0 0
0 0 0 0
00
0 0 0 0 00
00
Feb. 25th, 2010 NSNI-2010 Mumbai 8
Design of Inverter Chain
PMOS > NMOS
PMOS < NMOS
Feb. 25th, 2010 NSNI-2010 Mumbai 9
“Tail Biting”
enable
1 2 3 4
1
2
3
4
speed
Feb. 25th, 2010 NSNI-2010 Mumbai 10
Phase Locked Loop
On-chip PLL can lock sampling frequency to external reference clock
T Q
PhaseComparator
ExternalReference
Clock
Inverter Chain
loopfilter
down
1
2
sampling speed control
PLLup
Feb. 25th, 2010 NSNI-2010 Mumbai 11
Timing jitter
t1 t2 t3 t4 t5
• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”
• “Differential temporal nonlinearity” TDi= ti – tnominal
• “Integral temporal nonlinearity”TIi = ti – itnominal
• “Random aperture jitter” = variation of ti between measurements
• Inverter chain has transistor variations ti between samples differ “Fixed pattern aperture jitter”
• “Differential temporal nonlinearity” TDi= ti – tnominal
• “Integral temporal nonlinearity”TIi = ti – itnominal
• “Random aperture jitter” = variation of ti between measurements
TD1 TI5
Feb. 25th, 2010 NSNI-2010 Mumbai 12
Fixed jitter calibration
• Fixed jitter is constant over time, can be measured and corrected for
• Several methods are commonly used
• Most use sine wave with random phase and correct for TDi on a statistical basis
• Fixed jitter is constant over time, can be measured and corrected for
• Several methods are commonly used
• Most use sine wave with random phase and correct for TDi on a statistical basis
Feb. 25th, 2010 NSNI-2010 Mumbai 13
Fixed Pattern Jitter Results
• TDi typically ~50 ps RMS @ 5 GHz
• TIi goes up to ~600 ps
• Jitter is mostly constant over time, measured and corrected
• Residual random jitter 3-4 ps RMS
Feb. 25th, 2010 NSNI-2010 Mumbai 14
Achievable Timing Resolution
After proper timing calibration, a “split pulse timing accuracy” of typically~10 ps can be chieved
D. BretonPicosecond WorkshopClermont-Ferrand, Jan 2010
D. BretonPicosecond WorkshopClermont-Ferrand, Jan 2010
Feb. 25th, 2010 NSNI-2010 Mumbai 15
What determines the BW?
• The analog bandwidth is given by the parasitic capacitance of the input bus and the input impedance
• Typically 20fF/cell+20pF (bus), 2-3 for bond wire 1 GHz BW
• An active input buffer does not really help
20 fF
20 pFBond wire2-3
GHzRC
f dB 8.12
13
“The best buffer is no buffer” – G. Varner
“The best buffer is no buffer” – G. Varner
Feb. 25th, 2010 NSNI-2010 Mumbai 16
Cascaded Switched Capacitor Array
• Combines the advantage of a short input stage (32 cells) with a deep secondary sampling stage (32x32 cells)
• Estimated input BW:5 GHz
• Sampling speed:10 GSPS (130 nm)
• 100 ps sample time –3.1 ns hold time
• Matches BW of fastestdetectors (G-APD, MCP-PMT)
next generation of SCAs
shift registerinput
fast sampling stage secondary sampling stage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Readout Circuitry
How to read out sampled waveforms
Feb. 25th, 2010 NSNI-2010 Mumbai 18
Analog Readout Methods
write
read
C
. . .
R(700 )I
Uin
write
C
Uin
“DifferentialPair”
Ib
Vout
Ib/2Ib/2
+-
read
write
C (200fF)
Uin
read
I ~ kT
Feb. 25th, 2010 NSNI-2010 Mumbai 19
Digital Readout
Wilkinson-type ADC requires only one comparator per sampling cell
12-b
it co
unte
r
+
-
+
-
latc
h
DAC latc
h
ramp voltage
comparator comparator
ASIC
FPGA
Feb. 25th, 2010 NSNI-2010 Mumbai 20
How to minimize dead time ?
• Fast analog readout: 30 ns / sample
• Parallel readout
• Region-of-interestreadout
• Simultaneouswrite / read
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
STOP SHIFT REGISTER
READ SHIFT REGISTER
W SRO UT
CO NFIG REGISTER
RSRLO AD
DENABLE
W SRIN
DW RITE
DSPEED PLLO UT
DO MINO WAVE CIRCUIT
PLL
AGND
DG ND
AVDD
DVDD
DTAPREFCLKPLLLCK A0 A1 A2 A3
EN
AB
LE
OU T0
OU T1
OU T2
OU T3
OU T4
OU T5
OU T6
OU T7
OU T8/MUXOUT
BIASO-O FS
RO FSSROUT
RESETSRCLK
SRIN
F U N C T IO N A L B L O C K D IA G R A M
MUX
WR
ITE
SH
IFT
RE
GIS
TE
R
WR
ITE
CO
NF
IG R
EG
IST
ER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
MUX
LVDS
AD922212 bit
8 channels
DRS4DRS4
Feb. 25th, 2010 NSNI-2010 Mumbai 21
DRS4 ROI readout mode
readout shift register
Triggerstop
normal trigger stop after latency
Delay
delayed trigger stop
Patent pending!
33 MHz
e.g. 100 samples @ 33 MHz 3 us dead time
300,000 events / sec.
e.g. 100 samples @ 33 MHz 3 us dead time
300,000 events / sec.
Feb. 25th, 2010 NSNI-2010 Mumbai 22
Simultaneous Write/Read
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
0
FPGA
0
0
0
0
0
0
0
1 Channel 0
Channel 11
Channel 0 readout
8-foldanalog multi-event
buffer
Channel 21
Channel 10
Expected crosstalk ~few mVExpected crosstalk ~few mV
Feb. 25th, 2010 NSNI-2010 Mumbai 23
Current SCA ASICs
Chip family SAM [1] LAB [2] DRS [3] Anusmriti
[4]
Max. sampling speed
2.5 GSPS 3.7 GSPS 6 GSPS 0.5 GSPS
Analog Bandwidth 300 MHz 900 MHz 950 MHz ?
Number of channels
2 1-16 9 1
SNR 13.4 bits 10 bits 11.4 bits ?
Sampling depth 144-2520 256-64k 1025-8192 128
Readout time 650 s 150 s – 10ms
30 ns * nsamples 128 s
Input Buffers YES YES NO YES
Internal PLL YES NO YES YES
ADC External Internal External External
Power/channel 150-500 mW
15-50 mW 14-45 mW 400 mW[1] E. Delagnes, D. Breton et al., NIM A567 (2006) 21[2] G. Varner et al., NIM A583 (2007) 447[3] S. Ritt, NIM A518 (2004) and http://drs.web.psi.ch[4] M. Sukhwani et al., NSNI 2010
Advanced Topics
Triggering, Channel Cascading, Waveform Analysis
Feb. 25th, 2010 NSNI-2010 Mumbai 25
How to measure best timing?
Simulation of MCP with realistic noise and different discriminatorsSimulation of MCP with realistic noise and different discriminators
J.-F. Genat et al., arXiv:0810.5590 (2008)
Feb. 25th, 2010 NSNI-2010 Mumbai 26
Flash ADC Technique
60 MHz12 bit
Q-sensitivePreamplifierPMT/APD
WireShaper
• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is “fast” enough• All operations (CFD, optimal filtering, integration) can be done digitally
• Shaper is used to optimize signals for “slow” 60 MHz FADC• Shaping stage can only remove information from the signal• Shaping is unnecessary if FADC is “fast” enough• All operations (CFD, optimal filtering, integration) can be done digitally
FADC
TDC
“Fast”12 bit
TransimpedancePreamplifier FADC
PMT/APDWire
DigitalProcessing
Amplitude
Time
BaselineRestoration
Feb. 25th, 2010 NSNI-2010 Mumbai 27
How fast is “fast”
• Nyquist-Shannon: Sampling rate must be 2x the highest frequency coming from detector
• Analog Bandwidth must match signal from detector
• Fastest pulses coming from Micro-Channel-Plate PMTs
3mpores
Feb. 25th, 2010 NSNI-2010 Mumbai 28
Fastest pulses
• MCP-PMTs: 70 ps rise time 4-5 GHz BW 10 GSPS
• Cable should not limit bandwidth Put digitizer onto detector
• Higher sampling speed only improves statistics
J. Milnes, J. Howoth, Photek
shift registerinput
fast sampling stage secondary sampling stage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aimed parameters:5 GHz Bandwidth10 GSPS Sampling Rate
Aimed parameters:5 GHz Bandwidth10 GSPS Sampling Rate
10 GSPS
30 GSPS
Feb. 25th, 2010 NSNI-2010 Mumbai 29
Trigger and DAQ on same board
• All SCA applications need some kind of trigger split signals
• Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS
• FPGA can make local trigger(or global one) and stop DRSupon a trigger
• DRS readout (5 GSPS)though same 8-channel FADCs
an
alo
g fro
nt e
nd
DRSFADC12 bit
65 MHz
MU
X FPGA
trigger
LVDS
SRAM
DRS4
glo
bal tr
igger
bu
s
“Free” local trigger capability without additional hardware
“Free” local trigger capability without additional hardware
Feb. 25th, 2010 NSNI-2010 Mumbai 30
Daisy-chaining of channels
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Domino Wave
1
clock
0
1
0
1
0
1
0
enableinput
enableinput
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Domino Wave
1
clock
0
1
0
1
0
1
0
enableinput
enableinput
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling
depth
DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cellsChip daisy-chaining possible to reach virtually unlimited sampling
depth
Feb. 25th, 2010 NSNI-2010 Mumbai 31
Interleaved samplingdela
ys
(167p
s/8 =
21ps)
G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)
6 GSPS * 8 = 48 GSPS
Possible if delay is implemented on PCBPossible if delay is implemented on PCB
Feb. 25th, 2010 NSNI-2010 Mumbai 32
On-line waveform display
click
templatefit
pedestalhisto
848PMTs
“virtual oscilloscope”“virtual oscilloscope”
Feb. 25th, 2010 NSNI-2010 Mumbai 33
Pulse shape discrimination
)tt[...]θ.. )tθ(td)/τt(te
/τ)t(te i/τ)t(t
eAV(t)r00
000
CsB
Leading edge Decay time AC-coupling Reflections
Example: / source in liquid xenon detector (or: /p in air shower)Example: / source in liquid xenon detector (or: /p in air shower)
Feb. 25th, 2010 NSNI-2010 Mumbai 34
-distribution
= 21 ns
= 34 ns
Waveforms can be clearly
distinguished
= 21 ns
= 34 ns
Waveforms can be clearly
distinguished
Feb. 25th, 2010 NSNI-2010 Mumbai 35
Template Fit
• Determine “standard” PMT pulse by averaging over many events “Template”
• Find hit in waveform
• Shift (“TDC”) and scale (“ADC”)template to hit
• Minimize 2
• Compare fit with waveform
• Repeat if above threshold
• Store ADC & TDC values
Experiment500 MHz sampling
Pile-up can be detected if two hits are separated in time by ~rise time of signal
Pile-up can be detected if two hits are separated in time by ~rise time of signal
Feb. 25th, 2010 NSNI-2010 Mumbai 36
Do we still need crates?
• An empty crate slot costs ~1k$ (crate, interface/computer, cooling)
• Crate topologies requires long cables Reduction of bandwidth
• Alternative: Put electronics on detectors
MEG 3000 channelsMEG 3000 channels
G. VarnerBelle-TOF
G. VarnerBelle-TOF cPCI
H. FriedrichWaveDREAMPSI/ETHZ
H. FriedrichWaveDREAMPSI/ETHZ
GBitEthernet
Feb. 25th, 2010 NSNI-2010 Mumbai 37
Experiments using SCA ASCIs
MAGIC-IIMAGIC-IIMEG 3000 channelsMEG 3000 channels
ANITAANITA
ANTARESANTARES
H.E.S.S.H.E.S.S.
Belle-TOFBelle-TOF
Feb. 25th, 2010 NSNI-2010 Mumbai 38
Conclusions
• Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future, replacing traditional ADCs and TDCs
• SCA community growing! Exchange ofexperience is important. Joining is easy(e.g. USB evaluation boards)
• New generation of SCA chips on the horizon
Feb. 25th, 2010 NSNI-2010 Mumbai 39
Thank You!