27
Platform ASICs Reliability Bob Madge Miguel Vilchis LSI Logic , Milpitas, CA Vish Bhide

Platform ASICs Reliability

Embed Size (px)

DESCRIPTION

Platform ASICs Reliability. Bob Madge Miguel Vilchis LSI Logic , Milpitas, CA Vish Bhide. Three Aspects of Reliability. Infant Mortality Failures (Latent Defects and active defects that are not screenable with Testing) Environmental induced Failures (SER etc..) - PowerPoint PPT Presentation

Citation preview

Platform ASICs ReliabilityPlatform ASICs Reliability

Bob Madge Miguel Vilchis LSI Logic , Milpitas, CAVish Bhide

#141 MAPLD 2005Bob Madge 2

Three Aspects of ReliabilityThree Aspects of Reliability

Infant Mortality Failures (Latent Defects and active defects that are not screenable with Testing)

Environmental induced Failures (SER etc..)

Intrinsic Failures (Stress migration , electromigration , Wear-out , performance degradation)

#141 MAPLD 2005Bob Madge 3

Methods for Optimizing ReliabilityMethods for Optimizing Reliability

Design For Reliability Design for Defect Tolerance Design for SER tolerance Design for Stress Migration Tolerance Redundancy

Process Improvements Defect Density Reduction Excursion Control

Test Improvements Resistive Defect Fault Coverage Un-modeled fault coverage Statistical Testing

#141 MAPLD 2005Bob Madge 4

Platform ASIC –Infrastructure for ReliabilityPlatform ASIC –Infrastructure for Reliability

Embedded Test and Repair

Optimized Regular Logic Pre-Verified IP

Process Monitor and Die Traceability

Optimized Memory

Configurable I/O

#141 MAPLD 2005Bob Madge 5

Platform ASIC Design For ReliabilityPlatform ASIC Design For Reliability

Allowable antenna ratios have a 3x margin Additional protection against plasma induced damage Protection against wearout mechanisms

Stress Migration Electro Migration Hot Carrier Injection Time Dependent Dielectric Breakdown Vt stability

The rules are considered conservative within the industry The rules are tested for fabrication capability, yield and reliability during

qualification The libraries and layout tools strictly follow the design rules

Cells with intentional design rule violations require qualification

Tools such as relmil, BERT are available to the designers

#141 MAPLD 2005Bob Madge 6

Statistical Reliability ControlStatistical Reliability Control

Failure Mechanism or Attribute FIM

QUAL Qchip WLR Lot

ETEST + WLR

NRS @ Sort

SBL @ Sort

SBL @ FT

ORM Qchip

Antenna Damage TDDB Particles - Latent Reliability Defect Metal / Via Corrosion Metal Underetch Via Underetch Bridging Stress Voiding Ionic Contamination CHC Electromigration Lot to Lot Variation Wafer to Wafer Variation Within Wafer Within Field

#141 MAPLD 2005Bob Madge 7

Continuous feedback and improvementContinuous feedback and improvement

During Development:

Library elements are redesigned during the development cycle if design rules change

Process/Tool changes are made if the libraries cannot change

During production:

The customer issues are continuously fed back Process changes are made if applicable Cell changes are made if necessary

Current customers are protected by the MRB/TRB systems Redesigns incorporate the changes if necessary Future customers only receive the revised version Identification of issues by one customer benefits all others

#141 MAPLD 2005Bob Madge 8

Single Event Effects MitigationSingle Event Effects Mitigation

LSI Logic platform ASICs using 0.18 um CMOS commercial process are designed using best practices for SEE mitigation

optimization of n-well spacing and profile

buried layer for latchup mitigation

The mitigation strategies lead to SEL immunity to atmospheric neutron fluence of 5E10 n/cm2 and SEU cross section of 4E-14 cm2/bit. This performance is superior to a typical commercial grade product.

On chip error correction codes (ECC) for memory devices are available

word interleaving for multi bit error mitigation

#141 MAPLD 2005Bob Madge 9

Radiation PerformanceRadiation Performance Unlike commercial grade products, Platform ASICs using a 0.18 um

CMOS modified process have been characterized for Total Ionizing Dose (TID),

functional up to the maximum dose level of 300 krad-Si no noticeable degradation up to a total dose of 90 krad-Si.

Unlike commercial grade products, Platform ASICs using a 0.18 um CMOS modified process have been characterized for heavy ion Single Event Effects (SEE)

At LET of 75 MeV cm2/mg logic and SRAM blocks are immune to single event latchup (SEL) Single Event Upset saturation cross sections are 1E-06 cm2/bit and 7E-07 cm2/flip-flop

Additionally, Platform ASICs using a 0.115 um CMOS modified process have been characterized for heavy ion Single Event Effects (SEE)

At LET of 108 MeV cm2/mg logic and SRAM blocks are immune to single event latchup (SEL) Single Event Upset cross sections data is under evaluation

#141 MAPLD 2005Bob Madge 10

Efficient Netlist ImplementationEfficient Netlist Implementation

Early and Intrinsic Failure rates and Soft Error Rates are proportional to the number of used gates and SRAM

The platform ASICs implement the the RTL with minimum overhead of logic gates and require no configuration SRAM

Efficient Implementation through mask configuration leads to lower product failure rate than a product that requires more gates to implement the same functionality

#141 MAPLD 2005Bob Madge 11

Maverick Silicon Screening ProceduresMaverick Silicon Screening Procedures

Lot Level Lot Yield limits,Lot Acceptance testing >>>Minimum Quality

Wafer Level Wafer Yield limits,Statistical Bin Limits Maverick Lot Control >>>>Medium Quality

Die Level Iddq , VDD and Fmax Outlier Screening Dynamic and Enhanced Voltage Stress testing Adaptive Thresholds and limits Neighborhood Association or location Exclusion >>>>Maximum quality

#141 MAPLD 2005Bob Madge 12

Targeted Defect CoverageTargeted Defect Coverage

Reported Fault Coverage Tool reported Scan (target 99%) , Iddq , Memory , Delay faultcoverage.

Weighted Fault Coverage (Test Coverage) Reported Fault Coverage weighted by Area of the chip.

Defect Coverage Is a factor of : Weighted Fault Coverage , Fab. DefectivityFrequency , Gate Count and Outlier Screening Efficiency. Drives EFR and DPM Target 99.9%

#141 MAPLD 2005Bob Madge 13

LSI Logic Statistical Post-Processing™ Test FlowLSI Logic Statistical Post-Processing™ Test Flow

Wafer Test with full data collection and inkless wafermaps

Post-processor #1 : Delta IDDq / MinVDD

Post-processor #3 : Independent

Component Analysis (ICA)

Post-processor #2 : Neighborhood

Residual (NNR) and Exclusion (NAE)

Inkless Assembly

Burn-in (special

bins only)

Final package test

SHIPModify Inkless Maps (upgrade or

downgrade into special bins)

(Final Test Post-

Processing)

Data Wafers

Post-Processor #4: Temperature Ratios

#141 MAPLD 2005Bob Madge 14

SPP: Value Application:Burn-in elimination or reduction

Burn-in candidates

Rejection candidates

#141 MAPLD 2005Bob Madge 15Speed

Cu

rren

t

Count

Signal Overlap in Current Vs Speed

#141 MAPLD 2005Bob Madge 16

Statistical Post-Processing™ (SPP) used to Screen Test Outliers.Statistical Post-Processing™ (SPP) used to Screen Test Outliers.

SPP Concept # 1: Delta Iddq/MinVDD

The delta between the Iddq or MinVDD of discrete tests or vectors within a device can be used to distinguish between defective die and defect-free die.

SPP Concept # 2: Nearest Neighbor Residual (NNR)

If Iddq/MinVDD for a given die location on a wafer is significantly higher than it’s neighbors, that die can be considered defective.

SPP Concept #3 : Independent Component Analysis (ICA)

Identification and elimination of independent sources of parametric variation for defect identification.

SPP Concept #4 : Temperature Ratio Testing (US Patent Issue No . 6,532,431)

Ratio of test parameters (Iddq, MinVDD, Fmax) at two different temperatures can be used to distinguish between defective and defect free die.

#141 MAPLD 2005Bob Madge 17

SPP to Screen MinVDD Outliers : “Nearest Neighbor Analysis (NNR)”SPP to Screen MinVDD Outliers : “Nearest Neighbor Analysis (NNR)”

NNR Outliers

#141 MAPLD 2005Bob Madge 18Intrinsic Estimate

Res

idu

al

Count

Defect Signal Resolution after Post-Processing

SPP LimitSPP Limit

#141 MAPLD 2005Bob Madge 19

Resistive Defect Outlier ScreeningResistive Defect Outlier Screening

O45

0.00

20.00

40.00

60.00

80.00

100.00

120.00

140.00

R12

530_

4R

1253

0_5

R12

530_

6R

1253

0_7

R12

530_

10R

1253

0_13

R12

530_

14R

1253

0_15

R12

530_

16R

1253

0_18

R12

530_

19R

1253

0_21

R12

530_

24R

1253

0_25

R12

530_

26R

1253

0_27

R12

530_

29R

1253

0_30

R12

530_

34R

1253

0_35

R12

530_

39R

1253

0_41

R12

530_

43R

1253

0_44

R12

530_

45R

1253

0_48

R12

530_

52R

1253

0_53

R12

530_

54R

1253

0_60

R12

530_

61R

1253

0_62

R12

530_

70R

1253

0_75

R12

530_

76R

1253

0_15

15R

1253

0_15

37R

1253

0_15

74R

1253

0_17

28R

1351

5_64

1R

1351

5_65

1R

1351

5_65

6R

1351

5_65

8R

1351

5_69

3R

1351

7_62

2R

1351

7_67

5R

1351

7_69

2R

1351

7_70

4R

1351

7_70

6R

1351

8_62

3R

1351

8_71

3R

1351

8_71

4R

1351

8_71

5R

1351

8_71

8R

1351

9_64

0R

1351

9_64

3R

1351

9_66

2R

1351

9_67

7R

1351

9_68

9R

1352

0_64

4R

1352

0_65

0R

1352

0_66

0R

1352

0_67

3R

1352

0_68

4R

1377

6_1

R13

776_

2R

1377

6_3

R13

776_

4R

1377

6_5

Fm

ax (

MH

z)

Resistive unfilled

W Via

#141 MAPLD 2005Bob Madge 20

FVS vs RVS MinVDD on TDF Patterns at Room and -10C

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.1 1.2 1.3 1.4 1.5 1.6 1.7

RVS MinVdd

FV

S M

inV

dd

RMA1_room

RMA1_cold

RMA2_room

RMA2_cold

Gold1_room

Gold1_cold

Gold2_room

Gold2_coldThe two RMA parts are Feed-

Forward MinVDD Outliers

SPP Screening Temperature Dependant Defects

#141 MAPLD 2005Bob Madge 21Downgrades

8 9 1 8 1 81 8 8 8 1 8 1 1 8 8 8 8

8 8 1 1 8 1 1 1 1 1 1 8 8 1 1 88 8 1 8 1 1 1 1 1 1 1 1 1 1 1 1 8 1 8

8 8 8 1 8 1 1 1 1 1 1 1 1 1 1 1 1 8 1 8 8 111 1 8 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 8 1 8 8 8 88 8 1 1 1 1 1 1 1 8 1 1 1 8 1 8 8 8 8 8 8

1 1 1 1 1 14 1 1 1 1 1 1 1 8 1 1 1 8 8 1 14 1 8 8 1 11 1 1 9 8 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 8 8 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 10 1 1 8 8 8 8 81 1 1 1 1 1 1 1 1 8 1 1 8 1 1 1 1 1 1 1 1 1 1 1 8 1 1 8 8 88 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8

11 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 1 8 8 8 88 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 1 8 8 88 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 1 1 1 1 1 1 8 8 1 1 1 8 8 81 1 1 1 1 1 1 1 1 9 1 1 1 1 8 8 8 8 1 1 1 1 1 1 8 8 8 8 8 8 8 81 8 15 1 9 1 1 1 1 1 8 8 8 8 8 8 8 8 8 1 8 1 1 8 6 88 8 1 1 1 1 1 1 1 1 1 1 8 9 8 8 8 8 11 8 1 1 1 1 1 8 1 1 1 1 8 111 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 9 8 8 1 1 8 8 1 1 1 8 8 1 8 81 1 8 1 1 1 1 1 1 1 1 1 1 1 8 8 9 9 8 8 8 1 8 1 1 1 1 8 1 8 8 88 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 8 8 8 1 1 1 1 1 1 8 1 8 1 8

1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 1 8 8 8 8 8 8 8 1 8 88 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 8 8 1 1 8 1 8 8

1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 8 1 8 8 1 1 1 1 8 8 8 8 81 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 8 6 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 81 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 8 8 8

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 81 1 1 1 1 1 1 1 8 1 1 8 1 1 8 1 8 8 8 8

1 1 1 1 1 1 1 1 1 1 8 1 1 1 6 8 8 111 9 1 1 1 9 8 1 1 1 8 8 8 8

10 8 8 8 8 8 10

8 9 1 8 1 81 8 8 8 1 8 1 1 8 8 8 8

8 8 1 1 8 1 1 1 1 1 1 8 8 1 1 88 8 11 8 1 1 1 1 1 1 1 1 1 1 1 1 8 1 8

8 8 8 1 8 1 1 1 1 1 1 1 1 1 1 1 1 8 11 8 8 1111 1 8 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 8 1 8 8 8 88 8 1 1 1 1 1 1 1 8 1 1 1 8 1 8 8 8 8 8 8

1 1 1 1 1 14 1 1 1 1 1 1 1 8 1 1 1 8 8 1 14 11 8 8 11 111 1 1 9 8 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 8 8 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 10 1 1 8 8 8 8 81 1 1 1 1 1 1 1 1 8 1 1 8 1 1 1 1 1 1 1 1 1 1 1 8 11 11 8 8 88 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8

11 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 11 8 11 8 8 8 88 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 1 8 8 88 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 1 1 1 1 1 1 8 8 11 1 11 8 8 81 1 1 1 1 1 1 1 1 9 1 1 1 1 8 8 8 8 1 1 1 1 1 1 8 8 8 8 8 8 8 81 8 15 1 9 1 1 1 1 1 8 8 8 8 8 8 8 8 8 1 8 1 1 8 8 6 8 88 8 1 1 1 1 1 1 1 1 1 1 8 9 8 8 8 8 11 8 1 1 1 1 1 8 1 1 1 11 8 111 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 9 8 8 1 1 8 8 1 1 1 8 8 1 8 81 1 8 1 1 1 1 1 1 1 1 1 1 1 8 8 9 9 8 8 8 1 8 1 1 1 1 8 1 8 8 88 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 8 8 8 1 1 1 1 1 1 8 1 8 11 8

1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 8 8 8 8 8 8 1 8 88 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 8 8 11 11 8 11 8 8

1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 8 1 8 8 1 1 1 11 8 8 8 8 81 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 8 6 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 81 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 8 8 8

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 11 8 81 1 1 1 1 1 1 1 8 1 1 8 1 1 8 11 8 8 8 8

1 1 1 1 1 1 1 1 1 1 8 1 1 1 6 8 8 111 9 1 1 1 9 8 1 1 1 8 8 8 8

10 8 8 8 8 8 10

8 9 11 8 11 81 8 8 8 1 8 1 1 8 8 8 8

8 8 1 1 8 1 1 1 1 1 1 8 8 11 11 88 8 11 8 1 1 1 1 1 1 1 1 1 1 1 1 8 11 8

8 8 8 11 8 1 1 1 1 1 1 1 1 1 1 1 1 8 11 8 8 1111 11 8 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 8 11 8 8 8 88 8 1 1 1 1 1 1 1 8 1 1 11 8 11 8 8 8 8 8 8

1 1 11 1 1 14 1 1 1 1 1 1 1 8 1 1 1 8 8 1 14 11 8 8 11 111 1 1 9 8 1 1 1 1 1 1 1 1 1 1 8 1 1 1 11 1 1 8 8 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 10 1 11 8 8 8 8 81 1 1 1 1 1 1 1 1 8 1 1 8 1 1 1 1 1 1 1 1 1 1 1 8 11 11 8 8 88 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 8 8

11 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 11 8 11 8 8 8 88 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 11 8 8 88 1 1 1 1 1 1 1 1 1 1 8 1 1 1 8 11 1 1 1 1 1 1 1 8 8 11 11 11 8 8 81 1 1 1 1 1 1 1 1 9 1 1 1 1 8 8 8 8 1 1 1 1 1 1 8 8 8 8 8 8 8 8

11 8 15 1 9 1 1 1 1 1 8 8 8 8 8 8 8 8 8 1 8 8 11 11 8 8 6 8 88 8 1 1 1 1 1 1 1 1 1 1 8 9 8 8 8 8 11 8 11 1 1 1 1 8 1 1 11 11 8 111 1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 8 9 8 8 11 1 8 8 1 1 1 8 8 11 8 81 1 8 1 1 1 1 1 1 1 1 1 1 1 8 8 9 9 8 8 8 1 8 1 1 1 1 8 11 8 8 88 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 11 8 8 8 11 11 1 1 1 11 8 11 8 11 8

1 1 1 1 1 1 1 1 1 1 1 1 8 8 8 1 8 8 8 8 8 8 8 11 8 88 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 11 11 8 8 8 11 11 8 11 8 8

1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 8 11 8 8 1 1 11 11 8 8 8 8 81 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 8 8 6 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 8 8 81 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 1 8 8 8 8

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 11 11 8 81 1 1 1 1 1 1 1 8 1 1 8 1 1 8 11 8 8 8 8

1 1 1 1 1 1 1 1 8 1 8 1 1 11 6 8 8 111 9 1 1 11 9 8 11 11 11 8 8 8 8

10 8 8 8 8 8 10

8 9 11 8 11 811 8 8 11 1 11 8 8 8

8 8 11 11 8 11 1 1 1 1 11 8 8 11 11 88 8 11 8 11 1 1 1 1 1 1 1 1 11 11 11 8 11 8

8 8 8 11 8 11 1 1 1 1 1 1 1 1 1 1 11 8 11 8 8 1111 11 8 11 11 1 1 1 1 1 1 8 11 1 1 8 11 11 8 11 8 8 8 88 8 11 1 1 1 1 1 1 8 11 1 11 8 11 8 8 8 8 8 8

1 11 11 11 11 14 1 1 1 1 1 1 11 8 11 1 1 8 8 11 14 11 8 8 11 111 1 1 9 8 11 1 1 1 1 1 1 1 1 11 8 1 11 11 11 11 11 8 8 8 8 8 8

1 1 1 1 11 11 1 1 1 1 1 1 1 1 1 1 1 1 1 8 11 10 11 11 8 8 8 8 81 1 1 1 1 1 1 1 1 8 1 1 8 1 1 1 1 1 1 1 11 1 1 11 8 11 11 8 8 88 11 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 8 8 8 8

11 8 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 11 11 11 8 11 8 8 8 88 8 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 8 8 11 8 8 88 11 1 1 1 1 1 1 1 1 11 8 1 1 11 8 11 11 1 1 1 1 1 11 8 8 11 11 11 8 8 8

11 11 11 1 1 1 1 1 1 9 11 1 11 11 8 8 8 8 11 11 11 11 1 11 8 8 8 8 8 8 8 811 8 15 1 9 1 1 1 1 11 8 8 8 8 8 8 8 8 8 1 8 8 11 11 8 8 6 8 88 8 11 1 1 1 1 1 1 1 1 1 8 9 8 8 8 8 11 8 11 11 11 11 11 8 11 11 11 11 8 11

11 11 11 1 1 1 1 1 1 1 1 1 11 8 8 8 8 9 8 8 11 11 8 8 11 1 11 8 8 11 8 81 11 8 1 1 1 1 1 1 1 1 1 1 11 8 8 9 9 8 8 8 11 8 11 1 1 11 8 11 8 8 88 11 1 1 1 14 1 1 1 1 1 1 1 1 11 11 11 8 8 8 11 11 11 11 11 11 8 11 8 11 8

11 1 11 11 1 1 1 1 1 1 1 11 8 8 8 11 8 8 8 8 8 8 8 11 8 88 1 1 8 1 1 1 1 1 1 1 1 1 1 1 11 11 8 8 11 11 8 8 8 11 11 8 11 8 8

11 11 11 1 1 1 8 1 1 1 1 1 1 1 1 8 11 8 8 11 11 11 11 8 8 8 8 811 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 11 1 8 8 6 8 8 8 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 11 1 1 11 8 8 8 8 81 1 1 1 1 1 1 1 1 1 1 1 1 11 11 8 8 8 8

9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 8 8 11 11 8 81 1 1 1 1 1 1 1 8 1 11 8 11 1 8 11 8 8 8 8

1 1 1 1 1 1 11 11 11 11 8 11 11 11 6 8 8 1111 9 11 11 11 9 8 11 11 11 8 8 8 8

10 8 8 8 8 8 10

at increasing “stringency”

Good Die in Bad Neighborhoods – Latent Defect Post-ProcessingGood Die in Bad Neighborhoods – Latent Defect Post-Processing

In production on G12

#141 MAPLD 2005Bob Madge 22

Location Based DowngradesLocation Based Downgrades

11 11 8 8 8 1111 8 8 8 1 8 1 1 1 11 11 8

11 8 8 1 8 1 8 8 8 1 15 8 6 1 8 89 9 1 1 8 1 8 8 1 1 1 8 1 1 8 8 6 8 11

11 1 1 1 1 8 1 8 8 1 1 1 1 8 1 1 1 1 1 1 11 811 6 1 1 1 8 1 8 1 9 1 1 8 1 1 1 1 1 8 1 1 1 1 11

6 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 9 1 9 1 1 811 1 8 1 1 8 1 1 1 1 1 8 1 1 8 1 1 1 8 1 1 1 1 8 1 8

8 1 1 1 8 1 1 1 1 1 1 8 1 1 1 1 1 1 8 1 1 1 1 1 1 8 1 118 1 1 1 8 6 8 6 1 1 8 1 1 8 8 14 1 1 1 1 1 1 1 1 1 1 1 1 11

11 8 6 1 6 1 8 1 8 8 1 1 1 1 1 1 1 1 1 8 8 1 8 1 1 8 1 8 8 1111 1 1 1 1 1 1 8 8 1 1 1 1 8 8 1 1 1 1 8 1 1 1 1 1 1 1 1 1 11

8 1 8 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 8 1 1 1 8 6 1 1 8 1 8 1 911 1 8 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 8

9 1 1 6 1 1 1 1 1 1 1 1 1 1 8 8 1 8 8 1 1 1 1 1 1 1 8 1 1 1 89 1 1 1 1 1 1 1 1 1 1 1 8 6 15 8 8 1 8 8 1 8 1 1 1 1 1 8 1 1 88 1 1 1 1 1 1 1 1 1 8 1 1 1 8 1 1 1 1 1 6 6 1 1 1 1 1 8 1 9 11

11 8 1 1 1 1 1 1 1 8 1 1 8 8 8 1 1 1 8 8 1 6 1 1 1 1 8 1 1 1 1111 1 1 1 1 1 1 8 1 1 1 1 8 8 8 1 8 1 1 1 8 9 1 1 1 8 1 1 1 1 811 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 8 1 1 8 1 1 1 1 1 1 8 1 1 1 811 1 1 1 1 1 1 6 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 6 1 1 1 11

11 1 1 1 8 6 1 1 1 8 8 1 8 15 8 1 8 1 8 1 1 8 1 6 1 1 8 8 8 118 1 1 1 1 1 10 1 8 1 1 1 6 1 1 1 8 8 1 6 1 1 1 1 1 1 1 1 15 15

8 1 8 8 1 1 1 8 1 15 1 1 8 1 1 8 8 8 1 8 8 1 1 8 1 1 1 118 8 1 1 1 1 1 8 1 1 1 8 1 1 6 1 8 1 1 1 8 1 1 6 9 1 1 8

8 1 6 8 1 8 8 1 1 8 1 1 8 1 8 8 8 6 1 6 8 6 1 1 1 811 1 8 8 1 1 8 8 1 1 1 1 6 6 1 1 8 1 8 1 1 8 6 8

11 1 1 1 1 1 8 8 1 1 8 1 1 8 1 8 1 8 8 8 8 811 8 1 1 1 1 1 1 8 1 8 6 1 1 8 1 8 1 1 11

11 8 1 8 8 1 1 8 1 1 6 1 1 6 8 1 8 1111 8 8 11 8 8 8 11 11 8 8 6 8 8

Downgrade “good die” in “at-risk” locations like the edge

#141 MAPLD 2005Bob Madge 23

SPP: Application:New Technology Defectivity ControlSPP: Application:New Technology Defectivity Control

Def

ect

De

nsity

Time

Qua

lity

Time

Def

ect

De

nsity

Time

SP

P S

trin

genc

y

TimeQ

ualit

yTime

Quality Ramp Guarantee

Pre-emptive Variable Threshold control function

#141 MAPLD 2005Bob Madge 24

SPP: Application:Process Fluctuations and Maverick Lot Control

Qua

lity

Time

Feed ForwardS

PP

Str

inge

ncy

Time

Def

ect

De

nsity

TimeQ

ualit

yTime

Pre-emptive Variable Threshold control functionFeed-forward Variable Threshold control function

Def

ect

De

nsity

Time

Quality Ramp Guarantee

#141 MAPLD 2005Bob Madge 250 3 6 9 12 15 18 21 24 27 30 33 36 39

Node 1 EFR

Node 1 DD

Node 2 EFR

Node 2 DD

Node 3 EFR

Node 3 DD

Quality improvement due to Statistical Post-Processing™Quality improvement due to Statistical Post-Processing™

Overall EFR without SPP

Overall EFR with SPP

EF

R/D

PM

DD

Months

#141 MAPLD 2005Bob Madge 26

Reliability Improvement : Burn-in Results for SPP OutliersReliability Improvement : Burn-in Results for SPP Outliers

Sample # Fails %Fail Sample # Fails %Fail

Lot 1 3566 4.60% 163 163 25 15.34% 3403 0 0 0.00%

Lot 2 5320 3.74% 199 199 20 10.05% 5121 0 0 0.00%

Lot 3 5198 3.33% 142 142 15 10.56% 5056 0 0 0.00%

Lot 4 4620 2.79% 128 128 19 14.84% 4492 0 0 0.00%

Lot 5 5458 2.71% 144 144 0 0.00% 5314 444 0 0.00%

Lot 6 5458 2.64% 142 142 37 26.06% 5316 0 0 0.00%

Lot 7 5249 2.63% 137 137 16 11.68% 5112 0 0 0.00%

Lot 8 4580 2.62% 119 119 15 12.61% 4461 100 0 0.00%

Lot 9 4854 2.55% 121 121 6 4.96% 4733 0 0 0.00%

Lot 10 4888 2.39% 114 114 4 3.51% 4774 444 3 0.68%

Lot 11 5364 2.18% 106 106 4 3.77% 5258 100 0 0.00%

Lot 12 641 1.58% 10 10 0 0.00% 631 100 0 0.00%

Lot 13 4441 0.97% 41 41 7 17.07% 4400 100 0 0.00%

Lot 14 468 0.65% 3 3 0 0.00% 465 100 0 0.00%

Total 60105 2.68% 1,569 1,569 168 10.71% 58,536 1,388 3 0.22%

Burn-in Burn-inQuantity

Total Passing DieLot ID

SPP Downgrades Remaining Passing Die

% of Passing Die Quantity

#141 MAPLD 2005Bob Madge 27

# units # rejects % Fail DPM/Mgates

Bin 15 Population 1,569 168 10.7% 73,073

Bin 1 Population 1,388 3 0.2% 2,005

Est. for total Passing Population 60,107 298 0.5% 3,356

EFR improvement 56.4%

Yield Hit (%Bin 15 ) 2.68%

Reliability Improvement : Burn-in Results

Overall data show at least 56% effectiveness.

The EFR estimate for Bin1 population is data limited and likely to be at least 50% lower

Therefore the overall effectiveness number is likely to be much higher.