Designing with the TPS23753 Powered Device and Power

Application ReportSLVA305–July 2008

Designing with the TPS23753 Powered-Device and PowerSupply Controller

Eric Wright .......................................................................................................... HPA/Power Interface

ABSTRACTThe TPS23753 is an IEEE 802.3-2005-compliant powered-device and power supplycontroller optimized for isolated converter topologies. This application report provides acomprehensive design example for the TPS23753EVM-002 evaluation module (EVM).This EVM is targeted at low-cost, simple, 7-W flyback converter applications.

Contents1 Introduction .......................................................................................... 22 Design Example and Component Selection .................................................... 2

2.1 Powered-Device Controller............................................................... 42.2 Adapter Input ............................................................................... 42.3 Frequency and Blanking .................................................................. 52.4 Bias Supply................................................................................. 62.5 DC-DC Converter Characteristics ....................................................... 62.6 Flyback Transformer ...................................................................... 72.7 Power Train ................................................................................ 92.8 Feedback Control ........................................................................ 112.9 Frequency Characteristics .............................................................. 132.10 Loop Compensation ..................................................................... 13

3 PCB Layout Guidelines........................................................................... 184 PCB EMI Control .................................................................................. 185 Conclusion ......................................................................................... 196 References......................................................................................... 19

List of Figures

1 Generic PD and Flyback Converter Circuit Block Diagram ................................... 32 Example Primary Current Waveform............................................................. 83 Example Secondary Current Waveform ....................................................... 104 Mathcad™ Bode Plot (Minimum Input/2-A Output)........................................... 165 TPS23753EVM-002 Network Analyzer Plot (24-V Input/2-A Output) ...................... 176 TPS23753EVM-002 Network Analyzer Plot (48-V Input/2.2-A Output) .................... 17

List of Tables

1 TPS23753EVM-002 Electrical Specifications ................................................... 2

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1 Introduction

2 Design Example and Component Selection

Introduction www.ti.com

The TPS23753 supports designs using isolated flyback converter topologies. Benefits include lowervoltage operation along with built-in features including:• Devices optimized for isolated converters• Programmable frequency with synchronization• Adjustable leading-edge blanking• Simplified dc/dc control 100-V ratings• –40°C to 125°C junction temperature range• Current and inrush limit• Thermal protection

Table 1 outlines the electrical requirements for this design example.

Table 1. TPS23753EVM-002 Electrical SpecificationsPARAMETER CONDITION MIN TYP MAX UNIT

POWER INTERFACEInput voltage Applied to the power pins of connectors J1 or J2 0 – 57 VOperating voltage After start-up 30 – 57Input UVLO Rising input voltage – – 36

Falling input voltage 30 – –DC/DC CONVERTEROutput voltage 20 V ≤ Vin ≤ 57 V, ILOAD ≤ ILOAD (max) 3.3-V 3.13 3.3 3.47 V

10.8 V ≤ Vin ≤ 13.2 V, ILOAD ≤ ILOAD (max) outputOutput current 20 V ≤ Vin ≤ 57 V 3.3-V – – 2 A

output10.8 V ≤ Vin ≤ 13.2 V – – 1.2Output ripple voltage, Vin = 44 V, ILOAD = 2 A 3.3-V – 65 – mVpeak-to-peak outputEfficiency, end-to-end Vin = 44 V, ILOAD = 2 A 3.3-V – 77% –

outputSwitching frequency 225 – 275 kHz

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www.ti.com Design Example and Component Selection

The equations that follow are associated with the schematic diagram in Figure 1. The referencedesignators in Figure 1 perform a cross-reference function to both the TPS23753EVM-002EVM and theTPS23753 data sheet (SLVS853).

Figure 1. Generic PD and Flyback Converter Circuit Block Diagram


http://www-s.ti.com/sc/techlit/SLVS853


2.1 Powered-Device Controller

2.1.1 TVS, D1

2.1.2 Capacitor, C1

2.1.3 Detection Resistor, RDEN

DEN

DEN

23.75 k + 26.25 kR = = 25 k

2

Choose R = 24.9 k , 1%

W WW

W (1)

2.1.4 Classification Resistor, RCLS

2.2 Adapter Input

2.2.1 Input Blocking Diode, DA

Design Example and Component Selection www.ti.com

D1 is used to protect the powered-device (PD) controller front-end from overvoltage due to line transients,hotplug into 48-V sources, and output faults. A transient suppressor diode, such as the SMAJ58A, mustbe connected from VDD to VSS.

The IEEE 802.3-2005 standard specifies a VDD-VSS bypass capacitor whose value is required to be 0.05µF–1.2 µF. Typically, a 0.1-µF, 100-V, 10% ceramic capacitor is used.

The IEEE 802.3-2005 standard specifies a detection signature resistance, RDEN, between 23.75 kΩ and26.25 kΩ.

Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3-2005standard. The power assigned must correspond to the maximum average power drawn by the PD duringoperation. Select RCLS according to the following table.

CLASS POWER AT PD PI CLASS CURRENT RESISTOR MINIMUM NOTES(Ω) PACKAGEMINIMUM MAXIMUM MINIMUM MAXIMUM SIZE(W) (W) (mA) (mA)

0 0.44 12.95 0 4 1270 04021 0.44 3.84 9 12 243 04022 3.84 6.49 17 20 137 04023 6.49 12.95 26 30 90.9 06034 12.95 25.5 36 44 63.4 0603 802.3at only, not allowed for IEEE

802.3-2005

Because this design example is 7 W, either class 0 or class 3 can be chosen. Because the output loadingis not fixed, class 0 and RCLS = 1270 Ω is chosen.

The adapter configuration shown in Figure 1 bypasses the PD hotswap MOSFET by applying the adaptervoltage directly to the TPS23753 converter section (VDD1 and RTN). Other adapter O-ring configurationsare possible and are discussed in application report SLVA306.

DA should be rated for the reverse voltage required which is typically 80 V–100 V. A Schottky diode ratedfor the maximum adapter low line input current is preferred to minimize diode power loss. For thisexample, the MURA120 diode is used (200 V, 1 A, VF = 0.75 V maximum, VF = 0.7 V nominal at 550mA).


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2.2.2 APD Pin Divider Network, RAPD1, RAPD2

MINAPD

APDEN

Vin 36 VDR 24

V 1.5 V= = =

(2)

( )APD1 APD2 APDR = R DR 1 = 3.01 k 23 = 69.23 k´ - W ´ W (3)

APD1 APD2ADPTR_ON APDEN

APD2

R R 72.81 kV = V = 1.5 V = 36.3 V

R 3.01 k

+ W´ ´

W (4)

( )APD1 APD2ADPTR_OFF APDEN ADPH

APD2

R R 72.81 kV = V V = 1.2 V = 29 V

R 3.01 k

+ W´ - ´

W (5)

MAXAPD

APD1 APD2

APD2

Vin 48 1.1 VV 2.19 V

72.81 kΩR R

3.01 kΩR

´> = =

æ ö æ ö+ç ÷ç ÷è øè ø

<

(6)

2.3 Frequency and Blanking

2.3.1 Frequency Setting Resistor, RFRS

FRS

SW

FRS

15000 15000R (k ) = = = 60 k

f (kHz) 250

Choose R = 59 k

W W

W (7)


The APD pin can be used to disable the TPS23753 internal hotswap MOSFET giving the adapter sourcepriority over the PoE source. An active APD pin also disables the internal class regulator and CLS pin.

RAPD1 and RAPD2 provide ESD protection, leakage discharge for the adapter ORing diode, and inputvoltage qualification. The APD divider ratio DRAPD must be chosen with consideration given to the APD pinmaximum recommended input voltage, class regulator and resistor power dissipation, and adapter disablethreshold.

The following example illustrates selection of RAPD1 and RAPD2.1. To prevent the converter from operating at an excessively low adapter voltage, choose a start-up

voltage, VSTART, approximately 75% of nominal. Assuming that the adapter output is 48 V ± 10%, thisprovides 15% margin below the minimum adapter operating voltage.

2. Choose VSTART = 48 × 0.75 = 36 V.3. Select RAPD2, considering power dissipation. Choose RAPD2 = 3.01 kΩ

4. Choose RAPD1 = 69.8 kΩ5. Check the adapter turnon and turnoff voltage.

6. Check the APD pin voltage at maximum adapter input.

7. VAPD is less than VB, so is within the recommended maximum.

APD turns the class regulator off when the input voltage is above the threshold. When low-voltageadapters are to be used, the APD pin divider can be chosen with class regulator and class resistor powerdissipation in mind. With lower APD divider ratios, caution must be exercised to avoid damage to the APDpin if used with a higher voltage adapter.

For this design, ƒSW = 250 kHz



2.3.2 Blanking Interval, RBLNK

4

BLNK

SW

4

BLNK

BLNK

BI(%)10 (nS) = R (k )

f (kHz)

Choose BI(%) = 2%

2R (k ) = 10 = 80 k

250

Choose R = 80.6 k

´ W

W ´ W

W (8)

2.3.3 Internal Control Rail Capacitor, CVB

2.4 Bias Supply

2.4.1 Bias Supply Diode, DVC

2.4.2 Bias Supply Resistor, RVC

2.4.3 Bias Supply Capacitance, CVC1, CVC2

´

» - »

´

C ST

VC1

1

C ST 1

VC1

VC1

I TC =

UVLO

I 3 4 mA, T 30 mS, UVLO = 9 V

0.0035 0.05C = = 11.7 μF

9

Choose C = 10 μF (9)

2.5 DC-DC Converter Characteristics

2.5.1 Output

NOM RIPPLE

MAX MIN

MAX MIN

3.3V OutputLoad

Vout = 3.3 V, Vout = 1.5%

Pout = 7W, Pout = 0W

Iout = 2.15A, Iout = 0A

NOM RIPPLE

MAX MIN

MAX MIN

12V Bias

Vout = 12V, Vout = 5%

Pout = 60mW, Pout = 0W

Iout = 5mA, Iout = 0A (10)


External blanking can be achieved by installing RBLNK. If the internal blanking interval is sufficient, connectthe RBLNK pin to RTN. Choose the blanking interval to be a percentage of the switching period.

VB must be bypassed with a 0.1-µF ceramic capacitor to RTN. VB is an internal 5-V control rail and mustbe used to bias the feedback opto-coupler, U2

DVC can be a small, general-purpose diode. For this example, BAS16 diode is used (75 V, 150 mA).

RVC helps to reduce peak charging from the bias winding. Typical RVC values range from 0 Ω to 100 Ω.Choose RVC = 49.9 Ω.

VC must be bypassed with a 0.22-µF minimum ceramic capacitor (CVC2) to RTN. The value of the bulk VCcapacitor (CVC1) affects the converter start-up time as well as shorted output hiccup frequency. CVC1 ischarged by the internal VC bootstrap current source as VC approaches UVLO1. CVC1 affects the charge-uptime as follows:



2.5.2 Input

MAX MIN

MAX MIN

PoE (at PSE Power Interface)

Vpse = 57V, Vpse = 44V

Ipse = 350mA, Ipse = 0ANOM TOL

Adapter (24V)

Vadp = 24 V, Vadp = ±10%(11)

2.5.3 Efficiency Target

2.5.4 Maximum Adapter Input CurrentMAX

MAX

MIN FB

Pout 7WIadp = = = 415 mA

Vadp η 21.6V 0.78´ ´ (12)

2.5.5 Minimum Converter Input Voltage- -

MIN MIN DA

MIN

Vfb = Vadp V = 21.6V 0.7V = 20.9V

design for Vflyback = 20V (13)

2.5.6 Duty Cycle

2.6 Flyback Transformer

2.6.1 Primary Voltage Drops

M1 CS

PRIMARY MAX

Rds - on + R 1

Vdrop = 2 Iadp 1 = 0.831V

» W

´ ´ W (14)

2.6.2 Secondary and Bias Winding Voltage DropsMIN

MAX

MIN

secondary

DVC

VC

VC

BIAS DVC VC VC

Vflyback 20VIsecondary = 2 Iadp = 2 0.415A = 5.27A

Vout 3.15V

Vdrop 0.4V

V 0.5V

I 5mA

R = 50

Vdrop = V + I R = 0.5V + 0.005 50 = 0.75V

´ ´ ´ ´

»

»

»

W

´ ´ (15)

2.6.3 Required Transformer Turns Ratios.

-

- -

-

- -

DESIGN MIN PRIMARY

P_S

DESIGN NOM SECONDARY

DESIGN MIN PRIMARY

P_B

DESIGN NOM BIAS

Dmax Vflyback VdropN = × = 7.33

1 Dmax Vout Vdrop

Dmax Vflyback VdropN = × = 2.22

1 Dmax Vbias Vdrop (16)


ηFB ≈ 78%

The TPS23753 supports duty cycles up to 80%. Choose a maximum operating duty cycle for the converterthat includes plenty of margin.

DmaxDESIGN ≈ 60%

Estimate the primary element voltage drops assuming that the peak primary input current is twice themaximum adapter low line input current.

The equations yield a maximum turns ratio at VflybackMIN and DmaxDESIGN



2.6.4 Target Peak Primary Current

æ ö´ ´ç ÷

-è ø

P-S P_S

MAX

peak

P-S DESIGN

N = 7(N rounded to integer)

Iout4 1I = = 1.036A

3 N 1 Dmax (17)

2.6.5 Primary Inductance

-

´

´

DESIGN MIN PRIMARY

NOM peak

Dmax Vflyback VdropLprim = = 87.6 μH

freq 0.5 I (18)

2.6.6 Select the Transformer

2.6.7 Actual Duty Cycle at Voltage Using Selected TransformerNOM SECONDARY PS

ACTUAL

MIN PRIMARY NOM SECONDARY PS

NOM SECONDARY PS

ACTUAL

MAX PRIMARY NOM

(Vout + Vdrop ) NDmax = = 50.4%

(Vflyback Vdrop ) + (Vout + Vdrop ) N

(Vout + Vdrop ) NDmin =

(Vflyback Vdrop ) + (Vout

´

- ´

´

-SECONDARY PS

NOM SECONDARY PS

12V

PRIMARY NOM SECONDARY PS

= 25.7%+ Vdrop ) N

(Vout + Vdrop ) NDmax = = 67.7%

(10.1 V Vdrop ) + (Vout + Vdrop ) N

´

´

- ´ (19)

2.6.8 Calculate Primary Currents

TON TOFFIdc

fbM

AX

Ip

ri_

ste

p

Ip

rim

ary

PE

AK

D IL PRIMARY


For a continuous conduction mode (CCM) flyback converter, a good rule is to choose the primary ripplecurrent to be < 50% of the peak primary current. Doing this yields the following equation.

The following equation yields a minimum primary inductance required to keep the peak current below thatin Equation 17.

Several readily available 7-W choices exist for this PoE transformer. Significant data sheet parametersfollow.

Primary Inductance, LP = 155 µHPrimary-to-secondary turns ratio, NPS = 5.26Primary-to-bias turns ratio, NPB = 1.5

An example of the primary current waveform is shown in Figure 2.

Figure 2. Example Primary Current Waveform

8 Designing with the TPS23753 Powered-Device and Power Supply Controller SLVA305–July 2008Submit Documentation Feedback


MAX

MAX

MIN FB

PoutIdcfb = = 0.45A

Vflyback η´

MAX

ACTUAL

IdcfbIpri_step = = 0.89A

Dmax

-

´ACTUALMIN PRIMARY

PRIMARY

P

DmaxVflyback VdropΔIL = = 0.25A

L freq

PRIMARY

PEAK

ΔILIprimary = Ipri_step + = 1.0A

2

2.7 Power Train

2.7.1 Primary Switching MOSFET, M1

PRIMARY MAX NOM SECONDARY PS

Snubber to limit Vleakage to 25V

Vds = Vflyback + Vleakage + (Vout + Vdrop ) N 101V

»

´ » (20)

2.7.2 Current Sense Resistor, RCS

CSMAX

CSMAX

MIN

PEAK

CS

From TPS23753 datasheet, V = 0.55V typical

VRcs = = 0.55Ω

Iprimary

Choose R 0 = 0.56Ω, 0.25W (21)

2.7.3 Snubber, RSN , CSN, DSN

( )

´ ´

æ ö» » ´ç ÷

è ø

LKG

PEAK

WDG OSS_M1

2

NEW SN WDG OSS_M1

NEW

SN

L 4 μHVspike = Iprimary = 1.0A = 141V

C + C 200 pF

VspikeWe need Vspike 25V so C should be C + C = 6nF

Vspike

Choose C = 10nF (22)


Low line average DC input current:

On-state step current:

Ramp current:

Peak current:

Determine drain-to-source voltage rating. The snubber limits the actual voltage excursion.

Choose a MOSFET with a 150-V, drain-to-source rating. A small package device such as SOT-23 issuitable for this power level. Drain current of at least 1.5 A and RDSon of 500 mΩ is sufficient. Choose aMOSFET with a fairly low gate charge (10-20 nC) due to the potentially low operating voltage conditionsthat may be encountered in a shorted output condition. The TPS23753 can operate down to about 6.5 V;so, this requires that the MOSFET adequately switch on during these conditions.

Without a snubber, the stored energy in the leakage inductance rings with the transformer interwindingand MOSFET output capacitance at MOSFET turnoff. The transformer leakage inductance, LLKG, may be2%-3% of the primary inductance and the MOSFET and transformer winding capacitance can be severalhundred picofarads.

Choose RSN so that the snubber time constant is much larger (say 200x) than the switching period.Choose DSN for the input filter; LIN, CIN1, CIN2 required reverse voltage and leakage inductance chargingcurrent.



SN

SN

200R = 80 kΩ

freq C»

´ (23)

2.7.4 Input filter; LIN, CIN1, CIN2

( )RIPPLE

MAX ACTUAL

MIN

RIPPLE

IN2

Target input ripple voltage, Vin 1V

Ipri_step Idcfb DmaxCin = = 0.89 μF

freq Vin

Choose C = 1μF, X7R ceramic, 100V, 10m ESR at 100 + kHz

2ARMS ripple current rating

Vin

»

- ´

´

W

D( )MAX ACTUAL

CIN2 CIN2

IN2

Ipri_step Idcfb Dmax= + Ipri_step ESR = 0.9V

freq C

- ´´

´ (24)

CIN1 CIN1 CIN1 CIN1

CIN1 CIN2

IN

MAX

Choose C1 = 22 μF, aluminum electrolytic, 100V, 1.3 ESR at 100 kHz,

130 mA RMS ripple current rating.

Target I < 0.13A so V = I ESR = 170mV

V + VL

Ipri_step Idcfb

W

D D D ´

D D»

-

ACTUAL

CIN1

Dmax= 5.5 μH

I freq´

- D (25)

2.7.5 Calculate Secondary Currents

TOFF TON

Iou

tM

AX

Ise

c_

ste

p

Ise

co

nd

ary

PEAK

D IL SECONDARY


Alternatively, an RC snubber from the primary FET drain to RTN can be employed to limit the spike andslow down the turnoff rise time. This may be preferred for an application where reduced conductedemissions are required. The RC combination should be chosen to minimize the effect on efficiency whilereducing the spike to an acceptable safe level. Typical values are 80 Ω, 1/2 W, 330 pF, and 200-V for thisapplication.

The input capacitance (CIN1 and CIN2) must furnish the transient switching current. An inductor, LIN,provides another layer of filtering and reduces the requirements on CIN2. CIN1 provides bulk filtering,whereas CIN2 provides switching energy absorption.

Select a common-type aluminum electrolytic capacitor for CIN1, and then size the inductor to achieve theadditional attenuation of the ripple voltage.

Choose a 4.7-µH, 1.5 ARMS, 90-mΩ inductor.

An example of the secondary current waveform is shown in Figure 3.

Figure 3. Example Secondary Current Waveform



-

MAX

ACTUAL

IoutIsec_step = = 4.48A

1 Dmax

D ´ ´ -SECONDARY PS PEAK

IL = 2 (N Iprimary Isec_step = 1.73A

PEAK PS PEAKIsecondary = N Iprimary = 5.34A´

2.7.6 Output Filter; COUT1, COUT2

( )RIPPLE

MAX ACTUAL

MIN

RIPPLE

OUT2

Target output ripple voltage, Vout 50mV

Isec_step Iout (1 Dmax )Cout = = 90.4 μF

freq Vout

Choose C = 2x47μF, X5R ceramics, 6.3V, 2m ESR at 100+kHz

»

- ´ -

´

W (26)

( )( )MAX ACTUAL

COUT2 MAX COUT2

OUT2

4ARMS ripple current rating

Isec_step Iout (1 Dmax )Vout = + Isec_step Iout ESR = 51 mV

freq C

- ´ -D - ´

´ (27)

2.7.7 Output Rectifier; DS

2.7.8 Thermal Considerations

2.8 Feedback Control

2.8.1 Shunt Regulator, U3

2.8.2 Output Voltage Setpoint Resistors: RFBU, RFBL


Off-state step current:

Ramp current:

Peak current:

The output capacitance (COUT1 and COUT2) must furnish the transient load current. COUT1 provides bulkfiltering, whereas COUT2 provides switching energy absorption.

Add COUT1 = 47 µF, aluminum electrolytic, 6.3-V, 1.25-Ω ESR at 100-kHz, 90-mA RMS ripple currentrating.

The low-ESR ceramics effectively shunt the ESR of the aluminum electrolytic. The additional rippleattenuation due to the aluminum electrolytic is minimal due to the larger ESR.

The output rectifier diode must provide low forward voltage drop at the secondary peak current.Consideration must also be given to a safe operating area during output overload conditions. For thiscase, the converter goes to a constant output power condition with low-primary and high-secondary dutycycle. DS must withstand these conditions reliably. Choose DS to be a MBRS540T3 in a SMC package(40-V reverse voltage, 5-A continuous current max, Vf = 0.5 V max at 5 A).

Consideration must be given to the power dissipation in M1, RCS, and DS. Both conduction and switchinglosses must be considered.

For this 3.3-V application, a low-voltage reference shunt regulator is required. Choose the TLV431A with a1.24-V, 1% internal reference.

Choose RFBU based on expected integrator midband gain and zero location. Estimate the integrator zerolocation to be approximately 1 kHz, integrator zero capacitors are from 1 nF–10 nF, and low integratorgain.



IZE

FBUE IZE

FBU

1R = 33.9k

2 4.7nF 1kHz

R R

Choose R = 41.2 k

p» W

´ ´ ´

»

W (28)

FBU

FBL

NOM

FBL

Vref = 1.24V

Vref RR = = 24.8 k

Vout Vref

Choose R = 24.3 k

´W

-

W (29)

2.8.3 Opto-Isolator, U2 Biasing

5mA

2mA 5mA

OPTO OPTO

CTR = 80 160%,

CTR = 0.7 CTR 0.85 from device data sheet curves

Vled 1.1V at Iled = 2mA

-

´ »

» (30)

2.8.4 Opto-Isolator LED Bias Current

- -W

W

OPTO-K

NOM OPTO OPTO-K

OB

OPTO

OB

Start with bias at zero duty cycle (ZDC)

Vled = Vref + 150mV

Vout Vled VledR = = 405

Iled

Choose R = 402 (31)

2.8.5 Opto-Isolator Transistor Bias Current

´

- -

MAX

MAX B

MAX MAX MAX

MAX MAX

NOM

OPTO MAX

CTL

OPT

Start with bias at zero duty cycle (ZDC)

TPS23753 Vzdc = 1.7V

TPS23753 Vcs = 0.55V,V = 5V

Vctl = Vzdc + 2 Vcs

Vzdc + VctlVctl = = 2.25V

2

Vb Vled VzdcR =

IledW

´

W

O 2mA

CTL

= 1.94kCTR

Choose R = 2 k (32)

2.8.6 Secondary Side Soft Start


Choosing RFBL a little smaller than calculated ensures an output voltage a bit higher than nominal tocompensate for the DC drops from the power supply to the load.

Choose the opto-isolator to provide a fairly low but stable current transfer ratio characteristic when theLED is driven with a 1- to 2-mA current bias. Typical parameters for an opto-isolator of this sort are:

Place an RC network on the shunt regulator output for soft start. Typical values are RSS = 10 kΩ and CSS= 0.1 µF. A blocking diode, DSS, isolates the outer loop from RSS and CSS.



2.9 Frequency Characteristics

2.9.1 Modulator-Power Stage (MPS) Gain and Right-Half Plane Zero (RHPZ)

ACTUAL PS

MPS

CS

2

NOM

MAX

2

PS ACTUAL

ACTUAL P

(1 Dmax ) × N AGain, K = = 4.66

R V

VoutRload = = 1.56

Pout

Current mode control yields right half plane zero, RHPZ

[N (1 Dmax )]RHPZ = Rload = 21.6 k

2 Dmax Lp

-

W

-´

´ ´ ´Hz

(33)

2.9.2 MPS Current

RHPZ

MPS MPS

RHPZ

ω = 2 RHPZ

jωI (ω) = K (1 )

ω

´ ´

´ -

p

(34)

2.9.3 Output Filter (Plus Load) Frequency Characteristics

COUT1 COUT2Zout(ω) = Z (ω)||Z (ω)||Rload (35)

2.9.4 MPS Plus Filter and Load (MPF) Transfer Function

RHPZ

MPS

ω = 2 RHPZ

MPF(ω) = I (ω) Zout(ω)

´ ´

´

p

(36)

2.10 Loop Compensation

2.10.1 Choose Desired Loop Crossover Frequency, F0 = 5.5 kHz


The MPS gain, KMPS is the ratio of modulator output current to CS pin voltage, VCS. KMPS and RHPZ arederived below in Equation 33

The MPS current, IMPS(ω), is the product of KMPS and RHPZ.

The output impedance is simply the parallel combination of the output capacitors (including eachcapacitor's equivalent series resistance or ESR) and the load.

The MPF transfer function is shown in Equation 36

The following discussion relies on the use of a mathematics program like MathCAD™ or Excel™ toperform the calculations. Some iteration is involved, but the end results are close to actual performance.

The inner control loop consists of the opto-isolator and associated components. The outer control loopconsists of the integrator. It can be shown that the overall transfer function from VOUT to VCTL is:

–OPTO(ω) x [INT(ω) + 1]where OPTO(ω) is the opto-isolator transfer function and INT(ω) is the integrator transfer function



2.10.2 Overall Transfer Function

CTL

S 2mA

OB CTL CTL CTL

CTL

FB(ω) = - MPF(ω) OPTO(ω) (INT(ω)+1)

where FB(ω) is the flyback overall transfer function.

R 1 1Simplified OPTO (ω) = CTR

R 1+jω R C K

TPS23753 internal CTL divider, K = 2

S

´ ´

´ ´ ´

´ ´

S

FBU IZ

MO S

MO 0 0 S

1implified INT (ω) =

jω R C

Modulator/opto transfer function, G (ω) = MPF(ω) OPTO (ω)

G (2 F ) = MPF(2 F ) OPTO (ω)p p

´ ´

- ´

´ ´ ´ ´ ´ (37)

2.10.3 Compensate Opto-Isolator or Inner Loop

MO 0

2

0)CTL 2mA

OB CTL MO

CTL

0 CTL

CTL

Choose G (2 F ) = 0.75

MPF(2 FR CTR1

R K GC = = 50.3nF

2 F R

Choose C = 47nF

p

p

p

´ ´

é ù´ ´ê ú- ´ ´ê úë û

´ ´ ´

(38)

2.10.4 Inner Loop Control Zero Resistor, RZCTL

2.10.5 Inner Loop Transfer FunctionCTL ZCTL CTL

2mA

OB CTL ZCTL CTL CTL

R 1+jω R C 1OPTO(ω) = CTR

R 1+jω (R + R ) C K

´ ´

´ ´ ´

´ ´ (39)

2.10.6 Outer Loop Compensation

MO 0 0 S 0G (2 F ) = MPF(2 F ) OPTO (2 F ) = 0.772p p p´ ´ ´ ´ ´ ´ ´ (40)


Select CCTL to achieve a gain sufficiently below unity at the crossover frequency. Start by assuming thesimple integrator INTS(ω) with no midband gain (RIZ = 0). Target an initial |GMO(2 × π × F0)| > 0.5–0.8 toestimate CCTL. CCTL must be limited to 47 nF or less.

For lower output power and voltage designs, a resistor in series with CCTL can provide phase boost forstability. Target RZCTL ~ RCTL /10).

Choose RZCTL = 249 Ω

Now that the inner loop is first-pass compensated, design an integrator with midband gain to yield thedesired crossover. First calculate the new GMO including RZCTL.

Solve for the integrator midband gain (RIZ/RFBU), which causes the overall transfer function to be unity atF0.



( )

IZ

MB

FBU

MO 0 MB

IZ

MB

FBU MO 0

IZ FBU

MO 0

IZ

RINT =

R

G (2 F ) INT +1 = 1

R 1INT = = 1

R G (2 F )

1R = R 1 = 12.16 k

G (2 F )

Choose R = 12.1 k

p

p

p

´ ´ ´

-´ ´

é ù´ - Wê ú

´ ´ê úë ûW (41)

IZ

IZ 0

IZ

1C = = 11.9 nF

2 R (5 F )

Choose C = 6.8nF

p´ ´ ´ ´

(42)

IP

IZ 0

IP

1C = = 240 pF

2 R F

Choose C = 100pF

p´ ´ ´

(43)

2.10.7 Integrator Transfer Function

IZ IZ IZ

FBU IZ IP

11 +

R jω R CINT(ω) =

R 1+jω R C

´ ´

´

´ ´ (44)

2.10.8 Stability Check

( )

( )

0

-1 o

0

0

From Mathcad, FB(2 F ) = 0.790 + 0.612i

0.612 180Phase = tan = 37.8 or Phase = arg FB(2 π F )

0.790

20 log FB(2 F ) = 0.1 dB

´ ´

æ ö ´ ´ ´ç ÷è ø

´ ´ ´ -

p

p

p (45)

ZCTL

MO 0

IZ FBU

MO 0

IZ

Choose new R = 402

New G (2 F ) = 0.804

1New R = R 1 = 10 k

G (2 F )

Choose R = 7.15k

p

p

W

´ ´

é ù´ - Wê ú

´ ´ê úë û

W (46)


Select the integrator zero capacitor, CIZ, by choosing an integrator zero 4 to 5 times below F0. Note thatonce the bode plot is mathematically generated, some shaping of the response curves can be performedto optimize the desired response.

Select the integrator pole capacitor, CIP, by choosing an integrator zero 10 times above F0.

For loop stability analysis, break the feedback loop between the output load and the input to the shuntregulator feedback network and inject a noise source. The shunt regulator/integrator shifts phase by 270degrees (180 due to inversion and 90 due to integrator). So, the output load phase leads the input phaseby 90 degrees. Instability occurs as the phase difference approaches 0 degrees (or in-phase input andoutput signals).

The phase margin is inadequate. Increase RZCTL, then recompute RIZ.

Recompute the new phase margin.



( )

0

-1

0

From Mathcad, FB(2 F ) = 0.609 + 0.719i

0.719Phase = tan = 49.8

0.609

20 log FB(2 F ) = 0.5 dB

´ ´

æ öç ÷è ø

´ ´ ´ -

o

p

p (47)

10 100

-100

100

0

Gain and Phase

Lo

op

Ga

in -

dB

, P

ha

se

- d

eg

120

-120

20·log(|FB( )|)w

arg(FB( ))·w

180

p

1x103

1x104

1x105

1x106

f - Frequency - Hz

w

2·p


The new phase margin is now acceptable.

The modeled bode plot is shown in Figure 4 and the modeled crossover is at 5.3 kHz with phase marginof 50 degrees. Figure 5 and Figure 6 show the circuit response using a network analyzer. The actualresults correlate closely with the modeled results.

Figure 4. Mathcad™ Bode Plot (Minimum Input/2-A Output)



60

-60

Ga

in

Ph

as

e

180

-180

10 100 kf - Frequency - Hz

1 Side Bar:

4619 k Frequency - Hz,0 Gain - dB,48.82 Phase - deg,-1.47 Slope - 20 dB/decode

60

-60

Ga

in

Ph

as

e

180

-180

100 kf - Frequency - Hz

1 Side Bar:

6.168 k Frequency - Hz,0 Gain - dB,54.62 Phase - deg,-1.39 Slope - 20 dB/decode

10


Figure 5. TPS23753EVM-002 Network Analyzer Plot (24-V Input/2-A Output)

Figure 6. TPS23753EVM-002 Network Analyzer Plot (48-V Input/2.2-A Output)



3 PCB Layout Guidelines

4 PCB EMI Control

PCB Layout Guidelines www.ti.com

The layout of the PoE front end must follow power and EMI/ESD best practice guidelines. A basic set ofrecommendations include:• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,

diode bridges, TVS and 0.1-µF capacitor, and TPS23753 converter input bulk capacitor.• All leads must be as short as possible with wide power traces and paired signal and return.• Signals must not cross over one part of the flow to another.• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input

voltage rails and between the input and an isolated converter output.• The TPS23753 must be located over split, local ground planes referenced to VSS for the PoE input

and to RTN for the converter. Whereas the PoE side may operate without a ground plane, theconverter side must have one. Logic ground and power layers must not be present under the Ethernetinput or the converter primary side.

The DC/DC converter layout can benefit from basic rules such as:• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses which

include the power semiconductors and magnetics.• Minimize trace length of high current, power semiconductors, and magnetic components.• Where possible, use vertical signal pairing.• Keep the high-current and high-voltage switching away from low-level sensing circuits including those

outside the power supply.• Pay special attention to spacing around the high-voltage sections of the converter.

Refer to Designing an EMI Compliant PoE With Isolated Flyback UNPUBLISHED application report(SLUA469) for detailed EMI recommendations. A short list of recommendations follows.• Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).• Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching

nodes (minimize exposed radiating surface).• Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with

ground floods).• Minimize the amount of copper area associated with input traces (to minimize radiated pickup).• Hide copper associated with switching nodes under shielded magnetics where possible.• Heat sink the “quiet side” of components instead of the “switching side” where possible (like the output

side of inductor).• Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane• Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth

ground)• Use LC filter at DC/DC input to suppress high-frequency ringing on the switching nodes.• Control rise times with gate drive resistors and drain snubbers.• Use an EMI bridge capacitor across isolation boundary (isolated topologies).• Observe the polarity dot on inductors (embed noisy end).• Use common-mode inductors or ferrite beads in a common-mode filter fashion on the input.• Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as

boundary line).• Balance efficiency vs acceptable noise margin.• Consider the end-product enclosure and shielding with respect to input signal routing and filtering.


http://www-s.ti.com/sc/techlit/SLUA469


5 Conclusion

6 References

www.ti.com Conclusion

This application report outlines the steps to design a simple flyback converter using the TPS23753. Thedesign procedure outlined along with the included layout guidelines allows easy and accurate circuitdesign using the TPS23753.

1. TPS23753, IEEE 802.3-2005 PoE Interface and Isolated Converter Controller data sheet (SLVS853)2. TPS23753EVM-001 Evaluation Module for TPS23753 User's Guide (SLVU246)3. Compensating the (often missed) Inner and Outer Control Loops using the TL431 by Robert Kollman

and John Betten. Power Electronic Technology Conference, Power Systems World 2002, Chicago4. Practical Guidelines to Designing an EMI Compliant PoE Powered Device with Non-Isolated DC/DC

application report (SLUA454)5. Designing an EMI Compliant PoE Powered Device with Isolated Flyback application report (SLUA469)


http://www-s.ti.com/sc/techlit/SLVS853

http://www-s.ti.com/sc/techlit/SLVU246




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Designing with the TPS23753 Powered Device and Power