Design’Paradigmsof’ Intelligent’Control’Systemson’a’Chipusers.ntua.gr/kdelip/resources/pdf/PACET2009-Presentation.pdf · ip_data s el op_ data U9 aph _v ip d at mf_param

Design Paradigms of Intelligent Control Systems on a Chip

K. M. Deliparaschos and S. G. Tzafestas

Intelligent Automation Systems Research Group School of Electrical and Computer Engineering, NTUA

PACET 20-23 March 2009

2

Outline of Talk

BackgroundFPGA Design FlowDFLC CoreDLFC “Odd-Even” CoreGA CoreSoC for Robot Path TrackingConclusions

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Background

Field Programmable Gate Arrays (FPGAs) contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"Using Hardware Description Languages (HDLs) such as VHDL and Verilog one can configure these logic blocks to perform complex logic structuresMany pre-written FPGA generic component cores exist that allow implementing processors, multipliers, video/audio converters, network protocols, etcSo an FPGA is extremely flexible when it comes to designing a complex systemFPGA technology is being used in several application fields such as telecommunications, signal and image processing, medical equipment, automotive applications, robotics, space landing crafts, just to name a few

4

Outline of Talk


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FPGA Design FlowESL Design

HDL RTL Coding Testbench

Logic Synthesis

Behavioral (RTL)

Simulation

Translation

Map

Place & Route

Synthesis Optimization

Place & Route Optimization

Timing (Gate-Level) Simulation

ConfigurationFile

ConfigureDevice

In-circuit Verification

Static Timing Analysis

Description Test vectors

ESL DesignHDL RTL CodingRTL SimulationSynthesisImplementationDevice Configuration

6

Outline of Talk


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DFLC CoreT-S fuzzy controllers provide an effective representation of complex nonlinear systems in terms of fuzzy sets and fuzzy reasoning The T-S method is considered a quite simple method, leads to fast calculations and is relatively easy to apply. A fuzzy controller based on the T-S method provides a good trade-off between the hardware simplicity and the control efficiency In the T-S inference rule, the conclusion is expressed in the form of linear functions Rules have the following form:

Rule Ri: IF x1 IS A1iAND … AND xk IS Aki THEN yi = c0i + c1i x1 + … + cki xk

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DFLC CoreThe deffuzified output is the weighted average of the contribution of each rule

1

1

m i i

im i

i

w yy

w=

=

∑=

∑

where wi is the weight contribution of the left part of the ith rule and for theAND method connection is given by

1

( )ik

ni

kAk

w xµ=

=∏1

min ( )ik

ni

kAkw xµ

==or

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DFLC Core

Takagi-Sugeno 0-order TypeFully parametric coren No. of Inputsn Input/Output resolutionn Rule connection/Implication methodn Triangular/Trapezoidal Arithmetic or LUT based MFsn Arithmetic or LUT based Divisionn No. of pipeline stagesActive rule selectionInput data rate of 2n clocks

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DFLC Core (cont.)

U10

ip_data

selop_data

U9

alpha_valip_data

mf_param

U5

x_signed

x_unsigned

PSR2

CPR3CPR4

U11

ip_dataop_data

U1

ip_datafs_start_addr

addr_gen_pip_data

rst_nclk

int_zer

U3

addr_in addr_out

CPR1

PSR1

PSR3

cons_map_pU2

ars_p

trap_gen_prule_sel_p

mult

DCM

clkxclkdv

clkrst_n

andor_meth_p

CPR2U4

dataaddrs_rom_p

mf_rom_pdata addr

U8

gen_addr

CPR5

y

CPR6

U12

yclk

xrst_n

clear

int_unsCPR7

CPR8U6

yclkx

rst_n

clearint_sig

U7

opYXdiv_array

U13

opdivsdivddiv_ppa

IF*

rst

Clock management

Fuzzyfication Area Inference Engine Area

Defuzzyfication Area

Divider type selection

Note: CPR{1,9}, PSR{1,3} Register delays (R{1,2}), clocked

by clkx. All reset by rst_n.

R2

clk

rst

R1ip0ip1

ip2ip3 op

clkxrst_n

*IF GENERATE Statement

CPR9

48

12

12

1

12

160

48 32

32

12 12

32 32

1616

16

8

8

21 21 25

25

12

12

1212**

**truncated to 12 bits

clkxrst_n

Top structural design on FPGA Chip

clkd

rst_nclkm

ready_in

control_logic_pclkdv

rst_nclkx

ready_out

r_in

r_out

1

1

Top Structural DFLC Parameterized Soft Core IP Design

U0

(U1)

U2

4 inputs/12-bit, 1 output/12-bit7 Triangular Antecedents MFs/Input with 8-bit Degree of Truth resolution and Overlapping degree of 22401 Singleton Consequent MFs with 8-bit Degree of Truth resolutionRule base with 2401 RulesMinimum, AND MethodProduct, Implication MethodWeighted Average Defuzzification Method

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DFLC Core (cont.)For each new data set identifies and processes only 16 active rules.100 MHz Core frequency operationA new valid data set is given at the output every 16 clocks or 160 ns

12

Outline of Talk

BackgroundFPGA Design FlowDFLC Core (1)DLFC Core (2)GA CoreSoC for Robot Path TrackingConclusions

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DFLC Core (2)

Inherits the characteristics of DFLC Core (1)Takagi-Sugeno 0-order TypeFully parametric coreActive rule selectionImproved input data rate of 2n/2 clocks with “Odd-Even” method

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DFLC Core (cont.)

2 inputs/8-bit, 1 output/12-bit7 Triangular Antecedents MFs/Input with 8-bit Degree of Truth resolution and Overlapping degree of 249 Singleton Consequent MFs with 8-bit Degree of Truth resolution49 RulesMinimum, AND MethodProduct, Implication MethodWeighted Average Defuzzification Method

Active Rule Selector

Address Generator

ip0 ip1

region bus

ars gen bus region gen bus

consequent mapper

singletons ROM

odd even

srom ip odd srom ip even

odd even

sel odd sel even

alpha0 odd alpha1 alpha0 even

ars bus

MIN

odd even

active bus evenactive bus odd

Multiplier even Adder unsignedMultiplier odd

theta odd theta evencns odd cns even

Integrator unsignedAdder signed

implication odd implication even theta

is onereciprocal LUT

divisor

Integrator signed

implication

Multiplier

divident reciprocal

fix output

mul

one flag

op

clear int

Fuzzification &

Aggregation

Inference &

Defuzzification

8 8

12 4

1

9 3

6 6

4 4 4

2 2

8 8

8 8 4 4

13 13 5

14 6

1517

1

33

12

Trapezoidal Generator (x3)

Differencesigned

parameterMemory Banks

MembershipFunctionMultiplier

Fixalpha

Pipeline stages

Rule Selector

ip bus

Divider Block

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DFLC Core (cont.)

For each new data set identifies and processes only 4 active rules.200 MHz Core frequency operationA new valid data set is given at the output every 2 clocks or 10 ns

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Outline of Talk


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GA Core

Genetic Algorithms (GAs), initially developed by HollandThey are based on the notion of population individuals (genes/chromosomes), to which genetic operations as mutation, crossover and elitism are appliedGAs obey Darwin’s natural selection law i.e., the survival of the fittestGAs have been successfully applied to several hard optimization problems, due to their endogenous flexibility and freedom in finding the optimal solution of the problem The most serious drawbacks of software-implemented GAs are both the vast time and system resources consumption

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GA Core

Fully Parametric CoreChromosome length (bits)Fitness value bit resolutionPopulation sizeRandom number resolution (bits) in RWS algorithmNumber of elite childrenMutation rate

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GA Core

Chromosome length = 16-bitFitness value resolution = 16-bitPopulation size = 32Random number resolution in RWS algorithm = 4-bitNumber of elite children = 2Mutation rate = 80

Performance evaluation of the GA using the TSP

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GA Core

Software vs. Hardware implementation GA for the TSP problem

GA version Time (ms)Hardware (clk =10.8 ns) 1.702Software (Pentium 4 3.2Ghz 1Gb

RAM)18,783

A performance evaluation of the GA using the TSP (TSPLIB benchmark function, burma14), has been performed by comparing the time needed to find the optimal solution using the software version vs. the hardware implementation The Results for eight cities, 60 generations and 32 individuals show a speedup ratio of 11,035

21

Outline of Talk


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SoC for Robot Path Tracking

Differential-drive Pioneer 3-DX8 mobile robotLaptopDifferential GPSFPGA board hosting the SoCn DFLC Coren Microblaze Processor

The system consists of four modules tied together

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SoC for Robot Path Tracking (cont.)

The SoC implements the autonomous control logic of the P3 robotIt receives odometry information from the robot and issues steering commands outputted by the FL tracker realized by the DFLC CoreSeveral other tasks realized by the SoC besides the steering control include:n Decoding the information packets sent by the robot which include the pose estimation done by the robot and the status of the motors

n Encoding the steering commands in a data frame that is accepted by the robot

n Relaying critical information to a MATLAB monitoring appication that has been developed

The top-level program that attends to all these tasks and also handles synchronization and timing requirements is written in C and executed in the Microblaze processor core.

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SoC for Robot Path Tracking (cont.)The architecture of the SoC consists mainly:

n of the DFLC that communicates with the Microblaze processor through the Fast Simplex Bus (FSL)

n the utilized block RAMs (BRAM) through the LMB busn other peripherals such as the general purpose input/output ports (GPIO)n and UART modules via the OPB bus The DFLC incorporates the fuzzy tracking algorithm, whereas the Microblaze processor mainly executes the C code for the flow control

DFLCParameterized Fuzzy Logic Controller Soft Core IP

MicroBlaze Soft Processor

FSL_interface

FSL0 Bus

FSL1 Bus

BRAMLMB Bus

Debug Module

USB UART Module

OPB Bus

GPIO Input Ports (Push Buttons)

GPIO Output Ports (User LEDs)

RS232 UART Module

DDR

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SoC for Robot Path Tracking (cont.)The U_fpga_fc component is embedded in the flc_ip top structural entity wrapper which is compliant with the FSL standard and provides all the necessary peripheral logic to the DFLC soft core in order to send/receive data to/from the FSL bus

U_fpga_fc

rst_nclkip0ip1

op

fpga_fcState Machine

FSL_S_Data32

FSL_ClkFSL_M_FullFSL_RstFSL_S_Exists

FSL_S_Data_r32

GFSL_Clk

GFSL_Rst_nGFSL_S_Data_r

FSL_Rst_n

FSL_Rst_nFSL_Clk

FSL_S_Data_r : (12:23)FSL_S_Data_r : (0:11)

FSL_M_Data_i

FSL_M_Data

1212

FSL_M_Write_sync_proc

FSL_M_Write_i

FSL_ClkFSL_M_Write_cnt

32 FSL_M_Write

FSL_S_Read

FSL_S_Control

FSL_M_Clk

FSL_M_Control

FSL_S_Clk

Top Wrapper (flc_ip)

Process

NC

NC

NC

NC

G

NC

Block magnified below (U_fpga_fc)

Global Connection

No Connection

Combinatorial Logic

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Snapshot of the GUI after an experiment. n The map illustrates part of the 2nd floor of the Electrical & Computer Engineering faculty of NTUA

n The solid line represents the desired path while the dashed line the actual path

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The MATLAB application provides a path for the robot to track. The current application deals only with the path tracking task and since not path planning routine exists, the path is drawn in the application’s GUI by hand as a sequence of points encoded properly and downloaded to the SoCThe SoC begins the tracking control. The program uses a linear interpolation scheme to produce all the data samples of the path under a fixed sampling spacing, i.e., the distance between two sample points on the path is constant The application allows choosing the number of interpolation pointsThe MATLAB GUI depicts the pose of the robot in real time along with other information sent by the SoC. In particular, when the spatial window is of order one, i.e., when only the closest point is considered, the SoC sends the two calculated controller inputs

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UP: The S-shaped path experiment with the reference path (black), the odometry position estimation (blue) and the DGPS estimation (red)DOWN: The straight run experiment with the reference path (black), the odometry position estimation (blue) and the DGPS estimation (red)

-2 0 2 4 6 8 10 12 14-0.5

0

0.5

1

1.5

X (m)

Y (m

)

ReferenceGPSOdometry

0 2 4 6 8 10 12 14 16 18 20-2

-1.5

-1

-0.5

0

0.5

1

X (m)

Y (m

)

GPSReferenceOdometry

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Minimum distance in meters, to the reference path of the GPS and odometry solutions, versus the normalized length

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Normalized length

Min

imum

dis

tanc

e to

pat

h

GPSOdometry

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.2

0.4

0.6

0.8

1

1.2

1.4

Normalized length

Min

imum

dis

tanc

e to

pat

h

GPSOdometry

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The actual system

31

Outline of Talk


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ConclusionsFPGA technology, HDLs and EDA tools in recent years has allowed for the development of high performance intelligent control systems for industrial and robotic applicationsModern EDA software tools are used nowadays by the designers to create, simulate and verify the correct operation of a model of a complex system without the need of committing to hardwareSeveral intelligent control system applications implemented on FPGA chips were presented

n Three parameterized reusable FPGA cores, among them two fuzzy logic controllers [1], [2] ( “Odd-Even” method that achieves a significantly faster data processing rate) and a genetic algorithm processor unit [3], [4]

n Furthermore, a SoC for a path tracking task application on a differential-drive Pioneer 3-DX8 mobile robot [5], [6] that successfully utilizes the previously developed parametric DFLC core interfaced with a soft processor core and other secondary cores

The scalability of the fuzzy logic processor core [1] easily allowed adapting it to the fuzzy tracker model [7] without the need of recoding the core

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References1. K.M. Deliparaschos and S.G. Tzafestas, “A parameterized T-S digital fuzzy logic processor: soft

core VLSI design and FPGA implementation,” International Journal of Factory Automation, Robotics and Soft Computing, vol. 3, Jul. 2006, pp. 7-15.

2. K.M. Deliparaschos, F.I. Nenedakis, and S.G. Tzafestas, “Design and implementation of a fast digital fuzzy logic controller using FPGA technology,” Journal of Intelligent and Robotics Systems, vol. 45, Jan. 2006, pp. 77-96.

3. K.M. Deliparaschos, G.C. Doyamis, and S.G. Tzafestas, “A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation,” International Journal of Electronics, vol. 95, Nov. 2008, p. 1149.

4. K.M. Deliparaschos, G.C. Doyamis, and S.G. Tzafestas, “A parameterized genetic algorithm IP core design and implementation,” in Proceedings of the 4th International Conference on Informatics in Control, Automation and Robotics (ICINCO '07), Angers, France: 2007, pp. 417-423.

5. K.M Deliparaschos, G.P Moustris, and S.G Tzafestas, “Autonomous SoC for fuzzy robot path tracking,” in Proceedings of the European Control Conference 2007 (ECC '07), Kos, Greece: 2007.

6. S.G. Tzafestas, K.M. Deliparaschos, and G.P Moustris, “Fuzzy logic path tracking control for autonomous non-holonomic mobile robots: design of system on a chip,” IEEE Robotics and Automation Magazine (under review).

7. G. Moustris and S.G. Tzafestas, “A robust fuzzy logic path tracker for non holonomic mobile robots,” International Journal on Artificial Intelligence Tools, vol. 14, Nov. 2005, pp. 935-965.

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Thank you for your attention!

Documents

Design’Paradigmsof’ Intelligent’Control’Systemson’a’Chipusers.ntua.gr/kdelip/resources/pdf/PACET2009-Presentation.pdf · ip_data s el op_ data U9 aph _v ip d at mf_param