7/29/2019 Design of Next Generation SoC for Low Power
Applications
2/3
CS-SoC-001
The Problem StatementCustomer wanted a derivative SoC of their
existing design that meets the power and area
targets for the product, such that the product can be targeted
to several low power applicationsin addition to the one that it was
currently being used into. This involved changes to the
architecture and micro-architecture, partitioning the design to
appropriate power domains to
meet the low power requirements of the device, clock generation
logic using frequency scaling
to minimize power consumption, removal of features not being
used, modification to the register
configurations and the analog to digital interface.
The challenge was to setup a complete SoC development team with
the required signal
processing domain experience (the design contained a proprietary
DSP) that can take over the
SoC design, validation, physical design implementation,
post-silicon bring-up and ATE testing
with as minimal support from the customer.How C2SiS HelpedC2SiS
team took complete ownership of the SoC development by working with
the customerproduct marketing team and the design architecture team
and thoroughly understanding theproduct requirements. C2SiS team
quickly ramped up the knowledge on the existing designenvironment
and derived the changes required for meeting the power and area
targets for thederivative SoC.
C2SiS team worked on the following aspects as part of the
design, verification and physicaldesign of the derivative SoC:
Reviews of the design document, register specification and
existing micro-architecturedocument
Modifications to the micro-architecture and register
specification based on the changesplanned for meeting the low power
requirements and area targets for the device
Detailed plan for the RTL changes, verification environment
changes, strategy for theverification of modified features and
Physical Design of the SoC were developed andsigned-off with the
customer
RTL changes to implement the design specification
Extensive lint checks and thorough code reviews
Changes to the verification environment and the test caseso
Addition of monitors, checkers and score-boardo HVL Interface
changes and integration
Development of directed test cases for feature additions and
removalso Synchronization logic across power domains
o Low power verification for appropriate placement of level
shifters and isolationcells
o Power mode verification tests to verify transition between
different power modes
DFT implementation for different testability modeso Core based
DFT strategy implemented taking into account the low power
requirements for the deviceo ATPG for different configurations
and validation Achieved 99% coverage
Synthesis for the design adhering to different power modes and
power domains
7/29/2019 Design of Next Generation SoC for Low Power
Applications
3/3
CS-SoC-001
Physical Design Implementationo Floorplan Partitioning for
different power domains and placement of cells
relative to these power domainso Low power Clock-Tree-Synthesiso
Timing closure for different modes including DFT and voltage
cornerso Physical Verification and tape-out
Post-silicon validation and ATE testing / characterization
Business Impact
Meeting the Performance Specification: C2SiSs team completed the
SoC designsuccessfully meeting the low power specifications and the
area requirements thereby enablingthe customer to target this
product into the highly competitive smart phone market with
therequired product differentiation.
First Silicon Success: C2SiSs team thoroughly understood the
specification of the SoC,diligently created the micro-architecture
and implemented the same along with all the RTL sign-off checks.
The verification experts from C2SiS quickly ramped up on the
understanding of theexisting verification environment, created a
thorough verification plan for the derivative SoC andcompleted the
validation with 100% functional coverage. This thorough
verification acrossmultiple modes ensured that the design had zero
functional bugs in first silicon enabling thecustomer to ship this
product in very high volumes.
TAT Reduction: C2SiS teams product development, low power and
signal processing domainexpertise helped to effectively complete
the design on time meeting the market requirements.
Aggressive delivery schedules and high standards of quality and
technical expertise are someof the challenges that give us an
opportunity to demonstrate our commitment to customer
success.
For further information, please
contact:____________________________________________________________________________Concept2Silicon
SystemsVisit us athttp://www.concept2silicon.comCopyright 2011
Concept2Silicon Systems
All rights reserved.
http://www.concept2silicon.com/http://www.concept2silicon.com/http://www.concept2silicon.com/http://www.concept2silicon.com/
![[Tutorial] NoC the Next Generation of Multi-Processor SoC](https://img.pdfslide.us/doc/110x75/55cf9bb1550346d033a70a13/tutorial-noc-the-next-generation-of-multi-processor-soc.jpg)
