DESIGN OF LOW POWER CMOS BASED DUAL MODE ......LE is mainly used for standard CMOS logic gates, it is also shown to be useful for other logic families, such as the pass transistor

International Conference on Emerging Engineering Trends and Science (ICEETS – 2016)

ISSN : 2348 – 8549 http://www.internationaljournalssrg.org Page 58

DESIGN OF LOW POWER CMOS BASED DUAL MODE LOGIC GATES

P.Pandi selvi 1 M.Sharmila Devi 2 R.Ushanandhini 3 Ms.R.Gowri 4

1, 2, 3-Student Final year (ECE) 4-Asst.Professor (ECE)

1, 2, 3, 4-P.S.R.Rengasamy college of engineering for women

ABSTRACT

The CMOS based dual mode logic gates containing two operating modes: 1) static mode

2) dynamic modes. Features of dual mode logic gates are low power dissipation in static mode

and high performance in dynamic mode. This

methodology is used to minimize the delay and improve the speed of the logic gates and an

additional clocked transistor is used in this

methodology. It provides the very high level of flexibility. The proposed method is going to be

an optimize the power and delay. Sleep

transistor allows the path length minimization, delay optimization and delay estimation for

Dual mode logic gates. This paper represent the power optimization based on the principles of

CMOS based dual mode logic gates. The

efficiency of the proposed methodology is shown in a generic 250-nm process.

Index Terms - Dual mode logic, high

performance, minimize delay, logical effort, low power, optimization.

I .INTRODUCTION:

LOGIC optimization and performance are

basic tasks for digital circuit designers. The logical effort (LE) method was to be presented, for easy

and fast evaluation and optimization of delay in

CMOS logic paths. Because of it‟s the LE method has become a very popular tool for the designing

and developing the purposes and is adopted to be

the basis for several computer-aided-design tools. DML gates are achieved very high speed. Although

LE is mainly used for standard CMOS logic gates, it is also shown to be useful for other logic

families, such as the pass transistor logic. The dual mode logic ( DML ), which is switched between

two modes of operation. It is contained at 1) static

mode and 2) dynamic mode. Static mode is to be stable and it achieves very low power dissipation.

Dynamic mode achieves very high-speed logic mode is not to be on constant one. It will provide

high flexibility. The dual mode logic family cannot

use logical effort methodology.

DML-LE methodology to complete (exact) design of the problems, which can be solved

numerically, and simplifies these troubles to an

effortless and easy computational problem [approximate and semi approximate (SA)

solutions] with a combined sys tematic model. In applications such as carry look ahead adder,

counter, multiplexer, arithmetic and logic unit. The

method of logical effort primarily provides a quick means of estimating the delay of a path of logic

circuits. Sleep transistor techniques are to be used

in this paper to minimizing the delay and improving the speed compare to the dual mode

logic circuits. The objective of this paper is to

develop a simple method for minimizing delays and achieving an optimized number of stages in

logical paths containing CMOS-based DML gates. The static operation of the DML gates is also used

to reduce energy consumption. A general approach

is to optimize the delay for the dynamic mode of operation and operate the system in the static mode

only in stable mode without the more frequency

restrictions. These applications are to be implemented by NAND, NOR and NOT gates in

sleep transistor technique based on the CMOS logic gate circuits. The efficiency of the DML-LE

theoretical optimization is examined for a generic

250-nm process. The paper using for the methodology of dual mode logic gates only for the

reason of reducing the speed and minimizing the

power dissipation when compared to the sleep transistor technique to minimize the leakage power

of the transistor using on S and S` signal. To



represent the S and S` signal is the sleep signal at

the sleep of the transistor. A basic DML gate is collected of any static logic family gate, which can

be a conservative CMOS gate, and an additional

transistor. DML gates have a very simple and intuitive structure, requiring n predictable sizing

methodology to achieve the desired performance.

The DML is to be switched between the two modes of operation: 1) static and 2) dynamic modes. In the

static mode, DML gates achieve very low power

dissipation, with some humiliation in performance, as compared with standard CMOS. On the other

hand, dynamic operation of DML gates achieves

very high speed at the expense of increased power dissipation.

II.DML OVERVIEW

A basic DML gate architecture is composed of a

static gate and an additional transistor M1,whose gate is connected to a large-scale clock signal DML

gates present two possible topologies: 1) Type A

and 2) Type B. In the static mode of operation, the transistor M1 is turned off by applying the high Clk

signal for Type A and low Clk for Type B topology.

To operate the gate in the dynamic mode, the Clk is enabled, allow for two separate phases: 1)

precharge and 2) evaluation. During the precharge phase, the output is charged to VDD in Type A

gates and discharged to GND in Type B gates.

During evaluation, the output is evaluated according to the values at the gate inputs.

clk M1

inputs out inputss out

clk M1

(a) TYPE A (b) TYPE B

DML gates show a very robust operation in both static and dynamic modes under process variation

at low supply voltages. The inherent active restorer

(pull-up in Type A/pull-down in Type B) that also enabled glitch sustaining, charge leakage and

charge sharing mainly achieves the robustness in

the dynamic mode. DML gate can be implemented

in two ways, only one of which is efficient. The privileged topology is such that the precharge

transistor is placed parallel to the stacked

transistors, NOR in Type A is preferred over NAND, and NAND in Type B is preferred over

NOR. The evaluation is to be performing through the parallel transistors and therefore it is faster.

This design allows maximum performance, area,

minimization and improved power efficiency. This method presents many drawbacks, such as the

require of footer/header and harsh glitching. The

static operation of the DML gates is used to considerably reduce energy consumption. To

design a DML gate, the method that is to be follow is to place the pre-charge transistor in parallel to

the stacked transistors of the basic CMOS gate.

Then, the evaluation of the logic will be performed with the parallel transistors that will make the

evaluation process faster.

III.DML NAND, NOR and INVERTER GATES

DESIGN:

The Conventional NAND, NOR and NOT logic

gate design is done using Tanner S-Edit EDA (S-Edit Electronic Design Automation) tool and its

power and performance are establish. In addition,

Dual Mode Logic NAND gate Type A and Type B topologies designed and their power consumption

and performance were analyzed for static and

dynamic modes of operations. To design a DML gate, the method that is

followed to place the pre-charge transistor in equivalent to the stacked transistors of the basic

CMOS gate. Then the estimate of the logic will be

performing with the parallel transistors , which will make the evaluation process faster.

In the DML Type-A Static NAND topology, the switching element is a PMOS transistor connected

parallel to the Pull-up network. The input to the

switching element is a constant low voltage to make it OFF. DML Type-A Dynamic NAND

topology, is that the input to the switching element

Static

logic gate

Static

logic gate



is a clock signal having pre-charge and evaluate

Fig-1: Schematic for type A static NAND

Phase for dynamic mode of operation. In the DML

Type-B Static NAND topology, the switching element is an NMOS transistor connected parallel

to the Pull-down network. DML Type-B Dynamic

NAND topology is that the input to the switching element is a clock signal having pre-charge and

evaluate phase for dynamic mode of operation.

Fig-2: Schematic for type B static NAND

In the DML Type-A Static NOR topology, the

switching element is a PMOS transistor connected

parallel to the Pull-up network The input to the switching element is a constant low voltage to

make it OFF DML Type-A Dynamic NOR

topology, is that the input to the switching element is a clock signal having pre-charge and evaluate

phase for dynamic mode of operation.

Fig-3: Schematic for type A static NOR

In the DML Type-B Static NOR topology, the

switching element is an NMOS transistor connected parallel to the Pull-down network.DML

Type-B Dynamic NOR topology is that the input to

the switching element is a clock signal having precharge and evaluation phase for dynamic mode

of operation.

Fig-4: Schematic for type B static NOR

In the DML Type-A Static NOT topology, the

switching element is a PMOS transistor connected

parallel to the Pull-up network. The input to the switching element is a constant low voltage to

make it OFF DML Type-A Dynamic NOT topology, is that the input to the switching element

is a clock signal having pre-charge and evaluate

phase for dynamic mode of operation.

Fig-5: Schematic for type A static NOT

In the DML Type-B Static NOT topology, the

switching element is an NMOS transistor connected parallel to the Pull-down network. DML

Type-B Dynamic NOT topology is that the input to the switching element is a clock signal having pre-

charge and evaluate phase for dynamic mode of

operation. For static NOT type B , The switching element of NMOS is at logic 1 the output become

complementary. NMOS is at logic 0 output become

on normal. Pull-down network (NMOS) is connected to the ground.



Fig-6: Schematic for type B static NOT

IV.SLEEP TRANSISTOR

The Sleep method is the basic power gating method. The sleep transistors separate the logic

networks and the sleep transistor technique or the

sleep method radically reduces leakage power during sleep mode. The power gated sleep circuit

has two modes of operations: (1) Active mode (2)

Sleep mode. In active mode, the sleep Signal SLEEP of the transistor i.e. PMOS transistor is

held at logic'‟0‟and SLEEP` i.e. NMOS transistor at logic „1‟hence both the sleep transistors remain

ON In sleep mode, the sleep Signal SLEEP of the

transistor i.e. PMOS transistor is held at logic' 1 'and SLEEP` i.e. NMOS transistor at logic "0"

hence both the sleep transistors are turned OFF.

The sleep transistors are turned on during the active mode and they are turned off during the sleep

mode. This technique saves the leakage power

dissipation. In normal mode when the pull down NMOS transistor is in ON state and in the pull-up

network the PMOS sleep transistor is in ON state. During sleep mode, in the pull down network

NMOS transistor is in OFF state and PMOS

transistor is in ON state and in the pull up network, PMOS sleep transistor is OFF and NMOS sleep

transistor is ON. Therefore, in sleep mode state a

PMOS is in sequence with an NMOS in both pull-up network and pull-down network, which reduces

the power dissipation. V.SLEEP TRANSISTOR NAND, NOR and

INVERTER GATES DESIGN

The sleep transistor technique has the

advantage of using the two extra pull-up and two extra pull-down transistors in sleep mode. In

normal mode when the pull down NMOS transistor

is in ON state and in the pull-up network the

PMOS sleep transistor is in ON state.

Fig-7: Sleep for type A static NOR

During sleep mode, in the pull down network

NMOS transistor is in OFF state and PMOS transistor is in ON state and in the pull up network,

PMOS sleep transistor is OFF and NMOS sleep

transistor is ON. Therefore, in sleep mode state a PMOS is in sequence with an NMOS in both pull-

up network and pull-down network, which reduces

the power dissipation.

Fig-8: Sleep for type B static NOR

The sleep NOR gate for low leakage operating

of an inverter. Sleep NOR for active mode is the sleep signal „S‟ held at logic 1 voltage level and

complementary „S` ‟is held at logic 0 voltage

levels. When inverter has to function is stand-by or sleep mode the signal „S‟ is held at logic 0 and

signal „S`‟ is held at logic 1.

Fig-9: Sleep for type A static NAND



The sleep NAND gate for low leakage

operating of an inverter is depicted. During normal operation, the sleep signal „S‟ is held at logic 0

voltage levels and complementary sleep signal „S`‟

is held at logic 1 voltage levels. When inverter has to function in stand-by or sleep mode the signal „S‟

is held at logic 1 and signal „S`‟ is held at logic 0.

Fig-10: Sleep for type B static NAND

Fig-11: Sleep for type A static NOT

Fig-12: Sleep for type B static NOT

VI.GATE DIFFUS ION INPUT TECHNIQUE

GDI technique helps in designing low-power

digital combinatorial circuit by which we can

eliminate demerits of CMOS, PTL techniques. This technique allows reducing power consumption,

propagation delay, and area of digital circuits while

maintaining low complexity of logic design . The GDI cell contains three inputs: 1) G, P and N 2)

Bulks of both NMOS and PMOS are connected to

N or P so it can be randomly biased at contrast with a CMOS inverter. The Gate Diffusion Input

(GDI) technique proposed in which is a kind of

pass transistor logic (PTL) circuit, uses two-transistor cells to implement a logic function with

reduced complexity. The voltage swing of the internal nodes is typically low which reduces the

dynamic power consumption. The GDI technique

allows use of a simple and efficient design algorithm, based on the Shannon expansion. GDI

Technique result is implemented techniques GDI

consumes least power and the least number of transistors. Basic GDI Functions have been

simulated using SPICE and the simulated outputs. CONCLUSION: The result obtained leads to the conclusion that

while operating in the dynamic mode, sub threshold DML gates achieve an improvement in

speed compared to a standard CMOS, where as

dissipating more power and in the static mode, a reduction of power dissipation is achieved, at the

expense of a decrement in performance. The

different methods of power gating applied to the DML logic have reduced the power dissipation

further.LE approach for CMOS-based DML logic networks was presented. The proposed approach

allowed an efficient optimization of DML logic

networks for maximum performance in the dynamic mode of operation, which was the focus of

this paper. DML logic, optimized according to the

proposed LE methods, allowed extended flexibility in optimizing various structures of DML networks.

This optimization utilized the DML inherent properties of considerably reduced parasitic

capacitance and ultralow power dissipation in the

static operation mode.

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DESIGN OF LOW POWER CMOS BASED DUAL MODE ......LE is mainly used for standard CMOS logic gates, it is also shown to be useful for other logic families, such as the pass transistor