Design of Low-phase Noise, Low-power Ring Oscillator for ...€¦ · in data communication that requires low-phase noise performance [1,2]. In an optical communication network as

425IETE JOURNAL OF RESEARCH | VOL 58 | ISSUE 5 | SEP-OCT 2012

Design of Low-phase Noise, Low-power Ring Oscillator for OC-48 Application

Harikrishnan Ramiah, Chong Wei Keat and Jeevan Kanesan

Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia

ABSTRACT

A low-power, low-phase noise, high tuning range, and fully integrated inductorless RC-VCO (voltage-controlled oscillator) for OC-48 application is designed and simulated in standard 0.18 µm CMOS technology. The proposed inductorless RC-VCO has a simulated phase noise of -141 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz, with a bias current of 605 µA and voltage headroom of 1.8 V. It has 50% tuning range at 2.4 GHz of operating frequency and consumes 1.09 mW of power. This RC-VCO shows a figure of merit performance of -208.2 dBc/Hz at the desired frequency.

Keywords:CMOS ring oscillator, Phase noise, Voltage controlled oscillator.

1. INTRODUCTION

A CMOS VCO (voltage-controlled oscillator) which is commonly built using ring structures, relaxation circuits, or an LC resonant circuit are one of the important blocks in data communication that requires low-phase noise performance [1,2]. In an optical communication network as in the OC-48 transceiver application, a clock data recovery unit at the receiver restores the clock from the received data through the integration of phase locked loop (PLL), where a VCO is the heart of the PLL [3]. Ring oscillator finds a wide adaptation due to its system on chip integration, while achieving comparatively wide tuning range with low-voltage headroom consumption. The random fluctuations of the output phase addressed as jitter or phase noise in VCOs outlines a major setback in an efficient design [4]. The existence of various topologies of high-frequency ring oscillators highlight an essential design breakthrough optimizing to the power dissipation, tuning range, and phase noise or jitter.

To overcome the constraint of power dissipation and phase noise, VCOs with reduced number of delay stages and in the operation of sub-threshold region had been widely adapted [5]. Ring oscillator comparatively suffers from high-phase noise degradation respective to the resonant-based RC-oscillator, in the absence of high-Q, frequency selective elements. Ring oscillator with differential delay stages exhibit greater immunity to common mode noise such as the supply disturbance and substrate-induced noise [6].

In the motivation of integrating VCOs with low-power dissipation and low-phase noise, this work presents a three-stage ring oscillator designed and simulated

utilizing 0.18 µm standard CMOS technology, tunable from 1.6 to 2.6 GHz. A wide tuning range is achieved by substituting resistive composite load. Section 2 discusses the proposed structure of the ring oscillator, followed by a brief review on the concept of phase noise estimation in Section 3. The simulated result coupled with the performance comparison respective to the figure of merit (FoM) factor is presented in Section 4.

2. PROPOSED RING OSCILLATOR

2.1 Ring Oscillator

The proposed ring oscillator is fundamentally constructed by cascading series of delay cells, complying with the Barkhausen oscillation criterion of gain and phase shift [7]. Addressing the need of low-voltage headroom design, which leads to the increased delay cell integration, parallel differential amplifier cells are integrated in achieving high-speed operation in the penalty of increased power consumption. Slashing the number of delay cells reflects in a high-speed operation with low-power consumption, added with enhanced phase noise performance [8]. Barkhausen criterion highlights the need of increased number of cascaded differential amplifier based delay cells. Alternatively, the adaptation of partial positive feedback in each stage flexes the stringent requirement of increased number of delay cells integration while achieving low-power, high-speed operation and high level of on chip system integration [5].

Figure 1 illustrates the block diagram of the three-stage feed-forward loop architecture, adapted in this design. The single stage delay cell of the proposed 3-stage ring

[Downloaded free from http://www.jr.ietejournals.org on Wednesday, January 09, 2013, IP: 202.185.106.57] || Click here to download free Android application for thisjournal

https://market.android.com/details?id=comm.app.medknow


Ramiah H, et al.: Ring Oscillator for OC-48 Application

426 IETE JOURNAL OF RESEARCH | VOL 58 | ISSUE 5 | SEP-OCT 2012

oscillator architecture is illustrated in Figure 2, where transistor M1 and M2 generate the partial positive feedback. The partial positive feedback increases the gain of the cell, while providing the necessary delay, satisfying the minimum criterion of oscillation.

The transfer function describing the operation of the delay cells can be approximated as:

H sg Rg R

s C C R g R

sC gm

ma

L gd ma

gd m

( ) =−

+( ) −( )

−

( ) +

1

1 1

1

/

/ (1)

where, gm and gma are the transconductance of M1 - M2 and M1a - M2a, respectively. Cgd is the gate-drain capacitance of M1 - M2 and R is the composite load.

Substituting s=jw in (1), the oscillation frequency is found to be:

w w w= Z P (2)

where,

wP=gm/Cgd and wz=(1‑gmaR)/(CL+Cgd)R

2.2 Phase Noise

The phase noise insights the decision on the tradeoffs of power, area, and noise performance. The phase noise is predicted by the concept of impulse sensitivity function (ISF) [4].

In this method, the input system is injected current pulse at the oscillating node and the corresponding output illustrates the resulting phase shift of the oscillating signal. The resulting input-output transfer function is cyclostationary and changes with the phase of the oscillating signal at the moment of injection but is linear at any given phase instant. The phase noise is estimated through the ISF approximation by plotting the output-referred current noise. The phase noise performance comparison is given by FoM and is expressed as [1].

FoM L fff

PmWm

OSC

m

diss= { }−

+

20 101

log log (3)

where, L{fm} is the phase noise at a given offset, fm and fosc is the center frequency of oscillation. Pdiss is the dc power dissipation.

3. SIMULATION RESULTS

HSPICE simulations were performed adapting transistor models of 1.8V/0.18µm standard CMOS process. Figure 3 illustrates the tuning characteristic of the proposed

Figure 1: 3-stage integrated feed forward loop architecture.

Figure 2: Schematic of a differential single stage delay cell used in proposed ring oscillator.

Figure 3: Simulated frequency characteristic of the RC-vCO.

VCO. The variation of control voltage is between 0.6 to 1.0 V, which results in a respective frequency from 1.6 to 2.6 GHz corresponding to 50% of tuning range, thus encapsulating the OC-48 operating frequency [9].

The differential ring oscillator draws 605 µA of current from 1.8 V supply. The phase noise computed via ISF approximation shows a phase noise of -141 dBc/Hz at 1 MHz offset from 2.4 GHz center frequency. Figure 4 shows the simulated phase noise characteristic.





427IETE JOURNAL OF RESEARCH | VOL 58 | ISSUE 5 | SEP-OCT 2012

Figure 4: Simulated phase noise characteristic of the RC-vCO.

Figure 5: Simulated output power spectrum.

Figure 6: Simulated temperature variation effect.

Table 1: Simulated performance summaryPerformance parameter

ReferenceThis work [3] [10] [11] [12] [13]

Frequency (GHz) 2.4 2.5 2 2.4 1.6 2.45Power (mW) 1.09 10 0.7 15 33 19.2Phase noise @1MHz offset (dBc/Hz)

-141 -80 -90 -97 -102 -96

Technology 0.18 0.35 0.18 0.35 0.12 0.28FoM (dBc/Hz) -208 -124 -157 -153 -151 -151

The output spectrum of the oscillator operating at 2.4 GHz of oscillation frequency is illustrated in Figure 5. The maximum peak is observed at 2.4 GHz of oscillation frequency, with the spectrum of accompanying skirting spurs.

Simulation result confirming good transient stability against temperature variation is illustrated in Figure 6. The circuit is verified across a temperature range of -45°C to 125°C. Figure 6 illustrates the scattered distribution of the transient span at the discrete temperature of -25°C, -15°C, +55°C, +95°C, and +115°C. Over the described temperature span, the average common mode dc is evidently constant in a confined output swing.

To compare the performance of the present work with numerous ring oscillator which had been published, Table 1 enlists the performance comparison with other literature reports. The present oscillator achieves a FoM of -208.23 dBc/Hz, which is superior to the recent published findings. The proposed architecture also reports a significant reduction in power dissipation.

4. CONCLUSION

In this paper, a three-stage differential ring oscillator is introduced. Validation through simulation observes a superior phase noise performance of -141 dBc/Hz while consuming 1.09 mW of power. The differential ring oscillator illustrates a 50% tuning range at 2.4 GHz of operating frequency. The circuit also demonstrates a superior FoM performance in comparison with the reported work over a similar frequency range.

REFERENCES

1. WM Kuo, JD Cressler, YJ Chen, and AJ Joseph, “An inductorless Ka-band SiGe HBT ring oscillator”, IEEE Microwave and wireless Components Letters, Vol. 15, No. 10, pp. 682-4, Oct. 2005.

2. B Shrestha, and N Kim, “Design of Diodes Feedback Differential Colpitts Voltage Controlled Oscillator with Low Phase Noise Based on InGaP/GaAs HBT Technology”, IETE Journal of Research, Vol. 54, No. 5, pp. 364-8, 2008.

3. SB Anand, and B Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data”, IEEE J.Solid-State Circuits, Vol. 36, No. 3, pp. 432-9, Mar. 2001.

4. L Dai, and R Harjani, “Design of low-phase-noise CMOS ring oscillator”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, No. 5, pp. 328-38, May 2002.

5. DP Bautista, and ML Aranda, “A low power and high speed CMOS voltage-controlled ring oscillator” in IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 4, pp. 752-5, May 2004.

6. M Parvizi, A Khodabakhsh, and A Nabavi, “Low-power high-tuning range CMOS ring oscillator VCOs” in IEEE International Conference on Semiconductor Electronics (ICSE), Johor Bahru, pp. 40-4, Nov 2008.

7. J Xu, S Verma, and TH Lee, “Coupled inverter ring I/Q oscillator for low power frequency synthesis” in IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 172-3, 2006.





428 IETE JOURNAL OF RESEARCH | VOL 58 | ISSUE 5 | SEP-OCT 2012

8. HQ Liu, WL Goh, and L Siek, “A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers” in IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2, pp. 1525-8, May 2005.

9. A Momtaz, J Cao, M Caresosa, A Hairapetian, D Chung, and K Vakilian, et al, “A fully integrated SONET OC-48 transceiver in standard CMOS”, IEEE J.Solid-State Circuits. Vol. 36, No. 12, pp. 1946-73, 2001.

10. A Elshazly, and K Sharaf, “2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing” in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3213-6, 2006.

11. Z Shu, K Lee, and BH Leung, “A 2.4-GHz ring oscillator based CMOS frequency synthesizer with a fractional divider dual-PLL

architecture”, IEEE J.Solid-State Circuits, Vol. 39, No. 3, pp. 452-62, Mar 2004.

12. E Tatschl-Unterberger, S Cyrusian, and M Ruegg, “A 2.5-GHz phase-switching PLL using a supply controlled 2-delay-stage 10 GHz ring oscillator for improved jitter/mismatch” in IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 6, pp. 5453-6, May 2005.

13. R Rahajandraibe, L Zaid, VC de Beaupre, and G Bos, “Temperature compensated 2.45 GHz ring oscillator with double frequency control” in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 409-12, June 2007.

DOI: 10.4103/0377-2063.104161; Paper No JR 495_11; Copyright © 2012 by the IETE

AUTHORSHarikrishnan Ramiah received the B.E., M.S. and Ph.D. degrees in electrical and electronics engineering, majoring in analogue and digital IC design from University Science Malaysia, Penang, Malaysia, in 2000, 2003 and 2009, respectively. In the year 2003, he was with SiresLabs Sdn. Bhd, CyberJaya, Malaysia, working on audio pre-amplifier for MEMs ASIC application and

the design of 10Gbps optical transceiver solution. In year 2002 he was with Intel Technology Sdn. Bhd., Penang, Malaysia performing high frequency signal integrity analysis for high speed digital data transmission and developing Matlab spread sheet for Eye diagram generation, to evaluate signal response for FCBGA and FCMMAP packages. Currently, he is a Senior Lecturer in the Department of Electrical Engineering, University Malaya. Dr. Harikrishnan was the recipient of Intel Fellowship Grant Award, from 2000 to 2006. His research work has resulted in several technical publications. His main research interest includes Analogue Integrated Circuit Design, RFIC Design and VLSI system design.

E-mail: [email protected]

Chong Wei Keat received the B.S. degree in electronic engineering from University Malaysia Perlis, Malaysia, in 2008. Currently he is working towards the M.S degree in the University of Malaya, Kuala Lumpur, Malaysia. His current research interest includes analogue and Radio Frequency Integrated Circuit Design.


Jeevan Kanesan received B.S. degree in electrical & electronics engineering from University Technology Malaysia, Johor, Malaysia, in 1999, and M.S. degree and Ph.D. degree in mechanical engineering from University Science Malaysia, Penang, Malaysia in 2003 and 2006 respectively. From 2000 to 2001, he has worked as equipment engineer at Carsem Semiconductor, Ipoh,

Malaysia and IC Design engineer in the thermo-mechanical department, Intel Technology Sdn. Bhd., Penang, Malaysia from 2006 to 2008. He has been with University Malaya, Malaysia as a Senior Lecturer in the electrical engineering department since 2008. His research work has so far generated 20 technical publications. His research interests include CAD of VLSI circuits and design and analysis of algorithms.





Documents

Design of Low-phase Noise, Low-power Ring Oscillator for ...€¦ · in data communication that requires low-phase noise performance [1,2]. In an optical communication network as