Design of behavioural models, transistor level schematic and

simulation benches for innovative analog design flow based on IT /

AIDA-C

Telmo Martins de Oliveira

Thesis to obtain the MSc Degree in

Electrical and Computing Engineering

Supervisors: Prof. Nuno Cavaco Gomes Horta

Prof. Jorge Manuel Correia Guilherme

Examination Committee

Chairperson: Prof. Gonçalo Nuno Gomes Tavares

Supervisor: Prof. Jorge Manuel Correia Guilherme

Member of the Committee: Prof. Pedro Nuno Mendonça dos Santos

May 2016

ii

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iv

v

ABSTRACT

The work presented in this dissertation report belongs to the scientific area of Analog Integrated Circuits

Design and consists on the development of reference voltage buffers with rail-to-rail output for a Pipeline

ADC. The developed circuits give reference voltages of 1.15V and 2.15V fulfilling the demanded

specifications for the well operation of all the conversion chain. The main purpose was to improve the

already developed circuits in order to reduce the power consumption, without jeopardise the remaining

specifications, in all corners and considering the admitted input voltage range. An improvement of 5%

and 11.1% for negative and positive buffers power consumption, respectively, was achieved with a root

mean squared noise below 44μV in both cases in all the simulated situations. The circuits were

developed and simulated in XFAB XH035 technology. As development tools, Cadence© Virtuoso was

used for circuit design and sizing, Mentor Graphics Eldo© for simulation and AIDA-C as an optimization

tool of integrated circuits.

KEYWORDS

Analog Integrated Circuits Design; Automatic Circuit Synthesis; Correlated Double Sampling; Electronic

Design Automation; Operational Amplifier

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RESUMO

O trabalho apresentado nesta dissertação está inserido na área científica do Projecto de Circuitos

Integrados Analógicos e consiste no desenvolvimento de buffers com saída rail-to-rail de tensões de

referência para um ADC Pipeline. Os circuitos desenvolvidos fornecem tensões de referência de 1.15V

e 2.15V cumprindo com as especificações exigidas para o correcto funcionamento de toda a cadeia de

conversão. O objectivo principal deste projecto foi melhorar os circuitos já desenvolvidos no sentido de

reduzir o consumo, sem comprometer as restantes especificações, em todos os corners e considerando

a variação de tensões de entrada admitida. Conseguiu-se uma melhoria no consumo de 5% no buffer

negativo e de 11.1% no buffer positivo, com ruído quadrático médio abaixo de 44𝜇𝑉 em ambos os casos

em todas as situações simuladas. Os circuitos foram desenvolvidos e simulados em tecnologia XFAB

XH035. Como ferramentas de desenvolvimento foram utilizados o Cadence© Virtuoso para o desenho

e dimensionamento do circuito, o Mentor Graphics Eldo© para simulação e o AIDA C – uma ferramenta

para a optimização de circuitos integrados.

PALAVRAS-CHAVE

Amplificador Operacional; Automação do Projeto de Circuitos; Circuitos Integrados Analógicos;

Conversor de Analógico para Digital; Dimensionamento Automático de Circuitos Integrados Analógicos;

Dupla Amostragem Correlacionada;

viii

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ACKNOWLEDGEMENTS

I want to acknowledge my supervisors Doctor Nuno Horta, Doctor Jorge Guilherme and P.A. for this

opportunity, the motivation, guidance and overall for the support when everything seemed to be wrong.

Thanks to all the IT Analog Integrated Systems team: Ricardo Póvoa and Nuno Lourenço for the diligent

support, António Fitas, António Canelas, Márcio, André, David, Ricardo Martins, José, Nuno Machado,

Jonathan and Bruno for the companionship.

Quero agradecer aos meus pais e irmãs por todo o apoio e compreensão demonstrados ao longo deste

período de 6 anos.

Por fim, como não podia deixar de ser, quero agradecer a todos os que me acompanharam e me

apoiaram nesta que foi uma das etapas mais importantes da minha vida:

- Família C2 e associados;

- Caminhada A, GT15;

- Ohana Lim’s Hawaii Kenpo;

- Pessoal de MEFT;

- Pessoal de MEEC;

- Pessoal do CCF e miguxos de Fátima;

x

xi

CONTENTS

ABSTRACT .................................................................................................................................................v

KEYWORDS ................................................................................................................................................v

RESUMO ................................................................................................................................................... vii

PALAVRAS-CHAVE.................................................................................................................................... vii

ACKNOWLEDGEMENTS ............................................................................................................................... ix

CONTENTS ................................................................................................................................................ xi

FIGURES .................................................................................................................................................. xv

TABLES .................................................................................................................................................. xvii

ACRONYMS ............................................................................................................................................. xix

1 INTRODUCTION .................................................................................................................................. 1

1.1 Motivation ............................................................................................................................... 1

1.2 Goals ....................................................................................................................................... 1

1.3 Document Structure .............................................................................................................. 2

2 STATE-OF-THE ART ON OPERATIONAL AMPLIFIERS ............................................................................. 3

2.1. Operational Amplifiers Specifications ................................................................................ 3

2.1.1. Settling Time .................................................................................................................. 3

2.1.2. DC Gain ........................................................................................................................... 4

2.1.3. Gain Bandwidth ............................................................................................................. 4

2.1.4. Offset Voltage ................................................................................................................ 4

2.2. Operational Amplifiers Topologies ...................................................................................... 4

2.2.1. Single-Stage Amplifier .................................................................................................. 5

2.2.2. Operational Transconductance Amplifier ................................................................... 5

2.2.3. Two-Stage Amplifier ...................................................................................................... 6

2.2.4. Telescopic Amplifier ..................................................................................................... 8

2.2.5. Folded Cascode Amplifier .......................................................................................... 10

2.2.6. Double Recycling Folded Cascode Amplifier ........................................................... 12

2.3. Conclusions ......................................................................................................................... 16

3 WORK FLOW ................................................................................................................................... 17

3.1. ELT Devices ......................................................................................................................... 17

3.2. Topologies ............................................................................................................................ 18

3.2.1. Previous Amplifier ....................................................................................................... 18

3.2.2. DRFC Amplifier ............................................................................................................ 20

3.3. Buffers Load......................................................................................................................... 21

3.4. AIDA ...................................................................................................................................... 23

xii

3.4.1. Setup ............................................................................................................................. 24

3.5. Test Benches ....................................................................................................................... 27

3.5.1. OP and AC Analysis .................................................................................................... 28

3.5.2. Transient Analysis ....................................................................................................... 30

3.5.3. OP, AC and Transient Analysis .................................................................................. 32

3.5.4. Input Voltage Range .................................................................................................... 34

3.5.5. Output Voltage Range ................................................................................................. 36

3.5.6. Offset ............................................................................................................................ 37

3.5.7. Unique DC .................................................................................................................... 37

3.5.8. Power Shut Down ........................................................................................................ 38

3.6. Corners ................................................................................................................................. 40

3.7. Conclusions ......................................................................................................................... 41

4 RESULTS – FOLDED CASCODE ......................................................................................................... 43

4.1. VREFP Buffer ....................................................................................................................... 43

4.1.1. MOS operating point ................................................................................................... 44

4.1.2. Power on ....................................................................................................................... 46

4.1.3. Unique DC operating point ......................................................................................... 46

4.1.4. Supply current ............................................................................................................. 46

4.1.5. Power Shut Down Supplied Current and Current Peaks ......................................... 47

4.1.6. Output voltage range .................................................................................................. 48

4.1.7. Input voltage range ..................................................................................................... 50

4.1.8. Offset ............................................................................................................................ 50

4.1.9. Open loop Static gain .................................................................................................. 51

4.1.10. Gain Bandwidth product ............................................................................................. 52

4.1.11. Phase Margin ............................................................................................................... 52

4.1.12. Settling Time ................................................................................................................ 53

4.1.13. Noise ............................................................................................................................. 53

4.1.14. PSRR ............................................................................................................................. 54

4.2. VREFN Buffer ....................................................................................................................... 55

4.2.1. MOS operating point ................................................................................................... 56

4.2.2. Power on ....................................................................................................................... 57

4.2.3. Unique DC operating point ......................................................................................... 57

4.2.4. Supply current ............................................................................................................. 58

4.2.5. Power Shut Down Supplied Current and Current Peaks ......................................... 58

4.2.6. Output voltage range .................................................................................................. 60

4.2.7. Input voltage range ..................................................................................................... 61

4.2.8. Offset ............................................................................................................................ 62

4.2.9. Open loop Static gain .................................................................................................. 62

4.2.10. Gain Bandwidth product ............................................................................................. 63

4.2.11. Phase Margin ............................................................................................................... 63

xiii

4.2.12. Settling Time ................................................................................................................ 64

4.2.13. Noise ............................................................................................................................. 64

4.2.14. PSRR ............................................................................................................................. 65

4.3. Other Results ....................................................................................................................... 65

4.4. Conclusions ......................................................................................................................... 66

5 CONCLUSIONS AND FUTURE WORK .................................................................................................. 69

5.1. Conclusions ......................................................................................................................... 69

5.2. Future Work.......................................................................................................................... 69

REFERENCES .......................................................................................................................................... 71

APPENDIXES ............................................................................................................................................ 75

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xv

FIGURES

FIGURE 1: OUTPUT VOLTAGE RESPONSE ................................................................................................... 3

FIGURE 2: BASIC SINGLE-STAGE AMPLIFIER .............................................................................................. 5

FIGURE 3: OPERATIONAL TRANSCONDUCTANCE AMPLIFIER [3] ................................................................... 6

FIGURE 4: BASIC TWO-STAGE AMPLIFIER .................................................................................................. 7

FIGURE 5: POLES SEPARATION BY ADDING A CAPACITOR [4] ....................................................................... 7

FIGURE 6: TELESCOPIC AMPLIFIER ............................................................................................................. 8

FIGURE 7: ENHANCED TELESCOPIC AMPLIFIER ........................................................................................... 9

FIGURE 8: FOLDED CASCODE AMPLIFIER ................................................................................................. 10

FIGURE 9: EQUIVALENT SMALL SIGNAL CIRCUIT OF A FC ........................................................................... 11

FIGURE 10: INPUT STAGES OF (A) RFC AND (B) IRFC TOPOLOGIES ........................................................... 12

FIGURE 11: DOUBLE RECYCLING FOLDED CASCODE – DIFFERENTIAL STAGE ............................................ 14

FIGURE 12: DOUBLE RECYCLING FOLDED CASCODE – OUTPUT STAGE ..................................................... 15

FIGURE 13: DOUBLE RECYCLING FOLDED CASCODE – BIASING STAGE ..................................................... 16

FIGURE 14: ELT LAYOUT SCHEME [27] .................................................................................................... 17

FIGURE 15: SCHEMATIC OF THE OP AMP SELECTED PREVIOUSLY FOR VREFN BUFFER .............................. 18

FIGURE 16: (LEFT) PIPELINE ADC CHAIN; (RIGHT) SWITCHED-CAPACITOR COMPARATOR ......................... 21

FIGURE 17: TRANSIENT RESPONSES OF THE RC EQUIVALENT LOAD ......................................................... 22

FIGURE 18: NON-OVERLAPPING LOAD CLOCK SIGNALS ............................................................................ 23

FIGURE 19: AIDA OVERVIEW [31] ............................................................................................................ 24

FIGURE 20: AIDA ARCHITECTURE[31] ..................................................................................................... 24

FIGURE 21: EXTRACT OF A .XML SETUP FILE ........................................................................................... 25

FIGURE 22: AIDA’S GUI.......................................................................................................................... 26

FIGURE 23: AIDA'S SIMULATOR INTERFACE.............................................................................................. 26

FIGURE 24: AIDA'S OUTPUT GRAPHIC RESULTS ...................................................................................... 27

FIGURE 25: OP AND AC TEST BENCH ...................................................................................................... 29

FIGURE 26: OP AND AC ANALYSIS EXTRACTION ....................................................................................... 30

FIGURE 27: SETTLING TIME EXTRACTION CODE ........................................................................................ 31

FIGURE 28: INSERTED COMMANDS IN THE NETLIST ................................................................................... 33

FIGURE 29: EXTRACTION CODE ................................................................................................................ 33

FIGURE 30: PART OF THE .XML CODE ...................................................................................................... 34

FIGURE 31: INPUT VOLTAGE RANGE TEST BENCH ..................................................................................... 35

FIGURE 32: INPUT VOLTAGE RANGE EXTRACTION COMMANDS .................................................................. 35

FIGURE 33: OUTPUT VOLTAGE RANGE TEST BENCH ................................................................................. 36

FIGURE 34: OUTPUT VOLTAGE RANGE EXTRACTION COMMANDS .............................................................. 37

xvi

FIGURE 35: OFFSET EXTRACTION WITH MONTE-CARLO ............................................................................ 37

FIGURE 36: UNIQUE DC TEST BENCH ....................................................................................................... 38

FIGURE 37: CLK1, CLK2 AND ON SIGNALS IN PSD TEST BENCH ............................................................. 39

FIGURE 38: PARETO CURVE OF THE POSITIVE VOLTAGE BUFFER ................................................................ 43

FIGURE 39: OVERDRIVE VOLTAGE MARGINS (Y VALUES IN VOLTS) ........................................................... 45

FIGURE 40: VDS VOLTAGE MARGINS (Y VALUES IN VOLTS) ...................................................................... 45

FIGURE 41: SUPPLY CURRENT - SET UP AND SET DOWN (Y VALUES IN AMPERES) ...................................... 46

FIGURE 42: DC UNIQUE OPERATING POINT .............................................................................................. 46

FIGURE 43: TRANSIENTS RESPONSE WITH POWER-OFF AND POWER-ON (W(I_ALIM) IN AMPERES AND OTHERS

IS VOLTS) ................................................................................................................................................ 47

FIGURE 44: OUTPUT ERROR VOLTAGE ...................................................................................................... 49

FIGURE 45: INPUT VOLTAGE RANGE – ALL CORNERS ................................................................................ 50

FIGURE 46: MONTE-CARLO RESULTS (Y VALUES IN VOLTS) ..................................................................... 51

FIGURE 47: PARETO CURVE OF THE NEGATIVE VOLTAGE BUFFER ............................................................... 55

FIGURE 48: OVERDRIVE VOLTAGE MARGINS (Y VALUES IN VOLTS) ........................................................... 56

FIGURE 49: VDS VOLTAGE MARGINS (Y VALUES IN VOLTS) ...................................................................... 57

FIGURE 50: SUPPLY CURRENT - SET UP AND SET DOWN (Y VALUES IN AMPERES) ...................................... 57

FIGURE 51: UNIQUE DC OPERATING POINT ............................................................................................... 58

FIGURE 52: TRANSIENTS RESPONSE WITH POWER-OFF AND POWER-ON (W(I_ALIM) IN AMPERES AND OTHERS

IN VOLTS) ................................................................................................................................................ 59

FIGURE 53: OUTPUT ERROR VOLTAGE ...................................................................................................... 60

FIGURE 54: INPUT VOLTAGE RANGE – ALL CORNERS ................................................................................ 61

FIGURE 55: MONTE-CARLO RESULTS (Y VALUES IN VOLTS) ..................................................................... 62

FIGURE 56: DRFC WITH CLASS-AB OUTPUT STAGE ................................................................................ 77

xvii

TABLES

TABLE 1: STATE OF THE ART OF AMPLIFIERS ........................................................................................... 10

TABLE 2: STATE OF THE ART OF FOLDING CASCODE AMPLIFIERS (PART 1) ............................................... 13

TABLE 3: STATE OF THE ART OF FOLDING CASCODE AMPLIFIERS (PART 2) ............................................... 13

TABLE 4: VARIABLES AND RANGES FOR THE PREVIOUS OPAMP ............................................................... 20

TABLE 5: VARIABLES AND RANGES FOR DRFC OPAMP ............................................................................ 20

TABLE 6: EQUIVALENT LOAD PARAMETERS .............................................................................................. 22

TABLE 7: OP AND AC MEASURES AND SPECIFICATIONS ........................................................................... 28

TABLE 8: TRANSIENT MEASURES AND SPECIFICATIONS ............................................................................ 31

TABLE 9: OP, AC AND TRANSIENT MEASURES AND SPECIFICATIONS ........................................................ 32

TABLE 10: CORNERS LIST ....................................................................................................................... 40

TABLE 11: CONSIDERED CORNERS IN THE VREFP BUFFER OPTI9MIZATION ............................................... 43

TABLE 12: VREFP PERFORMANCE SYNTHESIS ......................................................................................... 44

TABLE 13: IDD – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 47

TABLE 14: IDD – WORST CASE ................................................................................................................ 47

TABLE 15: PSD – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ...................................................... 48

TABLE 16: PSD – WORST CASE .............................................................................................................. 48

TABLE 17: IVR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 49

TABLE 18: IVR – WORST CASE ............................................................................................................... 49

TABLE 19: IVR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 50

TABLE 20: IVR - WORST CASE ................................................................................................................ 50

TABLE 21: OFFSET – MONTE-CARLO RESULTS ........................................................................................ 51

TABLE 22: GDC – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ...................................................... 51

TABLE 23: GDC – WORST CASE .............................................................................................................. 51

TABLE 24: GBW – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ..................................................... 52

TABLE 25: GBW – WORST CASE ............................................................................................................. 52

TABLE 26: PM – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY......................................................... 52

TABLE 27: PM – WORST CASE................................................................................................................. 53

TABLE 28: ST – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ......................................................... 53

TABLE 29: ST – WORST CASE ................................................................................................................. 53

TABLE 30: NOISE – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY .................................................... 53

TABLE 31: NOISE – WORST CASE ............................................................................................................ 54

TABLE 32: PSRR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY .................................................... 54

TABLE 33: PSRR – WORST CASE ............................................................................................................ 54

TABLE 34: CONSIDERED CORNERS IN THE VREFP BUFFER OPTI9MIZATION ............................................... 55

xviii

TABLE 35: VREFN PERFORMANCE SYNTHESIS ......................................................................................... 56

TABLE 36: IDD – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 58

TABLE 37: IDD – WORST CASE ................................................................................................................ 58

TABLE 38: PSD – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ...................................................... 59

TABLE 39: IDD – WORST CASE ................................................................................................................ 59

TABLE 40: IVR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 60

TABLE 41: IVR – WORST CASE ............................................................................................................... 60

TABLE 42: IVR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ........................................................ 61

TABLE 43: IVR – WORST CASE ............................................................................................................... 61

TABLE 44: OFFSET – MONTE-CARLO RESULTS ........................................................................................ 62

TABLE 45: GDC – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ...................................................... 62

TABLE 46: GDC – WORST CASE .............................................................................................................. 63

TABLE 47: GBW – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ..................................................... 63

TABLE 48: GBW – WORST CASE ............................................................................................................. 63

TABLE 49: PM – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY......................................................... 63

TABLE 50: PM – WORST CASE................................................................................................................. 64

TABLE 51: ST – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY ......................................................... 64

TABLE 52: ST – WORST CASE ................................................................................................................. 64

TABLE 53: NOISE – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY .................................................... 64

TABLE 54: NOISE – WORST CASE ............................................................................................................ 65

TABLE 55: PSRR – SUPPLY VOLTAGE AND TEMPERATURE SENSITIVITY .................................................... 65

TABLE 56: PSRR – WORST CASE ............................................................................................................ 65

TABLE 57: CONSIDERED CORNERS IN THE VREFP BUFFER OPTI9MIZATION ............................................... 66

xix

ACRONYMS

ADC Analog Digital Converter

CDS Correlated Double Sampling

Cocn Negative coarse offset input

Cocp Positive coarse offset input

DRC Design Rule Check

DRFC Double Recycling Folded Cascode

ELT Enclosed Layout Transistor

FC Folded Cascode

GBW Gain Bandwidth

GM Gain Margin

GUI Graphic User Interface

LVS Layout versus Schematic

OP Operating Point

OpAmp Operational Amplifier

OTA Operational Transconductance Amplifier

PM Phase Margin

RMS Root Mean Squared

PSRR Power Supply Rejection Ratio

THD Total Harmonic Distortion

TID Total Ionization Dose

Vbg Bandgap Voltage

VCM Common Mode Voltage (1.65V)

VREFP Positive reference voltage (1.15V)

VREFN Negative reference voltage (1.15V)

PVT Process, Voltage and Temperature

xx

1

1 INTRODUCTION

This chapter presents a brief introduction on the importance of the ADC with special emphasis on the

reference voltages for their operation. First the motivation to address the ADC and the need of amplifies

in signal conversion. The goals and achievements of this work are outlined and then the structure of the

document is described.

1.1 Motivation

Analog to Digital Converters – ADC are an essential block in signal processing because in most

applications, the signal acquired by the sensors is converted into digital and only then processed. The

target ADC topology depends on the application accordingly with the resolution and bandwidth desired.

This work is integrated on a Pipeline ADC topology, with a precision of 12 bits and a frequency of 15MHz,

which is included in an on-going project.

Two Folded Cascode topologies were already designed and fulfilling the project specifications.

However, the achieved specifications resulted on a great amount of power consumption. Therefore, the

buffers were re-analysed and optimized with the AIDA-C.

AIDA-C is a tool developed in IT-Lisbon with state-of-the-art multi-objective multi-constraint optimization.

The tool enables the user to have a robust design fulfilling the requirements by considering worst case

PVT corners. The software gives also an accurate circuit’s performance evaluation, since it enables the

usage of common industrial simulators (Cadence Spectre, Mentor Graphics ELDO™ or Synopsys®

HSPICE®).

1.2 Goals

The objective of this work was the improvement of the buffers of the reference voltages addressing to

the optimal sizing of their elements. The chosen ADC topology, well-known for its high bandwidth, has

some drawbacks as the power consumption, delay and add-up of non-linearities over its stages. Since

the whole conversion relies on the accuracy and stability of these voltages, the design of these buffers

must have low-noise and a fast response to input and clock signal changes.

The intention was that the project presented in this thesis would be delivered for a possible

implementation. The following goals were set and were accomplish in order to achieve the proposed:

2

Analyze the state of the art to select the relevant topology: knowing the specifications of

the referred amplifiers, the state of the art topologies were analyzed and their strengths

compared in order to confirm that the used was the one that best fit the requirements.

Simulate and dimensioning the topology: Development of a test bench that allowed the most

general evaluation of circuits performances in order to include in AIDA work flow. Then obtain

a solution that fulfils the specs and reduces the power consumption.

Deliver the design database: Organize the database of the project respecting project norms.

1.3 Document Structure

The document is organized as follows:

Chapter 2 starts by describing an OpAmp. Then a series of OpAmp topologies are studied and

compared in order to choose what fits the best our case study;

Chapter 3 introduces the used tools, the workflow and some of the particularities in this project.

The developed test benches are then presented as all the considered corners;

Chapter 4 presents the obtained results. A description of the obtained results is done along with

the characterization of the amplifiers. In the end these results are compared with the obtained

in other facilities.

Chapter 5 concludes the work, stating some observations about the obtained results and the

performed work. Then, a few ideas are suggested as future work.

3

2 STATE-OF-THE ART ON OPERATIONAL AMPLIFIERS

This chapter starts by presenting some of the specifications that characterize an OpAmp which are

critical in this project. Then some topologies are presented, starting by the simple ones in order to

understand its performance passing to the ones that show more potential of implementation. In the end

some conclusions are presented.

2.1. Operational Amplifiers Specifications

The ADC whole operation relies on the accuracy and stability of the reference voltages. Therefore, the

design of these blocks must have in consideration some requirements in order to guarantee the

fulfilment of the ADC specifications. The requirements for the operational amplifiers are here addressed:

2.1.1. Settling Time

When a change is applied to the input of any system, usually it has a damping oscillation behaviour

which take some time to stabilize. Obviously, this only happens if the system is designed to be stable

with this changes.

Even though the system tends to stabilize, it is still oscillating, therefore a range of values within the

signal must be defined to classify the signal as settled. The settling time, is the time that the output takes

to be within this range since the change was applied to the input.

The change applied to the OpAmps is, usually a step at the input voltage signal. However, in this

application, it is a clock signal change at the load. Figure 1 presents an example of the output response

given two clock signals with a 300𝑛𝑠 period lagged half-period.

Figure 1: Output Voltage Response

The specified value is presented in Settling time.

4

2.1.2. DC Gain

To guarantee a precision of n bits in the ADC, the DC Gain of the reference voltage buffers must be

higher than:

20 𝐿𝑜𝑔10(2n) ≈ 6.02n 𝑑𝐵 (1)

The specified value is presented in DC Gain.

2.1.3. Gain Bandwidth

This specification is commonly used to describe the operational amplifier’s behaviour. In this application,

where the OpAmp is used as a buffer, the gain-bandwidth product is equal to the unity-gain bandwidth.

The GBW value must be calculated and specified to allow the amplifier to operate with its already defined

precision and sampling frequency.

Giving a maximum settling time 𝑡 and the intended precision of 0.5 𝐿𝑆𝐵n, the GBW can be calculated by

(3):

𝑒−

𝑡𝜏 =

0.5

2n⇒ 𝜏 =

𝑡

ln (2𝑛

0.5) (2)

𝐺𝐵𝑊 = 𝐹0.5𝐿𝑆𝐵n

=1

2𝜋 ∗ 𝜏 (3)

The specified value is presented in Gain Bandwidth Product.

2.1.4. Offset Voltage

The voltage offset in the buffers reflects on a reference voltage error, however this error is time

independent which means that it only represents a gain error in the ADC conversion. Therefore, is

acceptable a value higher than LSBn for the offset voltage in this kind of applications.

2.2. Operational Amplifiers Topologies

A series of topologies were taken into account in order to choose one that fits best the demands of this

particular project.

Even though some of the following topologies have been already compared [2], this subchapter focuses

also on the understanding of each of them and on the analysis of different approaches as the

combination of two different stages.

5

2.2.1. Single-Stage Amplifier

The simplest differential amplifier consists only in one differential pair and a current mirror – Figure 2.

Furthermore, an additional element is needed in order to drive the circuit’s transistors.The Mb1 transistor

drives a current according to the bias voltage at its gate, which is divided by 2 in the differential pair.

M4

avdd

M1 M2

agnd

M3

avdd

agnd

agnd

Mb1

avdd

vinn vinp

vb1

agnd

output

Figure 2: Basic Single-Stage Amplifier

Considering 𝑉𝐼𝑁− = 𝑉𝐶𝑀 −ΔV

2 and 𝑉𝐼𝑁+ = 𝑉𝐶𝑀 +

ΔV

2, where Δ𝑉 is the differential voltage at the inputs of

the amplifier, the current driven by Mb1 will be divided asymmetrically. This means that the branch of

the M1 will drive a current 𝐼𝑀1 =𝐼𝐵−Δ𝐼

2, thus 𝐼𝑀2 =

𝐼𝐵+Δ𝐼

2.

The current 𝐼𝑀1 is mirrored in M3 to M4, creating a difference of Δ𝐼 with 𝐼𝑀2. This difference of current is

driven through the output. Thus, the output current is higher when the voltage difference increases,

therefore this amplifier is an OTA – Operational Transconductance Amplifier.

This amplifier wouldn’t suit for this project by far, given the demanding specifications. However it is a

good example to explain the differential pair operation.

2.2.2. Operational Transconductance Amplifier

An OTA can be understood as a voltage controlled current source, since the output current is produced

according to an input differential voltage.

These amplifiers can also be used open-loop due to the possibility to attach a resistance at the output.

This permit to control and define the output voltage, hence maintain the saturation of the output

transistors.

The below presented two-stage OTA works very similarly to the Single-Stage Amplifier. However, in this

case the value of the output current can be controlled by the ratio of 1:k indexing the multiplicity of

transistors at the current mirrors M3-M5 and M4-M6.

6

M3

avdd

M1 M2

agnd

M4

avdd

agnd

agnd

Mb1

vinn vinp

vb1

agnd

M6

avdd

M8

agnd

M7

M5

avdd

agnd

avdd

agnd

k:1 1:k

output

Figure 3: Operational Transconductance Amplifier [3]

This topology enables wide input and output voltage ranges. Its gain and gain-bandwidth product are

given by (4) and (5), respectively:

𝐴𝑉𝐷𝐶 = 𝑘 𝑔𝑚1 (𝑟𝑜6||𝑟𝑜8) (4)

𝑓𝑢𝑛 =

1

2𝜋(𝑟𝑜6||𝑟𝑜8)𝐶𝐿

(5)

Given the previous equations, this topology cannot reach the specifications. Considering (5), the output

resistance should be below 280Ω, where 𝐶𝐿 = 17𝑝𝐹 is the lad capacitance. Considering this resistance

and an 𝐴𝑉𝐷𝐶 = 212 = 4096, the product k gm1 would be too high. The use of this topology is avoided

because the increase of the 𝑘 parameter would increase the power demand as well.

2.2.3. Two-Stage Amplifier

A simple two-stage topology, in Figure 4, is studied in order to understand how adding another stage of

amplification will improve the OpAmp performance in terms of gain and GBW. In this example, the

addition of a capacitor allows the analysis of compensation as well.

The circuit can be understood as a group of 4 parts: the differential pair – M1/M2, a current mirror –

M3/M4, a second stage of amplification – M5 and the bias current devices Mb and M6 that may have

the same bias voltage.

7

M4

avdd

M1 M2

agnd

M3

avdd

agnd

agnd

Mb1

avdd

vinn vinp

vb1

agnd

M5

avdd

Mb2

agnd

agnd

vout

vb2

Cc

Figure 4: Basic Two-Stage Amplifier

The addition of a second stage increases the gain of the amplifier (6), thus the unitary gain-bandwidth

product.

𝐴𝑉𝐷𝐶 = 𝐴𝑉𝐷𝐶1 ∗ 𝐴𝑉𝐷𝐶2 =𝑔𝑚2

(𝑔𝑜2 + 𝑔𝑜4)∗

𝑔𝑚5

(𝑔𝑜5 + 𝑔𝑜𝑏2)=

𝑔𝑚2𝑔𝑚5

(𝑔𝑜2 + 𝑔𝑜4)(𝑔𝑜5 + 𝑔𝑜𝑏2) (6)

The compensation capacitor is placed to improve the phase margin. By pulling left the pole, the second

one is pulled away, thus improving the phase margin. This process, presented in Figure 5 is often called

poles separation.

Figure 5: Poles separation by adding a capacitor [4]

The addition of a capacitor with a resistor is also a common practice that creates a zero in the transfer

function in order to cancel an undesired pole.

8

2.2.4. Telescopic Amplifier

The telescopic topology is the result of increasing the output impedance by adding cascode transistors

to a single stage amplifier. This modification enables a higher gain and bandwidth without a significant

cost of power consumption or speed.

M1 M2

agnd agnd

agnd

Mb1

vinn vinp

vb1

agnd

M8

avdd

M7

avdd

avdd

M6

avdd

M5

avdd

M3

agnd

M4

agnd

ouput

vb3

vb2

Figure 6: Telescopic Amplifier

This topology has a limited output swing that difficulties shorting the input and output in a buffer

application. As a result, it is mostly used in fully-differential applications where the input and output

common mode voltages are different and a small voltage range is applicable.

Even though this topology is advantageous, it is not enough to fulfil the specifications in terms of input

and output range. According with the following equation, it gives a quite narrow window for the output

voltage range, assuming that 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛:

𝑉𝑜𝑢𝑡𝑚𝑖𝑛 = 𝑉𝑑𝑠𝑠𝑎𝑡 + 2𝑉𝑑𝑠𝑚𝑎𝑟𝑔𝑖𝑛 + 𝑉𝑖𝑛 − 𝑣𝑡ℎ𝑁𝑀𝑂𝑆

⇒ 𝑉𝑑𝑠𝑠𝑎𝑡 + 2𝑉𝑑𝑠𝑚𝑎𝑟𝑔𝑖𝑛 = 𝑣𝑡ℎ𝑁𝑂𝑀𝑆 (7)

Therefore, if this topology is applied, a second stage is needed not only to buffer the amplifier, but also

to guarantee the output range. However, in that case, the phase and gain margins, as the bandwidth

will be changed due to the addition of parasitic poles in the circuit.

9

Enhanced Telescopic Amplifier

The previous analysed topology is commonly boosted using sub-circuits which gain is multiplied with

the DC gain of the amplifier, enhancing it and consequently the gain-bandwidth product [2-4].

M1 M2

agnd agnd

agnd

Mb1

vinn vinp

vb1

agnd

M8

avdd

M7

avdd

avdd

M6

avdd

M5

avdd

M3

agnd

M4

agnd

ouput

Figure 7: Enhanced Telescopic Amplifier

However, this enhancement isn’t an advantage by itself if the input/output voltage ranges do not improve

and the gain doesn’t need to be increased.

Table 1 presents a state of the art of these amplifiers where the two FOM are calculated as follows:

𝐹𝑂𝑀1 =

𝐺𝐵𝑊

𝐼𝐷𝐷

∗ 𝐶𝐿𝑜𝑎𝑑 (8)

𝐹𝑂𝑀2 =

𝑆𝑅

𝐼𝐷𝐷

∗ 𝐶𝐿𝑜𝑎𝑑 (9)

10

Table 1: State of the Art of Amplifiers

Work Enhanced Telescopic

[6]

Two-Stage

[7]

Analog Voltage Buffer

[8]

Three-Stage

[9]

FC

[10]

Telescopic

[10]

Enhanced Telescopic

[11]

Two-Stage

[12]

Year 2005 2005 2007 2008 2008 2008 2012 2013

Process (𝒏𝒎) 350 500 350 350 350 350 18 350

Supply Voltage (𝑽)

1.5 ±2.5 1.5 1.5 3.3 3.3 1.8 3.3

Supply

Current(𝒎𝑨) 2.6 0.041 0.188 0.03 4.8 4.8 0.044

Capacitive Load (𝒑𝑭)

2 5 10 500 1.4 1.4 4.5 5

DC-Gain (𝒅𝑩) 92 85.1 100 85.9 86.4 106 78.2

GBW (𝑴𝑯𝒛) 561 6.0 6.8 1.76 350 570 1130 5.82

PM (°) 62 65 59 56 85.6 71.75 64

SR (𝑽/𝝁𝒔) 450 5.2 61.3 0.88 472 832 5.58

Setting time (1%) (𝒏𝒔)

18 1280 14.8 8.6 1440

FOM1 (𝑴𝑯𝒛𝒑𝑭

𝒎𝑨) 432 725 362 29333 102 166 603

FOM2 ((𝑽

𝝁𝒔) 𝒑𝑭/𝒎𝑨) 346 628 3261 14667 138 243 246

𝐹𝑂𝑀1 =

𝐺𝐵𝑊

𝐼𝐷𝐷

∗ 𝐶𝐿𝑜𝑎𝑑

𝐹𝑂𝑀2 =

𝑆𝑅

𝐼𝐷𝐷

∗ 𝐶𝐿𝑜𝑎𝑑

2.2.5. Folded Cascode Amplifier

The folded cascode topology is an improvement of the telescopic amplifier in terms of input and output

voltage ranges. Comparing Figure 6 and Figure 8 is possible to conclude that the voltage swing of the

FC topology is higher than the Telescopic.

M1 M2

agnd agnd

agnd

Mb1

vinn vinp

vb1

agnd

M4

avdd

M3

avdd

M7

agnd

M8

agnd

M10

avdd

M9

avdd

avdd

vb2

M5

agnd

M6

agnd

agnd

vb3

vb4

output

A

B

C

Figure 8: Folded Cascode Amplifier

11

However, it comes with some drawbacks as the loss of gain, speed and power efficiency when

compared with the Telescopic.

Due to 𝑟𝑜9 being in parallel with 𝑟𝑜1 the output impedance will be reduced, meaning that the gain will be

less, when compared with the Telescopic.

Furthermore, the pole in the source of the cascode transistors M3 and M4 is closer to the origin than

that of the Telescopic (M3 and M4). In the FC structure, the mentioned node has its capacitance

increased due to the addition of the 𝐶𝑔𝑑9 and 𝐶𝑑𝑏9. This issue is aggravated when using PMOS input

devices, due to the need of larger PMOS transistors as second current source to drive both currents of

input and cascode devices. Also, lower transconductance of PMOS transistors, as cascode devices,

increases the impedance of the node, which pulls the pole to lower frequencies.

Cdb4

CLA Cdb6 CLB

gd4

gd in rd6

CLCgd8

gm1 Vin gm6 Vb4gm4 Vb3

A B

C

Figure 9: Equivalent small signal circuit of a FC

Similarly to the previous cases, is possible to have PMOS devices instead of the presented NMOS at

the input, which implies to reverse the whole topology. Figure 8 shows a FC, which equivalent small

signal circuit based on [13] is presented in Figure 9.

𝐶𝐿𝐴 = 𝐶𝑔𝑑10 + +𝐶𝑑𝑏10 + 𝐶𝑑𝑏1 + 𝐶𝑔𝑠4 + 𝐶𝑔𝑏4 + 𝐶𝑔𝑑1 (10)

𝐶𝐿𝐵 = 𝐶𝑔𝑑6 + 𝐶𝑔𝑑4 + 𝐶𝐿 (11)

𝐶𝐿𝐶 = 𝐶𝑑𝑏8 + 𝐶𝑔𝑑8 + 𝐶𝑔𝑠6 + 𝐶𝑔𝑏6 (12)

Assuming that 𝑔𝑚 are much larger than 𝑔𝑑, the following transfer function can be extrapolated. Thus the

DC gain is calculated by:

𝐴𝐷𝐶 =𝑔𝑚1

𝑔𝑑6𝑔𝑑8

𝑔𝑚6+

(𝑔𝑑1 + 𝑔𝑑10)𝑔𝑑4

𝑔𝑚4

(13)

and the dominant pole is given by the following equation, where 𝑅𝑜 is the output resistance:

𝑝1 = −

1

𝑅𝑜𝐶𝐿𝐵

(14)

The non-dominant poles are given by:

12

𝑝2 = −𝑔𝑚4

𝐶𝐿𝐴

; 𝑝3 =𝑔𝑚6

𝐶𝐿𝐶

(15)

The effect of 𝑝3 is cancelled out by the zero of the transfer function. Since the 𝐶𝐿𝐴can be dominated by

𝐶𝑔𝑠4, the gate-source capacitance of the cascode transistor, the phase margin which depends strongly

on 𝑝3 is degraded by the parasitic capacitance at this node.

This topology was selected before to perform this operation. Even though, a class AB output rail-to-rail

stage was added to buffer this topology and to enhance its gain, bandwidth and output voltage range.

2.2.6. Double Recycling Folded Cascode Amplifier

The Double Recycling Folded Cascode – DRFC topology [14] presented in Figure 11 and Figure 12 is

an OTA that represents another step over the enhancement of the well-known folded cascode. This

improvement is the result of a series of steps taken in this direction as: the recycling folded cascode –

RFC [15] and the improved recycling folded cascode – IRFC [6] presented in Figure 10.

The devices M9 and M10 in Figure 8 are used only as bias current sources. However they can be

exploited to generate an effective transconductance as proposed for the RFC by R. Assaad et al. in [15].

The RFC represents an improvement in terms of gain, bandwidth and slew rate without demanding extra

power. The improvement is directly related to the ratio between the current mirrors M3a/M3b and

M4a/M4b represented by K. Its value is upper-bounded to guarantee a good phase-margin which is

often an indicator to the transient response of the amplifier. Therefore, regarding this trade-offs, K is

often majored by 3.

M1b

avddvinp

M1a

avddvinp

M2a

avddvinn

M2b

vinn

M12

agnd

M11

agnd

M22

agnd

M21

agnd

M3cM3a

agnd

M4c M4a

agnd

M4b

agnd

M3b

M0

vb0

avdd

agnd

avdd

pfold nfold

K : 1 : M M : 1 : K

vb1

M1b

avddvinp

M1a

avddvinp

M2a

avddvinn

M2b

vinn

M11

agnd agnd

M21

agnd

M3a

agnd

M4a

agnd

M4bM3b

M0

vb0

avdd

agnd

avdd

pfold nfold

K : 1 1 : K

vb1

(a) (b)

Figure 10: Input stages of (a) RFC and (b) IRFC topologies

In the IRFC topology proposed by Y. L. Li et al. [17], two more shunt current sources (M3c and M4c)

are added to the input stage. M13 and M14 are also entailed to match the bias current. This change

allows the use of a higher K factor.

In addition to the already mentioned topologies, a few others strands of the RFC show great

performances which makes them good candidates to fulfil the requirements of this project. These results

are available and may be compared in Table 2 and Table 3. Notice that the missing data wasn’t available

in the referred documents.

13

Compared with all the previous presented structures, the RFC (and its strands) are the ones that present

better performances and power efficiency. However, analysing the following tables and choosing a

topology that would fit the best this project is quite tricky.

Table 2: State of the Art of Folding Cascode Amplifiers (Part 1)

Work FC

[10]

RFC

[15]

RFC

[18]

IRFC

[17]

ISFC

[19]

RFC

[20]

RFC

[21]

Year 2008 2009 2009 2010 2011 2011 2011

Process (𝒏𝒎) 350 18 18 130 65 500 65

Supply Voltage (𝑽) 3.3 1.8 1.8 1.2 1.2 3 2

Supply Current (𝒎𝑨) 4.8 0.8 0.782 0.26 0.402 0.456 0.685

Capacitive Load (𝒑𝑭) 1.4 5.6 3.6 7 5 100 1

DC-Gain (𝒅𝑩) 85.9 60.9 60.91 70.2 63.4 100 63.4

GBW (𝑴𝑯𝒛) 350 134.2 197.2 83 313.4 26.6 236

PM (°) 56 70.6 62.5 70 71.9 60.1 63.6

SR (𝑽/𝝁𝒔) 472 94.1 231.1 21.2 45.6 13.35 19

Setting time (0.1%) (𝒏𝒔)

14.3 11.2 11.6 - 4.2 - -

CMRR

@ DC (𝒅𝑩) - - - - - - 331

Noise (0-100MHz) (𝝁𝑽𝒓𝒎𝒔)

- 48.5 48.48 - - - -

FOM1 (𝑴𝑯𝒛𝒑𝑭

𝒎𝑨) 102.1 938.4 907.8 2235 3898.0 5833.3 344.5

FOM2 ((𝑽

𝝁𝒔) 𝒑𝑭/𝒎𝑨) 137.7 658.7 1063.9 570.9 567.2 2927.6 27.7

Table 3: State of the Art of Folding Cascode Amplifiers (Part 2)

Work DRFC

[14]

DRFC

[16]

IRFC

[22]

ERFC

[23]

FRFC

[24]

Year 2012 2012 2012 2013 2014

Process (𝒏𝒎) 65 90 40 180 18

Supply Voltage (𝑽) 1 1 1.1 1.8 0.6

Supply Current (𝒎𝑨) 0.8 0.22 6.5 0.311 0.0004

Capacitive Load (𝒑𝑭) 10 5 2 15

DC-Gain (𝒅𝑩) 54.5 58 56.3 75 66.1

GBW (𝑴𝑯𝒛) 203.2 231.7 3000 120 0.0828

PM (°) 66.2 40 61 72 76

SR (𝑽/𝝁𝒔) 84.1 1200 55 0.063

Setting time (0.1%) (𝒏𝒔) 10.7 9.7 2.9 - -

CMRR @ DC (𝒅𝑩) - - - 52 -

Noise (0-100MHz) (𝝁𝑽𝒓𝒎𝒔) 25.8 - ~30 - -

FOM1 (𝑴𝑯𝒛𝒑𝑭

𝒎𝑨) 2540.0 5265.9 923.0 1680 3105.0

FOM2 ((𝑽

𝝁𝒔) 𝒑𝑭/𝒎𝑨) 878.5 - 369.2 770.0 2362.5

14

Comparing the circuits by their figure of merit can be helpful since it allows the comparison of different

correlated measures. Since the FOM2 is comparing the slew rate and, in this case, this measure is not

as important as the GBW, only the FOM1 is considered in this comparison. Both RFC [20] and DRFC

[16] present the best FOM1, but the second has a higher GBW and a capacity load closer to the one we

are working with – see Buffers Load. Although the phase margin is quite low, with the reduction of the

GBW and with the addition of a compensation capacitor (if needed), it would be mitigated.

Equations (16), (17) and (18) show how this topology (DRFC) is able to improve this amplifier’s

characteristics when compared with the regular FC:

𝐺𝑚𝐷𝑅𝐹𝐶

= [1 +2(𝐾(2𝑀 + 1) − (𝑀 + 𝑁 + 1))

𝐾 + 𝑀 + 𝑁 + 1] 𝐺𝑚𝐹𝐶

(16)

𝑅𝑜𝐷𝑅𝐹𝐶

= 𝑔6𝑟𝑑𝑠6 ∗ ( [𝐾 + 𝑀 + 𝑁 + 1

𝐾 − 𝑀 − 𝑁 − 1𝑟𝑑𝑠2] | | [

𝐾 + 𝑁 + 𝑀 + 1

𝐾𝑟𝑑𝑠4] ) ||𝑔𝑚8𝑟𝑑𝑠8𝑟𝑑𝑠10 (17)

𝑆𝑅𝐷𝑅𝐹𝐶 =

𝐾(𝑀 + 1)

𝑀 + 𝑁 + 1𝑆𝑅𝐹𝐶 (18)

Assuming 𝐾 = 5, 𝑀 = 2 and N= 1, one is able to increase the transconductance 5.6 times and the slew

rate 3.75 times comparing with the FC, while maintaining the same power consumption.

M13 M23

M1c M2c

vinp vinn

M1b

avddvinp

M1a

avddvinp

M2a

avddvinn

M2b

avddvinn

M12

agnd

M11

agnd

M22

agnd

M21

agndvb1

avdd

agnd

M3d M4dM3cM3a

agnd

M4c M4a

agnd

M4b

agnd

M3b

M0

vb0

avdd

agnd agnd

avdd

pfold nfold

K : 1 M : N 1 : KN : M

Figure 11: Double Recycling Folded Cascode – Differential Stage

15

M10

avdd

M9

avdd

avdd

M8

avdd

M7

avdd

M5

agnd

M6

agnd

ouput

vb3

vb1

nfoldpfold

Figure 12: Double Recycling Folded Cascode – Output Stage

Due to the high impedance ( 𝑅𝑜𝐷𝑅𝐹𝐶) and to the large output capacitance, the dominant pole of the circuit

occurs in its output node. Therefore, the pole frequency is given by:

𝜔𝑝1 =

1

𝑅𝑜𝐷𝑅𝐹𝐶𝐶𝑜𝑢𝑡

(19)

Where:

𝐶𝑜𝑢𝑡 = 𝐶𝐿 + 𝐶𝐷𝐵8 + 𝐶𝐺𝐷8 + 𝐶𝐺𝐷6 + 𝐶𝐷𝐵6 (20)

The 1st non-dominant pole occurs in the node that connects the input stage and the output stage

(similarly to the FC topology):

𝜔𝑝2 ≅𝑔𝑚5

𝐶𝑋

(21)

Where

𝐶𝑋 = 𝐶𝐺𝐷3𝑎 + 𝐶𝐺𝑆5 + 𝐶𝐺𝐷1𝑎 + 𝐶𝐷𝐵3𝑎 + 𝐶𝐷𝐵1𝑎 + 𝐶𝑆𝐵5 (22)

Due to its dependence with M5 transconductance, is possible to manage either the current or the

overdrive voltage in order to improve the circuit phase margin and the gain bandwidth.

Biasing Circuit

The bias circuit presented below was applied by S. R. Patri et al.in [25] in a DRFC topology. The same

circuit was used in this application.

The devices must operate all in saturation region except the M41 in order to perform a Widlar MOS

current source.

16

M32 M33

agnd

M34 M40 M42

M41

vb1

agnd

M43M39M36M35

vb2

M37 M44M38

avdd

vb0

ib

Figure 13: Double Recycling Folded Cascode – Biasing Stage

2.3. Conclusions

This chapter was used to introduce the operational amplifier, some of the specifications that characterize

it in this particular project and some alternatives regarding the applied topology.

The settling time, DC gain and GBW will be specified ahead given ADC characteristics and the

expressions presented in the Operational Amplifiers Specifications sub-chapter.

Besides the topology already implemented before, Table 2 and Table 3 present some RFC variants

among which the DRFC shows a great potential for being applied in this project. A possible solution for

its biasing circuit is also presented.

17

3 WORK FLOW

This chapter starts by presenting the technology in which the project was based on and the used

topologies to fulfil the demands.

The load is briefly described and then AIDA is introduced, followed by a detailed description of the

developed/adapted test benches and how they were applied in order to have the optimum results in

terms of time and resources efficiency.

Lastly, the corner conditions are presented followed by some conclusions.

3.1. ELT Devices

The project where the buffers are integrated must have an extra-care regarding the radiation-hardness,

since it might be used in aerospace applications.

The radiation effects are avoided by the use of ELT devices and by considering a minimum current of

10𝜇𝐴 in each branch of the circuit – which, in this project in particular, won’t affect anything, since the

needed current is higher in every branch.

The ELT is an unusual kind of transistors where its gate is surrounded by its source, avoiding any

parasitic channels. The removal of the parasitic channels eliminates the threshold shift caused ionizing

radiation in the field-oxide.

Furthermore, when considering the layout of the amplifiers, it is a common practice the usage of low-

ohmic guard rings around all the p and n-wells. The ELT with guard-rings in deep submicron CMOS

technologies had been proven to be an extremely tolerant to radiation CMOS device [26].

Figure 14: ELT Layout Scheme [27]

18

The main difference between the usual transistors and the ELT, is the dependence of the width – W on

X and Y diameter, and also on the length – L, as presented in (23). Given the fact that 𝑑𝑥 and 𝑑𝑦 have

the minimum value: 1𝜇𝑚, it is reasonable to consider only one of the variables and left the other with its

minimum value. In this project the y diameter was left as a variable. The other parameters that were left

as variables during the optimization are the length and the multiplicity factor.

𝑊𝑒𝑓𝑓 = 3.3055 𝐿 + 2 (𝑑𝑥 + 𝑑𝑦) − 0.4614𝜇𝑚 (23)

The area occupied by one ELT can be roughly calculated by the following expression obtained by

analysing the Figure 14. Even though this wasn’t a constraint settled before, summing all the ELT’s area

gives an idea of the circuit layout dimension.

𝐸𝐿𝑇𝐴𝑟𝑒𝑎 = (2.7𝜇𝑚 + 2𝐿)(1.7𝜇𝑚 + 2𝐿 + 𝑑𝑦) (24)

3.2. Topologies

Two topologies were considered to be optimized and to fulfil all the settled requirements.

The first topology was the one that had already been chosen before. This would allow a comparison

between the results obtained with a standard work flow and a work flow where AIDA is utilized.

The second topology was the DRFC. Which showed a great balance between all the specifications that

are crucial for this project. Therefore it has potential to fulfil them and to reduce the power consumption

as described to be one of the goals of this project.

3.2.1. Previous Amplifier

M63

avdd

M1000 M2000

agnd

M62

avdd

M127

M110

avdd

M111

avdd

agnd

M272

agnd

M32

agnd

M30

agnd

M38

agnd

M21

M20

avdd

netcascn

avdd

cmfb

bcn1

bccp1

vout1n

M57

M56

vout2 avdd

agnd

R2

C7

R1

C8

vinn vinpbcp2

bccn1

ib

C1

netcascp

Figure 15: Schematic of the op amp selected previously for VREFN Buffer

19

The schematic presented in Figure 15 corresponds to the topology selected before for this project. The

first stage is a FC amplifier and the second is a class AB rail-to-rail output stage.

Two capacitors and two resistors with the same dimensions are placed in series between both stages

to perform frequency compensation.

Second Stage

The output class AB stage are commonly used due to their power consumption efficiency and to their

current handling capabilities which allows them to small resistive loads. The quiescent current, in this

stage must be as low as possible in order to have the best power consumption possible. Moreover, the

class AB control shall be compact to use the least die area possible.

The two common-source connected M57 and M56 are directly driven by two in-phase signal currents.

The gates of these devices are biased by two stacks of diode-connected transistors (not-presented).

The floating class AB control is formed by M20 and M21. The class AB control transistors, the stacks of

diode-connected and the output devices set up two translinear loops that determine the quiescent

current in the output transistors [28].

A drawback of the class AB control is the quiescent current dependence on power supply variations.

These variations affect the translinear loop previously referred by vary the gate-source voltages at the

output transistors, across the finite output impedance of the floating class AB devices.

Dimensioning

The sizing performed before served as starting point for the optimization process. Thus there was no

need to perform a previous dimensioning. However, sometimes the whole optimization process isn’t

enough and the designer has to consider some relations in order to speed it up. These considerations

are presented below.

Assuming that a device is in strong inversion and in saturation:

𝑔𝑚 =2𝐼𝑑

𝑉𝑔𝑠 − 𝑉𝑇𝐻

⇒ 𝑉𝑔𝑠 − 𝑉𝑇𝐻 ≈ √2𝐿

𝜇𝑛𝐶𝑜𝑥

(𝐼𝑑

𝑊) (25)

Under fairly general conditions is acceptable to consider the key parameter𝑓𝑡 given to describe its

achievable GBW.

𝑓𝑡 =

𝑔𝑚

2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑)∝

√𝑊

𝑊 (26)

Given the parasitic poles in the FC topology, described in the Folded Cascode Amplifier sub-section, for

a fixed current, one can decrease the width increasing the 𝑓𝑡, thus pushing away the pole in these nodes.

Furthermore, in order to increase the gain, one has to increase the overdrive voltage, thus the devices

width.

20

The dimensions variation range of each device were set according to its operation. Table 4 presents the

variation range assumed for each device:

Table 4: Variables and Ranges for the Previous OpAmp

Variable Min Grid Max

L_M57 L_M20 L_M272 [𝝁𝒎] 0.35 0.05 2

L_M56 L_M38 L_M110 L_M21 [𝝁𝒎] 0.35 0.05 3

L_M62 L_M30 [𝝁𝒎] 1 0.1 5

L_M1000 [𝝁𝒎] 0.5 0.05 3

dy_M57 dy_M56 dy_M38 dy_M62 [𝝁𝒎] 5 01 15

dy_M110 dy_M21 dy_M272 dy_M20 [𝝁𝒎] 2 0.1 10

dy_M20 [𝝁𝒎] 5 0.1 10

m_M57 m_M56 1 1 50

m_M62 10 1 50

m_M38 10 2 100

m_M8 (or m_M9) m_M21 m_M20 m_C0 1 1 20

m_M1000 40 5 100

L_R1 [𝝁𝒎] 1 1 50

m_C7 m_C8 1 1 40

3.2.2. DRFC Amplifier

In the sub-section Double Recycling Folded Cascode Amplifier the DRFC topology was selected as a

possible solution for this project. However, as explained in this sub-chapter, the topology is merely an

OTA, which means that a buffer is needed as a second stage for the amplifier, similarly to the previous

case. The full amplifier structure utilized in this project is presented in Appendix A (without the biasing

circuit which is already presented in the DRFC sub-section).

Table 5: Variables and ranges for DRFC OpAmp1

Variable Min Grid Max

L_M0 L_M1a L_M57 L_M20 L_M7 [𝝁𝒎] 0.35 0.05 4

L_M56 L_M11 L_M21 L_M3 [𝝁𝒎] 0.35 0.05 5

dy_M0 dy_M1a dy_M57 dy_M20 dy_M7 [𝝁𝒎] 5 01 15

dy_M56 dy_M11 dy_M21 dy_M3 [𝝁𝒎] 2 0.1 10

m_M57 m_M56 m_M3a m_M3b m_M3c m_M3d 1 1 50

m_M62 10 1 50

m_M0 10 2 100

m_M8 (or m_M9) m_M21 m_M20 m_C0 1 1 20

m_M1a m_M1b m_M1c m_M1d 40 5 100

L_R1 [𝝁𝒎] 1 1 50

m_C7 m_C8 1 1 40

1 The same table is available in Appendix A with the circuit.

21

The same considerations regarding the design and the optimization process referred in the previous

topology apply for this case as well. The parameters left as free variables are presented in the Table 5

with their variation range and step values.

Even though this topology was profoundly studied and considered for the fulfilment of this project, its

application got compromised due to some misunderstandings regarding the load block, the clock effects

and thus the settling time and how it was measured. After these mistakes, only the previous FC topology

which had already been developed was considered. However, all the work developed regarding the test

benches and work flow in general proved to be useful

3.3. Buffers Load

The voltage reference buffers load is the whole ADC chain that requires the reference voltages. This

chain is composed by operational amplifiers, resistors and the switch-capacitors that perform the signal

sample & hold before each comparator in every stage as presented in Figure 16. A capacitor of 5𝑝𝐹 is

also added in parallel to simulate the parasitic capacities that may occur.

Figure 16: (Left) Pipeline ADC Chain; (Right) Switched-capacitor Comparator

Due to the switch-capacitors the load changes with the clock signal, which affects the reference voltage.

This changes should be considered in the transient simulations to guarantee the settling time and the

precision of the reference voltage. Furthermore, the amplifier should also be tested regarding both clock

states.

The whole load can be interpreted as a parallel RC circuit to facilitate the understanding of the AC

performance of the amplifier. Therefore, a test bench was created for the load where all its inputs had

the required voltage, while the buffered voltage was cut-off by a switch.

Being this a problem of 2 variables – R and C, two different simulations are considered to compute the

variables. In the first one, only the load itself was considered, in the second, a capacitor of 5𝑝𝐹 was

added in parallel between the buffered voltage node and the ground. These two simulations were

repeated four times: regarding both clock signal stages, that could change the values of the load’s

capacitance, and regarding the two buffered voltages – positive and negative. The obtained transient

simulations are presented in Figure 17 showing the exponential behaviour of a RC system.

Knowing that the time constants of the exponential curves are given by: 𝜏 = 𝑅𝐶 and that its value

corresponds to the abscissas of the point where the curve intersects: 1 − 𝑒−1 = 63.2121% of its ascent

22

or descent, one is in conditions of determine R and C. Considering 𝜏1 and 𝜏2 to be the time constants of

the first and second simulation, respectively, one has:

𝑅 =τ2 − 𝜏1

5𝑝𝐹 (27)

𝐶 =𝜏1

𝑅=

𝜏1

𝜏2 − 𝜏1

5𝑝𝐹 (28)

VREFN Cut-offClock1 = 0Clock2 = 1

VREFN Cut-offClock1 = 1Clock2 = 0

VREFP Cut-offClock1 = 0Clock2 = 1

VREFP Cut-offClock1 = 1Clock2 = 0

Figure 17: Transient Responses of the RC Equivalent Load

With the extracted results of the curves in Figure 17, the following values were calculated:

Table 6: Equivalent Load Parameters

VREFN Cut-off VREFP Cut-off

R C R C

𝛀 𝐩𝐅 𝛀 𝐩𝐅

Clock1 = 0 2299,1 11.760 2298,0 11.720

Clock2 = 1

Clock1 = 1 2299,1 11.760 2298,0 11.720

Clock2 = 0

Considering the obtained results plus the 5𝑝𝐹 capacitor that simulates the parasitic at the output of the

amplifier, the load is approximately equivalent to a parallel of a resistance of 2.3 𝑘Ω and a 16.7𝑝𝐹

capacitor.

23

Even though the switched-capacitors chain is symmetric, the clock signals must be asymmetric to

guarantee the load’s performance avoiding current peaks when switching the capacitors. This is assured

by the non-overlapping of the clock signals. This is represented in Figure 18, where the Clock 2 has a

shorter duty-cycle.

Figure 18: Non-overlapping Load Clock Signals

The figure presented above shows the clock transition that causes a more significant change in the

output referred voltage. Thus this represents the transition where the settling time is measured.

3.4. AIDA

The optimization of the designed circuits was executed using AIDA-C, which is a tool developed in IT-

Lisbon that uses state-of-the-art and innovative techniques. AIDA-C is a multi-objective multi-constraint

optimization tool that enables the user to have a robust design fulfilling the requirements by considering

the typical and worst case PVT corners. The software gives also an accurate circuit’s performance

evaluation, since it enables the usage of common industrial simulators (Cadence Spectre, Mentor

Graphics ELDO™ or Synopsys® HSPICE®).

AIDA-L is a tool that completes AIDA-C, addressing to the layout implementation. It takes as inputs the

devices sizes and corresponding best floorplan template, then it places and routs the devices using an

internal DRC and LVS procedures [21-23]. After being saved, the generated circuit is subjected to a final

physical verification, using an external tool to ensure industrial level DRC, LVS and post-layout

performance compliance.

AIDA-C interacts with AIDA-L’s placer allowing the performing of a floorplan-aware circuit sizing

optimization. This is done during sizing optimization, since AIDA-L is able to generate a floorplan in-the-

loop for any possible sizing solution – Figure 20. Furthermore, the fully automatic router of AIDA-L allows

an accurate estimation of the layout’s parasitic devices, what enables a layout-aware circuit sizing.

24

Analog IC Design Automation

AIDA-L

Layout Generation

DESIGN

Specs. NetlistLayout-guides

AIDA-C

Circuit-LevelSizing

VALIDATION

RE-D

ESIG

N

ELECTRICAL SIMULATOR

SPECTRE®HSPICE® ELDO®

AIDA-AMG

Analog Module Generator

DESIGN KIT

Device ModelsDesign Rules

Figure 19: AIDA overview [31]

Since the goals of this project didn’t include the layout design of the circuit, only AIDA-C was set to run

the optimization.

3.4.1. Setup

The setup of the optimization on AIDA-C is schematized in Figure 20.

OUTPUTS

Sized Circuits

POF

Analog IC Design Automation - Circuit Level Synthesis

DESIGN

Layout-guides

AIDA-AMG

Analog Module Generator

DESIGN KIT

Device ModelsDesign Rules

SIMULATOR

SPECTRE®HSPICE® ELDO®

AIDA-L

Layout Generation

Netlist

Specifications

Graphical User InterfaceSetup

Assistant

Vov=VGS-Vth

ΔSAT=VDS-VDSAT

Constraints & Measures:

Variables:W, L, NFin ger

Draft:

Layout-guides

AIDA design setup

IGate, ISource, IDrain

Ranges, Objectives, ConstraintsMonitor execution

Setup & Monitoring

Optimizer

Gradient Model

W12

(+ )GBW,(+ )

W34

(+ )

L12 L34 Ib

A0,(-) (+ ) (+ )

Rules:

Parameters: c = 0.03

Objective: max(GBW)

Sampling

FACTORIALFRACTIONAL FACTORIAL

LATIN HYPERCUBE

NSGA-II

MOSA

MOPSO

Optimization

KernelEvaluation

Variability:TYPICAL

CORNERS

Layout:GEOMETRIC

PARASITIC

Figure 20: AIDA Architecture[31]

25

Netlist

Each developed test bench was extracted from CADENCE as an ELDO file where all the used circuits

and sub-circuits are defined, the simulations are settled and the parameters left as free variables are

defined in order to compute the simulation. Furthermore, the libraries and the devices models are

already defined as well. However, one has to setup the measure extractions according to their definitions

for each simulation. The optimization process starts by measuring the circuit performances given a

certain sizing. This means that the netlist file must include also a file where the dimensions can be

changed by AIDA.

Given the necessity of a series of test benches for the same circuit, makes more sense separate the

netlist file in different included files instead of compiling everything in one with thousands of lines. Thus

the amplifiers netlist, the extraction code and the sizing parameters were stored in different files allowing

an easier understanding and management of the performed work.

XML Setup File

The .XML setup synthetizes the whole optimization process in one single file – Figure 22. Each test

bench is here defined as all of its measures for typical and/or corner simulations. The sizing parameters

are defined accordingly with the netlist, as their ranges and variation steps. Furthermore, the constraints,

the limits of circuit’s performances and the objectives of its optimization are also settled in this file.

Figure 21: Extract of a .XML Setup File

AIDA-C GUI

The GUI, presented in Figure 22, allows the change of specifications, constraints and targets of the

optimizations, even if they are already defined in the .XML. In addition, the management of previous

designs – Load or Save previous configurations and solutions – is possible as well.

The user can also specify the number of generations and the population size in the GUI. Were population

size is the numbers of elements that are evaluated at each generation (larger populations allow a better

26

exploration of the search space). The number of generations the number of iterations of the algorithm

(larger number of generations allows the elements to evolve better).

Figure 22: AIDA’s GUI

The solution browser setting is an advantage in terms of simulations compared with some other tools

when the circuit’s simulation in different test benches is required or even to simply verify a lot of extracted

measures under certain constrains given a specific sizing. It is also able to perform a sweep of a defined

parameter as shown in the simulator’s interface presented in Figure 23.

Figure 23: AIDA's simulator interface

27

The simulations performed in the solution browser setting can be done while the optimization process

is running. Furthermore, this tool allows the designer to edit the solution using this own expertise to

speed up the optimization process.

Output

The evolution of the optimization is presented in two graphics: the first evaluates the solutions in a

nominal value and give the number of the feasible solutions; the second shows the best solutions

(feasible or not) in a Paretto curve considering the objectives settled for the optimization – Figure 25.

Figure 24: AIDA's Output Graphic Results

3.5. Test Benches

The amplifiers simulation requires the development of suitable circuitry for the measures extractions.

Although some of this test benches had been already developed, its application in AIDA-C design flow

required some changes in order to speed-up the optimization process and obtain a better relation

between obtained results and time needed. In fact, some of this test benches weren’t used in AIDA-C

and allowed only a characterization of the circuits performance.

The used test benches are here listed with a brief description of the each one:

OP and AC - performs OP and AC analysis of the circuit;

Transient - performs a transient analysis during circuit’s operation;

OP, AC and Transient - performs OP and AC analysis in two different points of the transient

simulation;

IVR - performs the input voltage range measure extraction;

OVR - performs the output voltage range measure extraction;

Offset - performs the offset extraction with Monte-Carlo simulations;

Unique DC - allows the verification of the common mode voltage sensitivity and the

unicity of the DC operation point;

Power Shut Down - performs a transient analysis when the circuit is turned on and off.

Moreover, each test bench is explained in detail in the following sub-sections.

28

3.5.1. OP and AC Analysis

The test bench here described performs an operational DC and an AC analysis. The specifications that

must be satisfied are presented below, followed by the description of the setup.

3.5.1.1. Specifications

DC Gain

The DC gain required for a precision of 12 bits calculated by (1) is 73𝑑𝐵. Considering a tolerance of

140%, the gain is specified at 73 ∗ 140% = 101𝑑𝐵 for typical conditions.

Gain Bandwidth Product

Given the settling time and the precision of 12 bits, a 𝐺𝐵𝑊0.5𝐿𝑆𝐵8= 33𝑀𝐻𝑧 is obtained by (3).

Table of specifications

Besides the specifications already settled for this test bench, the remaining were fixed previously. Table

7 presents all the extracted measures in this test bench with their specified values when applicable:

Table 7: OP and AC Measures and Specifications

Measures Specification

Typical Corners

Idd 𝑚𝐴

Device área 𝜇𝑚2

GBW >= 33 33 𝑀𝐻𝑧

GDC >= 101 73 𝑑𝐵

Phase Margin >= 70 65 °

Gain Margin 𝑑𝐵

Noise <= 41 46 𝜇𝑉

PSRR(1MHz) 𝑑𝐵

PSRR(12MHz) 𝑑𝐵

2Offset 𝑚𝑉

Overdrive Voltages >= 40 𝑚𝑉

𝑽𝑫𝑺 Margins >= 100 𝑚𝑉

3.5.1.2. Setup

Netlist

The test bench schematic presented in Figure 25 shows all the required elements to simulate the circuit,

and obtain the most accurate response considering non-ideal effects. The performed simulations

consider the parasitic capacitances, current source block, input path block and circuits load block.

2 In this context the measured offset corresponds to the difference of the DC voltages at the output and

the input. Moreover the random offset is extracted in a test bench detailed in Offset..

29

Figure 25: OP and AC Test Bench

The block regarding the current source – X_POLAR_80u – biases the circuit with a current of

approximately 80𝜇𝐴.This presents a good approach in terms of simulating parasitic and non-ideal

polarizing current values as it is in the corners cases.

The H_ANIF block simulates the reference voltage input path undesired effects.

The circuits load block already detailed in the sub-chapter 3.3 is placed at the output of the amplifier

with all its input signals. In this same node is placed a 5𝑝𝐹 capacitor to simulate the parasitic effects

after-layout at this node.

In all the developed test benches, two different voltage supply sources are used: one to power only the

amplifier and the other to power all the external circuitry. This allows the measurement of the consumed

current. Furthermore, this voltage source has also an AC component that allows the extraction of the

PSRR in this test bench.

A voltage source closes the loop between the negative input and the output to execute the .LSTB

command in ELDO. This allows the evaluation of the loop stability, to obtain the Bode Diagram and to

measure the input referred noise at the output of the load block without having an AC component in the

input voltage source – Figure 26.

30

Extraction

Part of the included file that performs the extraction of each measure is presented below.

Figure 26: OP and AC analysis extraction

After fulfilling all the specifications for the nominal input voltage, this test bench was changed in order

to fulfil the same specifications regarding the input voltage range extremes. This is achieved using the

same command that is used in corners simulations: .ALTER. This command allows the addition or the

change of any parameter, which in this case is the input voltage, allowing also to include these results

in AIDA-C.

AIDA

The optimization process regarding this test bench was set up with a .XML file. The file would be

completed as the specifications were fulfilled and hence the following test benches were added.

The obtained solutions were saved and used as starting points in the next steps of optimization where

more test benches were added.

3.5.2. Transient Analysis

The circuit’s operation trough time is simulated and verified in this test bench. The Settling time is the

only measure specified.

3.5.2.1. Specifications

Settling time

The maximum settling time corresponds to 90% of the semi-period:

1

15𝑀𝐻𝑧∗

1

2∗ 90% = 30𝑛𝑠 (29)

Given the precision of 12 bits and the additional 2 bits regarding parasitic effects pos-layout, the settling

time is measured within a 30𝜇𝑉 window range.

31

3.5.2.2. Setup

Extraction

This test bench presents exactly the same setup as the previous one, however in this case the change

of the clock states is considered during the transient simulation. The clock signal is used to operate the

switched capacitors in the load block, which justifies the oscillation in output signal of the amplifier that

is measured – Table 8.

Table 8: Transient Measures and Specifications

Measures Specification

Stable Output Voltage 𝑉

Slew Rate 𝑉/𝜇𝑠

Settling Time (𝟑𝟎𝝁𝑽) <= 33 𝑛𝑠

Settling Time (𝟔𝟏𝝁𝑽)

The Stable Output Voltage measure is extracted at the end of the clock semi-period, when the signal is

assumed to be already stable.

The extracted measures are performed by the following code segment:

Figure 27: Settling Time Extraction Code

Even though the 𝑙𝑏𝑜𝑢𝑛𝑑 and 𝑢𝑏𝑜𝑢𝑛𝑑 commands are facultative, they advert the user when a measure

exceeds or fall behind the specification. This comes quite handy when one is running a solution using

only Ubuntu’s command prompt.

AIDA

This test bench was included in the .XML file with the previous mentioned. However, this means a

decline in the optimization speed.

Even disregarding the corners simulations, two different setups were required for the whole simulation

of the circuit. Considering that ELDO takes about 60 seconds to setup one test bench and that each

generation required 128 simulations, this means that each generation took 2 more hours only performing

the setup of the test bench netlist (which was actually the same). Thus, the crossover of the two test

benches would be ideal.

32

3.5.3. OP, AC and Transient Analysis

The use the least number of test benches possible is required in order to spend the less time possible

in the optimization process using AIDA. This represents a challenge since each test bench is designed

to do a set of different extractions addressing different simulations as well.

Since the setup of the previous two test benches is the same, it was possible to perform some changes

in the ELDO files regarding the simulations and its extractions to group them in a single one.

3.5.3.1. Specifications

The extracted measures, presented in Table 9 and specifications are the same as the previous two test

benches.

Table 9: OP, AC and Transient Measures and Specifications

Measures Point of Extraction Specification

Idd 2 𝑚𝐴

Device área 2 𝜇𝑚2

GBW 1 and 2 >= 33 𝑀𝐻𝑧

GDC 1 and 2 >= 73 𝑑𝐵

Phase Margin 1 and 2 >= 70 °

Gain Margin 1 and 2 12 𝑑𝐵

Noise 1 and 2 <= 46 𝜇𝑉

PSRR(1MHz) 1 and 2 𝑑𝐵

PSRR(12MHz) 1 and 2 >= 𝑑𝐵

Offset 1 and 2 𝑚𝑉

Overdrive Voltages 1 and 2 >= 40 𝑚𝑉

𝑽𝑫𝑺 Margins 1 and 2 >= 100 𝑚𝑉

Stable Output Voltage 2 𝑉

Settling Time (𝟑𝟎𝝁𝑽) <= 30 𝑛𝑠

Settling Time (𝟏𝟐𝟎𝝁𝑽) 𝑛𝑠

3.5.3.2. Setup

Netlist

The netlist wasn’t significantly changed, even though a few commands should be inserted to allow the

extraction of time-dependent operation and AC measures. As presented below, OP analysis is

performed in the 299ns and 449ns instants of the transient analysis.

33

Figure 28: Inserted Commands in the Netlist

Although this change was successfully done, the inclusion of this test bench in the AIDA-C optimization

represented another issue. That was only solved by updating used the AIDA-C version.

Extraction

In this test bench two different OP and AC analysis are performed, addressing both clock states, in two

different point of the transient simulation – Figure 29.

Figure 29: Extraction code

The extracted measures are presented in Table 9. Considering the two different OP and AC simulations

regarding both clock states, some of the extractions are done twice. In terms of the circuit’s performance

characterization, if the values extracted are different, the worst case will be considered.

AIDA

Part of the .XML file is presented in Figure 30. Some of the changes that took place in this updated

version of AIDA are evident in this new .XML structure.

34

Figure 30: Part of the .XML Code

3.5.4. Input Voltage Range

The voltage range at the input of the amplifiers is evaluated by the test bench here presented.

Since the previous test bench was used to validate the circuits operations within the specified range,

this one was used only to acquire the voltage range without its inclusion in the optimization process..

3.5.4.1. Specifications

The input and output voltage ranges of the negative reference buffer are defined by the following

equations, which was demanded before for the good operation of the whole ADC chain.

Vrefn = VCM(±0.1) − 0.5(23%) (30)

Which means that:

𝑉𝑟𝑒𝑓𝑛𝑚𝑖𝑛 = 0.935𝑉

𝑉𝑟𝑒𝑓𝑛𝑚𝑎𝑥 = 1.365𝑉

Similarly, for the positive buffer, the ranges are defined by:

𝑉𝑟𝑒𝑓𝑛 = 𝑉𝐶𝑀(±0.1) + 0.5(23%) (31)

Thus:

𝑉𝑟𝑒𝑓𝑝𝑚𝑖𝑛 = 1.935𝑉

𝑉𝑟𝑒𝑓𝑝𝑚𝑎𝑥 = 2.365𝑉

3.5.4.2. Setup

Netlist

The input voltage range measurement requires a different netlist setup of the previous test benches.

This setup is presented below, in Figure 31:

35

Figure 31: Input Voltage Range Test bench

Extraction

The input voltage range measured corresponds to the range of the 𝑉𝐼𝑁 voltages that introduce a change

at the output of the amplifier less than 0.1%. According to the following expression, obtained by

analyzing the currents at the 𝑉𝐼𝑁𝑁 node, the output has the same value within the range: 𝑉𝐶𝑀 + 𝐷𝑉𝐼𝑁

because the input voltage source is inverted.

((𝑉𝐶𝑀 + 𝐷𝑉𝐼𝑁) + 2𝑉𝐼𝑁) − 𝑉𝐼𝑁 = 𝑂𝑈𝑇𝑃𝑈𝑇 − 𝑉𝐼𝑁 ⇒ 𝑂𝑈𝑇𝑃𝑈𝑇 = 𝑉𝐶𝑀 + 𝐷𝑉𝐼𝑁 (32)

Therefore, the extraction is performed by sweeping the 𝑉𝐼𝑁 voltage and extracting the range where its

variation is lower than the specified value. Part of the used code is shown in the following image.

Figure 32: Input Voltage Range Extraction Commands

AIDA

As mentioned before, this test bench was not included in the .XML file, thus in the optimization process.

Besides the fact that it would increase even more the optimization time, that was not necessary since

the circuits performed as expected. The same situation happened with the output voltage range test

bench.

36

3.5.5. Output Voltage Range

3.5.5.1. Setup

Netlist

Similarly to the previous case, this test bench requires a distinct setup as well. This setup is presented

in Figure 33. The specified values for the voltage ranges are the same, as mentioned previously.

Figure 33: Output Voltage Range Test bench

Extraction

The setup of the test bench allows the comparison between the real output and an ideal one, where the

effects of a possible offset are mitigated. The voltage range corresponds to the 𝑉𝐼𝑁 voltage values

where the 𝐸𝑅𝑅𝑂𝑅 signal, which is the difference between both outputs, is lower than 0.1%.

Considering an offset of 𝛿, the 𝑂𝑈𝑇𝑃𝑈𝑇 voltage is obtained by considering the currents law at the 𝑉𝐼𝑁𝑁

node which has a virtual 𝛿 voltage:

𝑂𝑈𝑇𝑃𝑈𝑇 = 𝑉𝐼𝑁 + (𝑉𝐶𝑀 + 𝐷𝑉𝐼𝑁) + 𝛿 (33)

While the 𝐼𝐷𝐸𝐴𝐿_𝑂𝑈𝑇𝑃𝑈𝑇 is obtained by performing the voltages law in the ideal voltage-controlled

voltage sources:

𝐼𝐷𝐸𝐴𝐿_𝑂𝑈𝑇𝑃𝑈𝑇 = −(𝑉𝐼𝑁 + (𝑉𝐶𝑀 + 𝐷𝑉𝐼𝑁) + 𝛿) (34)

This means that the 𝐸𝑅𝑅𝑂𝑅 signal, which is in fact the sum of this two signals, should be zero. The code

used to perform the extraction is presented below:

37

Figure 34: Output Voltage Range Extraction Commands

3.5.6. Offset

In this application, a high offset does not compromise the result at the end of the ADC chain, as

explained before. Even though, this measure is commonly extracted using Monte-Carlo simulations,

since it is quite sensitive to local and process dispersions.

This test bench was used to characterize the circuits, thus was not used in the optimization process to

avoid an unnecessary delay.

3.5.6.1. Setup

Netlist

The used netlist was the same as used in the OP, AC and Transient Analysis. However, only the DC

simulation was considered.

Extraction

Only the offset measure is extracted in this test bench. Furthermore, the Monte-Carlo simulation is

performed with 1000 points considering local and local+process uniform dispersions. The extraction

code is presented below:

Figure 35: Offset Extraction with Monte-Carlo

3.5.7. Unique DC

This test bench was used to verify the unicity of the operating point of the amplifier given two different

voltages at the inputs. This allows the analysis of the output voltage behavior and its sensitiveness with

the input voltage difference.

3.5.7.1. Setup

Netlist

The used netlist is presented in Figure 36, where the main changes are the voltage sources at the

inputs. Furthermore this simulation is taken considering all corners and the specified input voltage range.

38

Figure 36: Unique DC test bench

3.5.8. Power Shut Down

At last, the circuit is tested turning it on and off in order to evaluate its transient behaviour, the voltage

and current peaks and the settling times.

As the previous four test benches, this one wasn’t intended to be included in the optimization process.

Not only there aren’t any values specified for the extracted measures but also this operation is assured

by a good design. Even so, the measured values must have reasonable values in order to not

compromise the ADC operation.

3.5.8.1. Setup

Netlist

This test bench uses the same netlist as the presented in Figure 25 in OP, AC and Transient Analysis.

One possible approach, that was in fact applied initially, would be to join this test bench with the one

presented in the OP, AC and Transient Analysis sub-section. However, the measures here performed

aren’t so crucial for the circuits operation as the others. Therefore, the positive effects of joining these

two test benches wouldn’t compensate its drawbacks as the time that a transient simulation takes.

For the same reason, the simulation with this test bench was divided in two different parts: firstly, the

circuit was tested with the power on and off of the supply voltage extracting the graphic results that

characterize its response. Only then the circuit was tested with the variation of the power-up/power-

down signal (“ON”). Doing so avoids the excessive precision when the supply voltage varies during

100𝑚𝑠 speeding up the workflow.

39

Extraction

Firstly, the power supply is turned on during 50𝑚𝑠 and then it is turned off. This simulation is performed

separately regarding the specified rising time for the power supply.

The Figure 37 shows the variation of ON, CLK1 and CLK2 signals through time. A period of 300𝑛𝑠 was

considered for the clock signals. The variation of the ON signal takes a lot longer in order to allow the

stabilization of the operating point of the amplifier in all its nodes.

Figure 37: CLK1, CLK2 and ON Signals in PSD test bench

The extracted measures are listed below:

Peak Current ON - current peaks during nominal operation

Peak Current Power-off - current peak when the circuit is turned off

AVDD Current OFF - supplied current when the circuit is off

Peak Current Power-on - current peak when the circuit is turned on

The settling time of output voltage could be measured when the circuit is turned on at 2𝜇𝑠, if the clock

variations are disregarded. However it wouldn’t be the better and more accurate approach to

characterize the circuits response.

Instead of disregard the clock signals, which would present an erratic transient simulation, the settling

time extraction was disregarded. On the other hand, the output response through time is presented,

which allow also an analyse of its behaviour without a precise time period during which the circuit

stabilizes.

40

3.6. Corners

The designed circuits must perform and fulfil the specifications under previously specified variations of

fabrication, power supply and temperature. Therefore, all the following corners were taken in

consideration in each of the above described test benches.

Table 10: Corners List

Process Power Supply Temperature

V ◦C

wp_avdd_max_dvdd_max_temp_min_1 Worst Power 3.456 -55

wp_avdd_max_dvdd_max_temp_max_2 Worst Power 3.456 125

wp_avdd_min_dvdd_min_temp_min_3 Worst Power 3.135 -55

wp_avdd_min_dvdd_min_temp_max_4 Worst Power 3.135 125

ws_avdd_max_dvdd_max_temp_min_5 Worst Speed 3.456 -55

ws_avdd_max_dvdd_max_temp_max_6 Worst Speed 3.456 125

ws_avdd_min_dvdd_min_temp_min_7 Worst Speed 3.135 -55

ws_avdd_min_dvdd_min_temp_max_8 Worst Speed 3.135 125

wo_avdd_max_dvdd_max_temp_min_9 Worst One 3.456 -55

wo_avdd_max_dvdd_max_temp_max_10 Worst One 3.456 125

wo_avdd_min_dvdd_min_temp_min_11 Worst One 3.135 -55

wo_avdd_min_dvdd_min_temp_max_12 Worst One 3.135 125

wz_avdd_max_dvdd_max_temp_min_13 Worst Zero 3.456 -55

wz_avdd_max_dvdd_max_temp_max_14 Worst Zero 3.456 125

wz_avdd_min_dvdd_min_temp_min_15 Worst Zero 3.135 -55

wz_avdd_min_dvdd_min_temp_max_16 Worst Zero 3.135 125

tm_avdd_min_dvdd_min_temp_typ_17 Typical 3.135 25

tm_avdd_max_dvdd_max_temp_typ_18 Typical 3.456 25

tm_avdd_typ_dvdd_typ_temp_min_19 Typical 3.3 -55

tm_avdd_typ_dvdd_typ_temp_max_20 Typical 3.3 125

Furthermore, the current supplied to the circuit also changes with this environmental variations, since

they affect the current source block as well. Therefore, each corner has its own value for the supplied

current, accordingly.

However, not all of the test benches were included in the optimization process due to time and resources

saving. Only the worst cases were considered and included iteratively for two reasons: firstly, due to

some inability, it was impossible to exclude an already included test bench, and secondly, this way was

faster than simply include all the worst test benches.

41

3.7. Conclusions

In this chapter the core of the performed work was presented. Besides introducing all the tools and

circuits used in the optimizations, the developed test benches were also detailed.

Although the OP, AC and Transient Analysis was in fact the only test bench used in AIDA, it represented

the junction of two different ones previously introduced.

The following test benches served merely to characterize the circuits performance after they were

dimensioned, since the expected results were obtained.

A different approach was applied in the power shut down in order to speed-up the circuits simulation.

Thus, for the same test bench, two different simulations were performed.

In the end, all the corners within the circuits must operate were presented.

42

43

4 RESULTS – FOLDED CASCODE

The results of the optimization taken by AIDA for the previous used amplifier are here presented. These

results include the considered corners in the optimization, its POF and the performance regarding all

the test benches mentioned in the previous chapter. The results are presented for both buffers following

the same structure as presented in the reports regarding the previous amplifiers.

4.1. VREFP Buffer

The circuit was optimized with AIDA-C considering only the test bench presented in OP, AC and

Transient Analysis. This optimization was performed during 5 weeks (approximately) while the following

test benches were added to this process.

Table 11: Considered corners in the VREFP Buffer opti9mization

Corner Input Voltage

wp_avdd_max_dvdd_max_temp_min_1 2.365

ws_avdd_max_dvdd_max_temp_max_6 2.365

ws_avdd_min_dvdd_min_temp_max_8 2.365

wz_avdd_max_dvdd_max_temp_max_14 1.935

wz_avdd_min_dvdd_min_temp_min_15 2.15

Figure 38: Pareto curve of the positive voltage buffer

44

Every time a few new solutions were got, these solutions were tested in all the corners. While it didn’t

fulfil all the corners and all the extremes of the voltage range, the worst corner was added, or the input

voltage was changed.

Table 11 presents all the considered corners at the end of this process. However in this case the GBW_2

wasn’t fulfilled for all the corners and a few more specs weren’t achieved in the voltage extremes. This

is detailed in Appendix D. One of the obtained Pareto’s curve is shown in Figure 38. After testing all the

obtained solutions and enhance the demand of the optimization, a better solution was not found for 2

weeks straight.

The obtained results addressing the positive voltage reference buffer are presented below for each

measures that characterize it.

For each measure, the range extremes of its values is presented, indicating also the conditions where

they occur. Moreover the sensibility of each measure regarding the temperature and VDD range

variations are also presented.

The circuit’s devices dimensions are presented in Appendix C. The obtained results addressing the

positive voltage reference buffer are here presented for each one of the specified and non-specified

measures.

Table 12: VREFP performance synthesis

Parameters Unit Spec Min. Typ. Max.

Functional verification

SET OK

MOS operatring point OK

Peak current 𝑚𝐴 5.455 7.090 8.492

Unique DC operating point OK

Static performances

Supply current 𝑚𝐴 3.5 4.0 4.8

Input voltage range 𝑉 <1.935 >2.365

0.68 - 3.4

Output voltage range 𝑉 <1.935 >2.365

0.003 - avdd

PSRR (1Hz) 𝑑𝐵 36.6 40.6 45.3

Dynamic performances

Static gain 𝑑𝐵 >70 108.2 111.9 113.3

Gain Bandwdth product 𝑀𝐻𝑧 >33 32.5 54.3 111.7

Phase margin ° >65 65.5 70.4 79.4

Settling time 𝑛𝑠 <30 14.4 18.1 24.7

NRMS 𝜇𝑉𝑚𝑟𝑠 <46 32.7 37.9 40.1

PSRR (12MHz) 𝑑𝐵 15.0 19.0 23.7

4.1.1. MOS operating point

The operation point of the amplifiers are guaranteed within typical conditions. Even though the circuit’s

operation isn’t affected in all corners solutions, in some of them the margin voltages aren’t completely

fulfilled. This situation is presented in the following figures, where the voltage margins of each device

are presented in all corners.

45

The overdrive voltage isn’t above 40mV only in the M43 device in both 9th and 11th corners:

Figure 39: Overdrive Voltage Margins (Y Values in Volts)

The M27 device 𝑉𝑑𝑠 margin isn’t fulfilled in the 2nd, 4th, 10th and 12th corners:

Figure 40: Vds Voltage Margins (Y Values in Volts)

The obtained operating points in all the corners are not ideal since the margins are not fulfilled in the

tested conditions. However, the circuit’s operation is still uncompromised which makes this results

acceptable and reliable.

46

4.1.2. Power on

During the 50𝑚𝑠 that the power supply takes to set up and to set down the circuit was tested. The

graphic results of the supplied current are presented below :

Figure 41: Supply current - Set up and set down (Y Values in Amperes)

4.1.3. Unique DC operating point

The circuit’s operations is verified for all the corners and input voltages. The result of the DC sweep of

the VINP voltage is presented below. Furthermore, the graphic here presented assumes the same

shape as the one obtained with the previous sizing, which proves that the circuit is operating as expected

and has an unique DC point for each of the input voltages within the acceptable range.

Figure 42: DC Unique Operating Point

4.1.4. Supply current

The consumed current and its variation in the different corners is detailed in the following tables:

47

Table 13: IDD – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

CONSO_1 4.0 4.0 4.0 4.4 4.0 3.8 𝑚𝐴

Table 14: IDD – Worst case

Measure Process Supply Temperature Worst Case Result Unit

CONSO_1 WS min MAX 3.5 𝑚𝐴

WP MAX min 4.8 𝑚𝐴

With this re-sized solution, the consumption is 11.1% below the previous 4.5 mA in typical conditions.

The consumption variation with the temperature has also an atypical behaviour, since it decreases with

the temperature. Meanwhile, the supply voltage sensitivity is almost inexistent.

Furthermore, the range of variation of this spec is lower than the achieved before, where the maximum

value was 5.2 mA.

4.1.5. Power Shut Down Supplied Current and Current Peaks

The transient response of the circuit when it is turned off and on is presented in Figure 43. The clocks

and ON signals are also presented allowing to justify the current and output voltage responses:

Figure 43: Transients response with power-off and power-on (W(I_ALIM) in Amperes and others is Volts)

48

Table 15: PSD – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Units Supply Voltage Sensitivity Temperatue Sensitivity

3.135 3.3 3.465 -55 25 125

Peak Current ON 6.937 7.090 7.252 7.559 7.090 7.051 𝑚𝐴

Peak Current Power-off 6.656 6.759 6.870 7.504 6.759 6.322 𝜇𝐴

AVDD Current OFF 1.438 1.402 1.372 1.338 1.402 1.530 𝑚𝐴

Peak Current Power-on 5.871 5.967 6.042 7.196 5.967 5.463 𝑚𝐴

Table 16: PSD – Worst case

Measure Process Supply Temperature Worst Case Result Units

Peak Current ON WS min MAX 5.455 𝑚𝐴

WP MAX min 8.492 𝑚𝐴

Peak Current Power-off WS min MAX 651 𝑛𝐴

WP MAX min 2.045 𝜇𝐴

AVDD Current OFF WP MAX min 4.934 𝑚𝐴

WS min MAX 7.896 𝑚𝐴

Peak Current Power-on WS min MAX 2.060 𝑚𝐴

WP MAX min 7.479 𝑚𝐴

The results obtained addressing to the worst cases are presented in the previous two table. Although

this measures were not specified before, the measured values must have the same magnitude as the

previously extracted. However, the values were presented are in general higher. The measured current

when the circuit is off is particularly higher than the previously dimensioned circuit presenting a serious

disadvantage comparing both dimensioning..

4.1.6. Output voltage range

The “ERROR voltage” signal obtained in this test bench is presented in Figure 44, where the “X Value”

in the graphic corresponds to a DC sweep of the output voltage while the input is keep constant. The

output voltage range is tested not only for the typical input voltages but also considering the extremes

of the specified voltage range. In all the analysed cases, the specification is fulfilled.

49

Figure 44: Output error voltage

The output voltage ranges corresponding to variations of 1% and 0.1% are presented in the following

tables considering only the typical input voltages:

Table 17: IVR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

VOUTMIN_1% 3.4 3.3 3.2 2.2 3.3 5.6 mV

VOUTMIN_0.1% 4.5 4.2 4.2 3.0 4.2 9.7 mV

VOUTMAX_0.1% 3.1 3.3 3.5 3.3 3.3 3.3 V

VOUTMAX_1% 3.1 3.2 3.4 3.3 3.2 3.2 V

Table 18: IVR – Worst Case

Measure Process Supply Temperature Worst Case Result Unit

VOUTMIN_1% WO MAX min 2.1 mV

WZ min MAX 7.5 mV

VOUTMIN_0.1% WO MAX min 2.5 mV

WZ min MAX 17.2 mV

VOUTMAX_1% WO min MAX 3.1 V

WZ MAX min 3.5 V

VOUTMAX_0.1% WP min MAX 3.1 V

WS MAX min 3.4 V

Although this test bench didn’t take part in the AIDA-C workflow, its results not only fulfil the requirements

but also are in the same order of magnitude of the previously obtained. This proves the well operation

of the Class AB output stage.

50

4.1.7. Input voltage range

The different outputs voltages that result of the sweep of VIN are presented in the following figure:

Figure 45: Input Voltage Range – all corners

The input voltage ranges corresponding to variations of 1% and 0.1% are presented in the following

tables:

Table 19: IVR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

VINMIN_1% 0.695 0.703 0.710 0.775 0.703 0.695 V

VINMIN_0.1% 0.808 0.825 0.859 0.886 0.825 0.808 V

VINMAX_1% AVDD AVDD AVDD AVDD AVDD AVDD V

VINMAX_0.1% 2.877 3.009 3.143 3.242 3.009 2.877 V

Table 20: IVR - Worst Case

Measure Process Supply Temperature Worst Case Result Unit

VINMIN_1% WO min MAX 0.506 V

WZ MAX min 0.828 V

VINMIN_0.1% WP MAX MAX 0.677 V

WZ MAX min 0.990 V

VINMAX_1% WP min MAX 2.931 V

WS min min 3.395 V

VINMAX_0.1% WP min MAX 2.563 V

WS min min 3.400 V

The results presented above lead to the same conclusions as the previous specification allowing to

argue that the non-fulfilment of the overdrive and Vds margins don’t compromise the performance of the

circuit at least on its input and output range.

4.1.8. Offset

The MC simulations histograms for the offset are presented in the following figure. For both simulations

(local and local+process) the results detailed in Table 44.

51

Figure 46: Monte-Carlo Results (Y Values in Volts)

Table 21: Offset – Monte-Carlo Results

Min Mean Max Std Dev Unit OFFSET (Local dispersion) 1.93344 1.93512 1.93685 560𝜇 𝑉 OFFSET (Local+process dispersion) 1.93298 1.93662 1.93662 530𝜇 𝑉

In both cases a uniform dispersion was considered, contrary to the normal dispersion considered

previously which were less demanding. Even though the results show a great performance that won’t

compromise the whole ADC chain operation.

4.1.9. Open loop Static gain

The open loop gain results for both clock states are presented below:

Table 22: GDC – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

GDC_1 111.7 111.9 112.1 111.8 111.9 111.1 𝑑𝐵

GDC_2 111.7 111.9 112.1 111.8 111.9 111.1 𝑑𝐵

Table 23: GDC – Worst case

Measure Process Supply Temperature Worst Case Result Unit

GDC_1 WP min MAX 108.2 𝑑𝐵

WS MAX min 113.3 𝑑𝐵

GDC_2 WP min MAX 108.2 𝑑𝐵

WS MAX min 113.3 𝑑𝐵

52

Besides the fulfilment of the specification, these results show a higher gain and a smaller variation of its

values within the series of the considered corners.

4.1.10. Gain Bandwidth product

The GBW results for both clock states are presented below:

Table 24: GBW – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

GBW_1 55.8 56.1 56.4 96.7 56.1 39.2 𝑀𝐻𝑧

GBW_2 53.6 54.3 54.7 90.9 54.3 38.2 𝑀𝐻𝑧

Table 25: GBW – Worst case

Measure Process Supply Temperature Worst Case Result Unit

GBW_1 WS min MAX 33.7 𝑀𝐻𝑧

WP MAX min 111.7 𝑀𝐻𝑧

GBW_2 WS min MAX 32.5 𝑀𝐻𝑧

WP MAX min 106.2 𝑀𝐻𝑧

The obtained results in this case show a greater variation of values within the corners. Furthermore, the

analysis of the results allow the conclusion that in the second situation of clock states combinations the

GBW reaches lower values. This leads to the non-fulfilment of the GBW_2 on its worst case.

Results like this one prove that the consideration of both clock states must be taken into account in order

to consider the very worst case, so the ADC performance won’t be compromised.

4.1.11. Phase Margin

The phase margin results for both clock states are presented below:

Table 26: PM – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

MPHASE_1 74.5 75.0 75.5 77.0 75.0 72.6 °

MPHASE_2 70.3 70.4 70.8 72.0 70.4 68.4 °

53

Table 27: PM – Worst case

Measure Process Supply Temperature Worst Case Result Unit

MPHASE_1 WP MAX min 69.5 °

WZ MAX min 79.4 °

MPHASE_2 WP MAX min 65.5 °

WZ min min 76.8 °

The PM_1 assumes the same values as the previous sizing. However, the second combination of clock

states leads to a lower value, as happened in the GBW. Even so, the stability of the circuit is assured

as its speed that is shown in the next sub-section.

4.1.12. Settling Time

The settling time results are presented below:

Table 28: ST – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

SETTLING_0P5LSB14 23.7 18.1 17.7 16.8 18.1 20.2 𝑛𝑠

Table 29: ST – Worst case

Measure Process Supply Temperature Worst Case Result Unit

SETTLING_0P5LSB14 WP MAX min 14.4 𝑛𝑠

WO min MAX 24.7 𝑛𝑠

Although the ADC has a precision of 12 bits, the fulfilment of this specification considering a precision

of 14 assures its robustness face to the undesired parasitic pos-layout effects. From the previous sizing

to the one here presented is possible to see a reduction higher than 40% in the worst case, satisfying

now the requirement.

4.1.13. Noise

The noise results for both clock states are presented below:

Table 30: Noise – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

NRMS_1 37.8 37.9 37.9 35.9 37.9 42.1 𝜇𝑉𝑟𝑚𝑠

NRMS_2 35.3 35.3 35.3 33.2 35.3 39.3 𝜇𝑉𝑟𝑚𝑠

54

Table 31: Noise – Worst case

Measure Process Supply Temperature Worst Case Result Unit

NRMS_1 WO min min 35.3 𝜇𝑉𝑟𝑚𝑠

WZ MAX MAX 42.7 𝜇𝑉𝑟𝑚𝑠

NRMS_2 WO min min 32.7 𝜇𝑉𝑟𝑚𝑠

WP MAX MAX 40.1 𝜇𝑉𝑟𝑚𝑠

The new sizing solution does not present a major improvement in this spec. This can be explained by

the choice of the solution with lower power consumption from the POF which corresponds also to the

worst case of the noise spec.

Contrary to the PM and the GBW results, here the second combination of clock states presents best

results than the first. This means that both of them show worst cases in different measures, thus in both

of them an AC analysis must be performed.

4.1.14. PSRR

The PSRR results for both clock states and for 1𝑀𝐻𝑧 and 12𝑀𝐻𝑧 are presented below:

Table 32: PSRR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

PSRR1_1 40.6 40.6 40.6 43.7 40.6 38.1 𝑑𝐵

PSRR1_2 40.6 40.6 40.6 43.7 40.6 38.1 𝑑𝐵

PSRR12_1 19.0 19.1 19.1 22.3 19.1 16.3 𝑑𝐵

PSRR12_2 19.0 19.0 19.0 22.3 19.0 16.2 𝑑𝐵

Table 33: PSRR – Worst case

Measure Process Supply Temperature Worst Case Result Unit

PSRR1_1 WS Min MAX 36.6 𝑑𝐵

WP MAX min 45.3 𝑑𝐵

PSRR12_1 WS Min MAX 15.0 𝑑𝐵

WP MAX min 23.7 𝑑𝐵

PSRR1_2 WS Min MAX 36.6 𝑑𝐵

WP MAX min 45.3 𝑑𝐵

PSRR12_2 WS Min MAX 14.9 𝑑𝐵

WP MAX min 23.7 𝑑𝐵

Although this specification has not the desired value (above 20 dB at 12MHz), its non-fulfilment won’t

compromise the ADC operation. In fact, the extraction of this measures was not considered in the

optimization process.

55

4.2. VREFN Buffer

The circuit was optimized with AIDA-C considering only the test bench presented in OP, AC and

Transient Analysis. This optimization was performed during 3 weeks (approximately) while the following

test benches were added to this process.

Table 34: Considered corners in the VREFP Buffer opti9mization

Corner Input Voltage

wp_avdd_max_dvdd_max_temp_min_1 1.365

wp_avdd_max_dvdd_max_temp_max_2 1.15

ws_avdd_max_dvdd_max_temp_max_6 1.15

ws_avdd_min_dvdd_min_temp_max_8 0.935

wz_avdd_max_dvdd_max_temp_max_14 1.15

wz_avdd_min_dvdd_min_temp_min_15 1.15

Every time a few new solutions were got, these solutions were tested in all the corners. While it didn’t

fulfil all the corners and all the extremes of the voltage range, the worst corner was added, or the input

voltage was changed.

Table 34 presents all the considered corners at the end of this process. The obtained Pareto’s curve is

shown below. The considered solution is the one presented at the middle since it was the least

consuming in typical.

Figure 47: Pareto curve of the negative voltage buffer

The obtained results addressing the negative voltage reference buffer are presented below for each

measures that characterize it.

For each measure, the range extremes of its values is presented, indicating also the conditions where

they occur. Moreover the sensibility of each measure addressing the temperature and VDD range

variations is also presented.

56

The circuit’s devices dimensions are presented in Appendix F.

Table 35: VREFN performance synthesis

Parameters Unit Spec Min. Typ. Max.

Functional verification

SET OK

MOS operatring point OK

Peak current 𝑚𝐴 5.2 6.5 8.4

Unique DC operating point OK

Static performances

Supply current 𝑚𝐴 3.2 4.0 4.8

Input voltage range 𝑉 <0.935 >1.365

0.722 - avdd

Output voltage range 𝑉 <0.935 >1.365

0.008 - 3.193

PSRR (1Hz) 𝑑𝐵 37.2 41.1 45.8

Dynamic performances

Static gain 𝑑𝐵 >70 104.2 107.2 109.0

Gain Bandwdth product 𝑀𝐻𝑧 >33 35.1 57.1 114.2

Phase margin ° >65 65.2 70.1 82.3

Settling time 𝑛𝑠 <30 13.8 19.3 24.8

NRMS 𝜇𝑉𝑚𝑟𝑠 <46 33.7 39.0 41.4

PSRR (12MHz) 𝑑𝐵 16.0 19.7 24.4

4.2.1. MOS operating point

The operation point of the amplifiers are guaranteed within typical conditions. Even though the circuit’s

operation isn’t affected in all corners solutions, in some of them the margin voltages aren’t completely

fulfilled. This situation is presented in the following figures, where the voltage margins of each device

are presented in all corners:

Figure 48: Overdrive Voltage Margins (Y Values in Volts)

The Vds voltage margin isn’t completely fulfilled in the 5th, 7th, 13th and 15th corners.

57

Figure 49: Vds Voltage Margins (Y Values in Volts)

4.2.2. Power on

During the 50𝑚𝑠 that the power supply takes to set up and to set down the circuit was tested. The

graphic results of the supplied current are presented below :

Figure 50: Supply current - Set up and set down (Y Values in Amperes)

4.2.3. Unique DC operating point

The circuit’s operations is verified for all the corners and input voltages. The result of the DC sweep of

the VINP voltage is presented below. This assures that the operation of the OpAmp has an unique DC

operating point for each of the input voltages within the acceptable range.

58

Figure 51: Unique DC operating point

4.2.4. Supply current

The obtained results for the DC supplied current with typical input voltage is presented below:

Table 36: IDD – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

CONSO_1 4.0 4.0 4.0 4.3 4.0 3.8 𝑚𝐴

Table 37: IDD – Worst case

Measure Process Supply Temperature Worst Case Result Unit

CONSO_1 WO min MAX 3.2 𝑚𝐴

WP MAX min 4.8 𝑚𝐴

In this buffer happens exactly the same as in the VREFP, that is the atypical variation with the

temperature and the shrinkage of its variation with the different corners.

4.2.5. Power Shut Down Supplied Current and Current Peaks

The transient response of the circuit when it is turned off and on is presented in Figure 52. The clocks

and ON signals are also presented allowing to justify the current and output voltage responses:

59

Figure 52: Transients response with power-off and power-on (W(I_ALIM) in Amperes and others in Volts)

Table 38: PSD – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

Peak Current ON 4.2 4.2 4.2 5.0 4.2 3.9 𝑚𝐴

Peak Current Power-Off 6.4 6.5 6.7 7.4 6.5 6.0 𝑚𝐴

AVDD Current OFF 730.8 705.1 676.8 780.0 705.1 568.6 𝑛𝐴

Peak Current Power-On 5.2 5.4 5.6 5.8 5.4 5.6 𝑚𝐴

Table 39: IDD – Worst case

Measure Process Supply Temperature Worst Case Result Unit

Peak Current ON WS min MAX 3.5 𝑚𝐴

WP MAX min 5.5 𝑚𝐴

Peak Current Power-Off WS min MAX 5.2 𝑚𝐴

WP MAX min 8.4 𝑚𝐴

AVDD Current OFF WP MAX min 165.4 𝑛𝐴

WS min MAX 1042.9 𝑛𝐴

Peak Current Power-On WS min MAX 4.5 𝑚𝐴

WP MAX MAX 6.9 𝑚𝐴

The conclusions taken regarding this test bench in the previous circuit apply here as well. However, i9n

this case the output voltage presented in Figure 52 stabilizes quite faster than in the previous case.

60

4.2.6. Output voltage range

The “ERROR voltage” signal obtained in this test bench is presented in Figure 53, where the null X value

correspond to input voltage. The output voltage range is tested not only for the typical input voltages but

also considering the extremes of the specified voltage range. In all the analysed cases, this

specifications is fulfilled.

Figure 53: Output error voltage

The output voltage ranges corresponding to variations of 1% and 0.1% are presented in the following

tables considering only the typical input voltages:

Table 40: IVR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

VOUTMIN_1% 4.3 4.1 3.8 2.5 4.1 2.5 mV

VOUTMIN_0.1% 7.8 7.8 8.1 8.2 7.8 12.7 mV

VOUTMAX_0.1% 3.1 3.3 3.5 3.3 3.3 3.3 V

VOUTMAX_1% 3.0 3.2 3.4 3.2 3.2 3.2 V

Table 41: IVR – Worst Case

Measure Process Supply Temperature Worst Case Result Unit

VOUTMIN_1% WO MAX min 2.3 mV

WZ min MAX 9.0 mV

VOUTMIN_0.1% WS min min 5.2 mV

WZ MAX MAX 73.8 mV

VOUTMAX_1% WP min MAX 3.1 V

WP min MAX VDD V

VOUTMAX_0.1% WP min MAX 3.0 V

WP min MAX 3.4 V

These results lead to the same conclusions of the previous buffer.

61

4.2.7. Input voltage range

The different outputs voltages that result of the sweep of VIN are presented in the following figure:

Figure 54: Input Voltage Range – all corners

The input voltage ranges corresponding to variations of 1% and 0.1% are presented in the following

tables:

Table 42: IVR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

VINMIN_1% 0.838 0.862 0.923 0.931 0.862 0.786 V

VINMIN_0.1% 0.713 0.722 0.731 0.797 0.722 0.637 V

VINMAX_1% 2.905 3.038 3.176 3.286 3.038 2.794 V

VINMAX_0.1% 3.300 3.300 3.300 3.300 3.300 3.212 V

Table 43: IVR – Worst Case

Measure Process Supply Temperature Worst Case Result Unit

VINMIN_1% WO min MAX 0.561 V

WZ MAX min 0.856 V

VINMIN_0.1% WO min MAX 0.703 V

WZ MAX min 1.095 V

VINMAX_1% WP min MAX 2.584 V

WO MAX min 3.450 V

VINMAX_0.1% WP min MAX 2.976 V

WS MAX MAX 3.448 V

This specification is also fulfilled even though the OP margins aren’t completely fulfilled and the test

bench is not included in AIDA optimization process.

62

4.2.8. Offset

The MC simulations result histogram for the offset are presented in the following figure. For both

simulations (local and local+process) the results detailed in Table 44.

Figure 55: Monte-Carlo Results (Y Values in Volts)

Table 44: Offset – Monte-Carlo Results

Min Mean Max Std Dev Unit

OFFSET (Local dispersion) 1.36322 1.36518 1.36744 680𝜇 V

OFFSET (Local+process dispersion) 1.36283 1.36518 1.36703 680𝜇 V

Once again, even considering a worst case uniform dispersion, the MC results are within the same

magnitude of the presented in the previous sizing.

4.2.9. Open loop Static gain

The open loop gain results for both clock states are presented below:

Table 45: GDC – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

GDC_1 107.0 107.1 107.2 108.2 107.1 90.0 𝑑𝐵

GDC_2 106.9 107.1 107.1 108.2 107.1 90.0 𝑑𝐵

63

Table 46: GDC – Worst case

Measure Process Supply Temperature Worst Case Result Unit

GDC_1 WZ MAX MAX 104.2 𝑑𝐵

WS min MAX 109.0 𝑑𝐵

GDC_2 WZ MAX MAX 104.2 𝑑𝐵

WS min MAX 109.0 𝑑𝐵

As in the previous buffer, this spec is way above the required. Comparing with the previous sizing, it

shows also a shrinkage of its worst cases variation.

4.2.10. Gain Bandwidth product

The gain bandwidth results for both clock states are presented below:

Table 47: GBW – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

GBW_1 61.3 61.5 61.8 101.4 61.5 44.9 𝑀𝐻𝑧

GBW_2 57.8 58.6 59.1 92.1 58.6 43.2 𝑀𝐻𝑧

Table 48: GBW – Worst case

Measure Process Supply Temperature Worst Case Result Unit

GBW_1 WO min MAX 36.1 𝑀𝐻𝑧

WP MAX min 114.2 𝑀𝐻𝑧

GBW_2 WS min MAX 35.1 𝑀𝐻𝑧

WP MAX min 108.8 𝑀𝐻𝑧

In this buffer, since the convergence of the optimization with AIDA was faster than the previous, all the

specs were fulfilled including this one in all the corners as presented above.

The same conclusions regarding the different clock states apply to this buffer as well.

4.2.11. Phase Margin

The phase margin results for both clock states are presented below:

Table 49: PM – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

MPHASE_1 77.3 77.8 78.2 80.9 77.8 74.6 °

MPHASE_2 71.8 71.5 71.7 74.9 71.5 68.9 °

64

Table 50: PM – Worst case

Measure Process Supply Temperature Worst Case Result Unit

MPHASE_1 WO min MAX 69.8 °

WZ MAX min 82.3 °

MPHASE_2 WO min MAX 65.2 °

WZ MAX min 76.2 °

The PM spec is also fulfilled in this buffer, presenting also the same variation with the clock states as

the previous one.

4.2.12. Settling Time

The settling time results are presented below:

Table 51: ST – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

SETTLING_0P5LSB14 19.082 19.81 19.84 24.33 19.81 26.68 𝑛𝑠

Table 52: ST – Worst case

Measure Process Supply Temperature Worst Case Result Unit

SETTLING_0P5LSB14 WP min min 13.8 𝑛𝑠

WS MAX MAX 24.8 𝑛𝑠

In this case the reduction of the settling time face to the worst case of the previous sizing is not so

accentuated, even so a reduction of 9.2ns is obtained in the same corner.

4.2.13. Noise

The noise results for both clock states are presented below:

Table 53: Noise – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

NRMS_1 39.6 39.7 39.8 37.3 39.7 44.2 𝜇𝑉𝑟𝑚𝑠

NRMS_2 36.5 36.5 36.6 33.7 36.5 41.0 𝜇𝑉𝑟𝑚𝑠

65

Table 54: Noise – Worst case

Measure Process Supply Temperature Worst Case Result Unit

NRMS_1 WP min min 35.9 𝜇𝑉𝑟𝑚𝑠

WP MAX MAX 43.7 𝜇𝑉𝑟𝑚𝑠

NRMS_2 WZ min min 33.7 𝜇𝑉𝑟𝑚𝑠

WP MAX MAX 41.4 𝜇𝑉𝑟𝑚𝑠

The same conclusion discussed in the previous buffers applies to this case as well.

4.2.14. PSRR

The PSRR results for both clock states are presented below:

Table 55: PSRR – Supply Voltage and Temperature sensitivity

Temperature: 25◦C Supply Voltage: 3.3V

Unit Supply Voltage Sensitivity (𝑉) Temperatue Sensitivity (°𝐶)

3.135 3.3 3.465 -55 25 125

PSRR1_1 41.1 41.1 41.1 43.9 41.1 38.9 𝑑𝐵

PSRR1_2 41.1 41.2 41.2 43.9 41.2 38.9 𝑑𝐵

PSRR12_1 19.6 19.6 19.6 22.4 19.6 17.3 𝑑𝐵

PSRR12_2 19.6 19.6 19.6 22.4 19.6 17.3 𝑑𝐵

Table 56: PSRR – Worst case

Measure Process Supply Temperature Worst Case Result Unit

PSRR1_1 WS MAX MAX 37.2 𝑑𝐵

WP min min 45.8 𝑑𝐵

PSRR12_1 WS min MAX 16.0 𝑑𝐵

WP min min 24.4 𝑑𝐵

PSRR1_2 WS MAX MAX 37.2 𝑑𝐵

WP min min 45.8 𝑑𝐵

PSRR12_2 WS MAX MAX 15.9 𝑑𝐵

WP min min 24.3 𝑑𝐵

Similarly to the previous buffer, this spec is not ideally accomplished, even so it is not critical and does

not compromise the circuits operation.

4.3. Other Results

The VREFP circuit was set up to run on AIDA in other facilities, which allowed a comparison between

the different set of results given the corners with which AIDA was sat up.

In this case, the circuit was set to run in the corners presented in Table 57. The results considering the

simulation in all the corners are available in Appendix I and Appendix J.

66

Table 57: Considered corners in the VREFP Buffer opti9mization

Corner Input Voltage

wp_avdd_max_dvdd_max_temp_min_1 Typical

wp_avdd_max_dvdd_max_temp_min_1 Dvin_max3

ws_avdd_min_dvdd_min_temp_max_8 Typical

ws_avdd_min_dvdd_min_temp_max_8 Dvin_max3

Although the test benches considered were worst cases for some of the specifications, these weren´t

enough to address all the worst cases. Therefore, AIDA tended to an optimal solution that fitted the best

the three situations. However when the circuit was simulated in all corners considering also the voltage

range, it is understandable that it didn’t meet some of the specs.

4.4. Conclusions

The results achieved with the FC topology were presented in 4.1 and 4.2. The circuits that resulted with

the new dimensioning were characterized with the test benches introduced in the 3rd Chapter.

In both cases the reduction of the power consumption was possible. However only in the positive buffer

this reduction was noticeable: 11.1%.

The achieved reduction comes with the drawback of the non-fulfilment of GBW specifications in the 8th

corner. This represents a fail of 1.5% in this specification, which only happens with one of the clock

signals combinations.

During the circuits characterization some of the extracted measures were performed twice, in both clock

states, evidencing their dependence with the clock and the need to consider both of extracted measures

in the optimization process. Even though the previous results regarding the first dimensioning performed

before doesn’t take this in consideration, their results are not completely compromised. However, this

approach is recommended

Another failure in the specifications is presented in the Gain Margin of the VREFN buffer. However, in

this case, the non-fulfilment of this specification won’t certainly compromise the circuits operation, which

also justifies why it isn’t introduced in the previous sub-chapters.

At last, the other results obtained for the VREFP buffer allow also a comparison between the different

optimization procedures:

- In both cases, the need to use more than one corner was concluded. In addition, the use of

application of the extreme input voltage was also necessary.

- The dimensioning results presented in 4.3 allow to conclude that the settling time specification

is the one that enhances the need of a high current. The non-fulfilment, or the attenuation of

3 Although these inputs are simulated, they weren’t included in the optimization process.

67

this requirement in all the corners would mean a much lower current consumption. However,

this means the disoperation of the Pipeline ADC.

- The changes performed in order to speed up the circuits optimization – decrease of the clocks

period and decrease of the precision – showed a great advantage since each population was

generated a lot faster here in the IT than in the other facilities, without compromise the obtained

results. After this, the results were obviously tested with a full precision in order to acquire its

reliability..

68

69

5 CONCLUSIONS AND FUTURE WORK

In this thesis, the re-designed buffers were presented, including some comparisons between alternative

sizing solutions. This chapter presents the closing remarks, and the future directions for continuing the

development of the circuits.

5.1. Conclusions

In both cases, the dimensioned buffers meet almost all the settled specifications in all the corners,

considering also the whole input range. Although the specifications could be completely fulfilled in all

the corners, it would mean an incensement of power consumption which is the contrary of the settled

goals in this project. Furthermore, the non-fulfilment of those specifications does not compromise the

correct operation of the ADC chain.

Besides the re-dimensioning of the circuits, another topology was suggested – DRFC. Although the

study of this topology wasn’t finished due to a misunderstanding about the load operation, based on the

primary results obtained before, it is reasonable to argue that this topology could be implemented.

The use of AIDA-C was justified by the achieved results, the number of different solutions allowing to

choose the one that fits best the needs facing the trade-offs between them, the effectiveness and speed

in the convergence toward the desired results.

Without replacing the designer role in the development of an IC, AIDA has been proving that has a great

potential to be widely used in many different IC application. However, its integration in the workflow will

depend strongly on the circuits operation and its testing. In this project, for instance, the use of two

different test benches took longer than the crossing of both, furthermore, after analyzing the OpAmp

behavior, the clock period was shrunken from 1µs to 300ns in order to speed up the optimization while

keeping the feebleness of the results.

5.2. Future Work

Besides the ADC reference buffers where this thesis focused, there are some other components within

the ADC that are also consuming a lot of power and have a great potential to be optimized.

- MD0 operation amplifier corresponding to the 1st stage of the ADC;

- CDS stage operation amplifier.

The study with DRFC topology was not concluded. Considering some new releases that have been

made with some variants of the RFC topology being used in Pipelined ADC [30-32], a further study in

70

these circuits is suggested, to explore the maximum potential of this recent topologies. This development

could not only be applied in the reference buffers but also in the restart components of the ADC that

continue to consume more than what is desirable.

In this project the optimization was settled disregarding the elements that shut down of the circuit

shorting the nodes where the quiescent current flows. Thus in some of the tested corners, the supplied

current when the circuit is turned off is too high. Therefore, a faster and last optimization regarding only

these elements and its operation is recommended in order to avoid such high currents when the circuit

is off.

Moreover, in this work, only AIDA-C tool was used as optimization tool. The use of AIDA-L us

recommended in order to not only get more robust results, but also to have a comparison between the

results provided by these tools.

71

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[30] R. Martins, N. Lourenço, A. Canelas, and N. Horta, “Electromigration-aware analog Router with

multilayer multiport terminal structures,” Integration, the VLSI Journal, vol. 47, no. 4, pp. 532–

547, Sep. 2014.

[31] N. C. C. Lourenço, “Automatic Analog IC Sizing and Optimization Constrained with PVT Corners

and Layout Effects”, Ph.D. dissertation, DEEC, IST, 2014.

[32] M. Ahmed, F. Tang, and A. Bermak, “A 14-bit 70MS / s pipeline ADC with power-efficient back-

end stages,” in 2015 IEEE International Conference on Electron Devices and Solid-State Circuits

(EDSSC), 2015, pp. 154–157.

[33] D. R. da Silva and N. Oki, “An amplifier and capacitor sharing technique using recycling folded

cascode operational amplifier with applications in MDAC of CMOS pipelined ADC,” in 2015

Conference on Design of Circuits and Integrated Systems (DCIS), 2015, pp. 1–4.

74

75

APPENDIXES

APPENDIX A: DRFC OPAMP SCHEMATIC ................................................................................................. 77

APPENDIX B: SOLUTIONS OBTAINED WITH AIDA IN TYPICAL CONDITIONS FOR VREFP ............................... 79

APPENDIX C: VREFP DIMENSIONING ....................................................................................................... 81

APPENDIX D: VREFP BUFFER RESULTS (PART 1) .................................................................................... 82

APPENDIX E: VREFP BUFFER RESULTS (PART 2) .................................................................................... 83

APPENDIX F: VREFN DIMENSIONING ...................................................................................................... 85

APPENDIX G: VREFN BUFFER RESULTS (PART 1) ................................................................................... 86

APPENDIX H: VREFN BUFFER RESULTS (PART 2) ................................................................................... 87

APPENDIX I: VREFP OTHER FACILITY RESULTS (PART 1)......................................................................... 89

APPENDIX J: VREFP OTHER FACILITY RESULTS (PART 2) ....................................................................... 90

76

77

Appendix A: DRFC OpAmp Schematic

The schematic of the DRFC OpAmp is presented below with a class AB output stage adapted from the previous amplifier:

M13 M23

M10

avdd

M9

avdd

avdd

M8

avdd

M7

avdd

M5

agnd

M6

agnd

vb3

vb1

M1c M2c

vinp vinn

M1b

avddvinp

M1a

avddvinp

M2a

avddvinn

M2b

avddvinn

M12

agnd

M11

agnd

M22

agnd

M21

agndvb1

avdd

agnd

M3d M4dM3cM3a

agnd

M4c M4a

agnd

M4b

agnd

M3b

M0

vb0

avdd

agnd agnd

avdd

pfold nfold

nfoldpfold

K : 1 M : N 1 : KN : M

agnd

M21

M20

avdd

M57

M56

vout2 avdd

agnd

R2

C7

R1

C8

vout

bcp2

C1

Figure 56: DRFC with Class-AB Output Stage

78

79

Appendix B: Solutions obtained with AIDA in typical conditions for VREFP

Specs #1 #2 #3 #4 #5 #6

conso < 4.5 mA 3.881 4.086 4.291 4.343 4.343 4.35

gbw_1 > 33 MHz 39.74 36.46 35.49 40.48 37.46 35.76

gbw_2 > 33 MHz 38.93 35.82 35.21 39.76 36.87 35.23

gdc_1 > 70 dB 113.2 111.4 115.3 103.6 116.4 116.1

gdc_2 > 70 dB 113.8 111.4 115.3 103.6 116.4 116.1

mgain_1 > 15 dB 20.87 22.98 25.99 24.56 23.76 24.25

mgain_2 > 15 dB 23.72 24.72 27.78 26.66 25.93 26.54

mp_1 > 70 deg 74.9 77.13 77.42 79.6 76.49 76.44

mp_2 > 70 deg 70.17 73.24 74.6 75.67 73.48 73.52

nrms_1 < 41 μV 37.58 36.57 35.17 24.78 32.26 32.23

nrms_2 < 41 μV 34.67 33.97 32.77 32.61 30.76 30.76

settling_0p5lsb14 < 22 ns 19.41 19.57 18.41 21.66 20.34 20.17

After AIDA-C was set to run with OP, AC and Transient Analysis test bench, 6 different solutions were found. Even though they wouldn’t fulfil the corners

specifications, they achieved the desired ones in typical which are presented in the table above.

80

81

Appendix C: VREFP Dimensioning

Y Diameter [µm] Lenght [µm] Multiplicity

MALL_DY 9.0 MALL_L 3.8

M0_DY 6.0 M0_L 1.1

M12_DY 3.0 M12_L 0.4

MA_DY 9.0 MA_L 1.4 M37M38_M 31

MC_DY 10.8 MC_L 3.4 M53M54_M 45

MD_DY 5.2 MD_L 0.5

ME_DY 6.0 ME_L 1.3 M62M63_M 12

MF_DY 6.9 MF_L 1.8

MG_DY 9.5 MG_L 1.1 M21_M 5

MH_DY 5.9 MH_L 0.8 M20_M 5

MI_DY 14.2 MI_L 1.2 M56_M 20

MJ_DY 14.5 MJ_L 0.6 M57_M 18

M8_M 9.0

MK_DY 2.5 MK_L 0.7 M1000M2000_M 60

C0_M 2.0

C7C8_M 16.0

RP1_L 14.0

The dimensioning obtained with AIDA-C for the VREFP buffer is presented in the previous table. The achieved results for all the corners are presented in the

following two tables. The higher and lower extremes are highlighted with brighter and darker gray. The values that don’t fulfil the specs are highlighted with red.

82

Appendix D: VREFP Buffer Results (Part 1)

CONSO_1 GBW_1 GBW_2 GDC_1 GDC_2 MGAIN_1 MGAIN_2 MPHASE_1 MPHASE_2 NRMS_1 NRMS_2 SETTLING _0P5LSB14

mA MHz MHz dB dB dB dB deg deg μV μV ns

Typical 4.0 56.1 54.3 111.9 111.9 19.0 19.2 75.0 70.4 37.9 35.3 18.1

wp_avdd_max_dvdd_max_temp_min_1 4.8 111.7 106.2 110.3 110.2 13.6 13.4 75.6 70.2 35.8 33.5 14.4

wp_avdd_max_dvdd_max_temp_max_2 4.1 45.7 44.7 108.7 108.7 23.7 24.8 71.6 67.5 42.7 40.1 19.1

wp_avdd_min_dvdd_min_temp_min_3 4.8 109.5 103.3 110.0 109.9 13.9 14.4 74.4 69.6 35.6 33.2 14.8

wp_avdd_min_dvdd_min_temp_max_4 4.1 45.3 44.2 108.2 108.2 23.9 25.6 70.8 66.7 42.6 40.0 19.1

ws_avdd_max_dvdd_max_temp_min_5 4.0 86.0 80.2 113.3 113.3 12.3 12.9 79.1 74.0 36.6 33.5 20.7

ws_avdd_max_dvdd_max_temp_max_6 3.5 33.9 33.1 113.1 113.1 22.7 23.5 74.7 70.4 42.0 39.0 23.6

ws_avdd_min_dvdd_min_temp_min_7 4.0 84.3 79.2 113.1 113.0 12.5 13.5 78.1 76.7 36.3 34.2 24.5

ws_avdd_min_dvdd_min_temp_max_8 3.5 33.7 32.5 112.7 112.7 22.9 24.7 73.9 70.4 41.9 39.3 24.1

wo_avdd_max_dvdd_max_temp_min_9 4.2 91.0 86.3 112.9 112.8 12.8 12.7 75.6 70.0 35.5 33.0 17.4

wo_avdd_max_dvdd_max_temp_max_10 3.5 37.1 36.3 112.2 112.2 23.3 21.6 70.4 66.1 41.5 38.9 24.1

wo_avdd_min_dvdd_min_temp_min_11 4.1 89.4 84.1 112.6 112.6 13.1 13.6 74.5 69.6 35.3 32.7 18.1

wo_avdd_min_dvdd_min_temp_max_12 3.5 36.8 36.1 111.9 111.8 23.5 23.1 69.5 65.5 41.4 38.9 24.7

wz_avdd_max_dvdd_max_temp_min_13 4.6 103.8 97.2 110.7 110.7 13.3 13.9 79.4 74.3 36.4 33.6 16.1

wz_avdd_max_dvdd_max_temp_max_14 4.1 41.3 40.2 108.9 108.8 22.8 24.9 75.6 71.4 42.7 39.8 18.4

wz_avdd_min_dvdd_min_temp_min_15 4.6 101.5 95.7 110.4 110.3 13.6 14.6 78.4 76.8 36.2 34.2 18.5

wz_avdd_min_dvdd_min_temp_max_16 4.0 40.9 39.7 108.5 108.4 23.0 25.0 74.8 71.2 42.5 40.0 19.3

tm_avdd_min_dvdd_min_temp_typ_17 4.0 55.8 53.6 111.7 111.7 19.2 20.2 74.5 70.3 37.8 35.3 23.7

tm_avdd_max_dvdd_max_temp_typ_18 4.0 56.4 54.7 112.1 112.1 18.9 18.5 75.5 70.8 37.9 35.3 17.7

tm_avdd_typ_dvdd_typ_temp_min_19 4.4 96.7 90.9 111.8 111.8 13.1 13.6 77.0 72.0 35.9 33.2 16.8

tm_avdd_typ_dvdd_typ_temp_max_20 3.8 39.2 38.2 111.1 111.1 23.4 24.7 72.6 68.4 42.1 39.3 20.2

83

Appendix E: VREFP Buffer Results (Part 2)

VINMIN _0.1%

VINMAX _0.1%

VOUTMIN _0.1%

VOUTMAX _1%

PSRR 1_1

PSRR 1_2

PSRR 12_1

PSRR 12_2

Peak Current

ON

Peak Current

Power-off

AVDD Current

OFF

Peak Current

Power-on

V V mV V dB dB dB dB mA mA µA mA

Typical 0.825 3.009 4.2 3.248 40.6 40.6 19.1 19.0 7.090 6.759 1.402 5.967

wp_avdd_max_dvdd_max_temp_min_1 0.919 3.286 3.1 3.416 45.3 45.3 23.7 23.7 9.050 8.492 0.651 7.896

wp_avdd_max_dvdd_max_temp_max_2 0.752 2.790 13.7 3.385 39.5 39.5 17.7 17.6 7.726 6.862 1.300 5.904

wp_avdd_min_dvdd_min_temp_min_3 0.832 3.003 3.2 3.090 45.2 45.2 23.7 23.7 8.527 7.982 0.771 7.738

wp_avdd_min_dvdd_min_temp_max_4 0.691 2.563 14.7 3.063 39.5 39.5 17.6 17.6 7.438 6.375 1.300 5.925

ws_avdd_max_dvdd_max_temp_min_5 0.944 AVDD 2.7 3.425 42.3 42.3 20.9 20.9 6.810 7.199 1.513 6.697

ws_avdd_max_dvdd_max_temp_max_6 0.816 2.989 7.1 3.403 36.7 36.7 15.0 15.0 5.988 5.903 1.964 5.007

ws_avdd_min_dvdd_min_temp_min_7 0.905 AVDD 3.0 3.099 42.3 42.3 20.9 20.9 6.443 6.806 1.556 6.268

ws_avdd_min_dvdd_min_temp_max_8 0.779 2.743 7.8 3.078 36.6 36.6 15.0 14.9 5.795 5.455 2.045 4.934

wo_avdd_max_dvdd_max_temp_min_9 0.861 3.400 2.5 3.423 43.6 43.6 22.1 22.1 7.053 7.533 1.261 6.966

wo_avdd_max_dvdd_max_temp_max_10 0.718 2.933 6.8 3.398 37.7 37.7 16.0 16.0 6.240 6.318 1.470 5.100

wo_avdd_min_dvdd_min_temp_min_11 0.816 3.109 2.9 3.096 43.6 43.6 22.1 22.1 6.654 7.063 1.258 6.789

wo_avdd_min_dvdd_min_temp_max_12 0.677 2.683 7.3 3.074 37.7 37.7 16.0 15.9 5.972 5.863 1.697 5.092

wz_avdd_max_dvdd_max_temp_min_13 0.990 3.361 3.1 3.419 43.9 43.9 22.4 22.4 8.998 7.937 1.592 7.612

wz_avdd_max_dvdd_max_temp_max_14 0.848 2.833 15.9 3.390 38.3 38.3 16.6 16.5 7.383 6.685 1.431 5.833

wz_avdd_min_dvdd_min_temp_min_15 0.920 3.080 3.2 3.093 43.9 43.9 22.4 22.4 8.185 7.446 1.503 7.206

wz_avdd_min_dvdd_min_temp_max_16 0.796 2.610 17.2 3.066 38.3 38.3 16.5 16.5 7.121 6.324 1.601 5.748

tm_avdd_min_dvdd_min_temp_typ_17 0.808 2.877 4.5 3.086 40.6 40.6 19.0 19.0 6.937 6.656 1.438 5.871

tm_avdd_max_dvdd_max_temp_typ_18 0.859 3.143 4.2 3.411 40.6 40.6 19.1 19.0 7.252 6.870 1.372 6.042

tm_avdd_typ_dvdd_typ_temp_min_19 0.886 3.242 3.0 3.258 43.7 43.7 22.3 22.3 7.559 7.504 1.338 7.196

tm_avdd_typ_dvdd_typ_temp_max_20 0.754 2.768 9.7 3.234 38.1 38.1 16.3 16.2 7.051 6.322 1.530 5.463

84

85

Appendix F: VREFN Dimensioning

Y Diameter [µm] Lenght [µm] Multiplicity

MALL_DY 9.0 MALL_L 2.2

M0_DY 9.0 M0_L 1.6

M12_DY 2.0 M12_L 0.9

MA_DY 8.8 MA_L 1.6 M37M38_M 33

MC_DY 9.1 MC_L 1.4 M53M54_M 46

MD_DY 2.9 MD_L 0.9

ME_DY 6.8 ME_L 1.2 M62M63_M 15

MF_DY 2.1 MF_L 1.3

MG_DY 6.6 MG_L 2.4 M21_M 6

MH_DY 5.5 MH_L 0.6 M20_M 4

MI_DY 14.2 MI_L 1.8 M56_M 41

M9_M 3

MJ_DY 12.3 MJ_L 0.5 M57_M 21

MK_DY 3.5 MK_L 0.6 M1000M2000_M 40

C0_M 2.0

C7C8_M 14.0

RP1_L 12.0

The dimensioning obtained with AIDA-C for the VREFP buffer is presented in the previous table. The achieved results for all the corners are presented in the

following two tables. The higher and lower extremes are highlighted with brighter and darker gray. The values that don’t fulfil the specs are highlighted with red.

86

Appendix G: VREFN Buffer Results (Part 1)

CONSO_1 GBW_1 GBW_2 GDC_1 GDC_2 MGAIN_1 MGAIN_2 MPHASE_1 MPHASE_2 NRMS_1 NRMS_2 SETTLING _0P5LSB14

mA MHz MHz dB dB dB dB deg deg μV μV ns

Typical 3.8 58.8 57.1 107.2 107.2 15.0 15.0 75.3 70.1 39.0 36.6 19.3

wp_avdd_max_dvdd_max_temp_min_1 4.8 114.2 108.8 104.7 104.7 12.7 13.2 77.8 71.8 35.9 33.9 14.6

wp_avdd_max_dvdd_max_temp_max_2 3.9 49.2 48.0 104.6 104.6 18.0 16.8 72.3 67.8 43.7 41.4 17.8

wp_avdd_min_dvdd_min_temp_min_3 4.7 112.9 107.3 104.7 104.7 12.6 13.1 76.6 70.5 35.9 33.9 13.8

wp_avdd_min_dvdd_min_temp_max_4 3.9 49.0 47.8 104.7 104.7 17.5 16.5 71.4 66.9 43.7 41.4 17.7

ws_avdd_max_dvdd_max_temp_min_5 4.0 85.9 81.3 107.6 107.5 11.6 12.7 81.5 75.3 36.7 33.9 21.3

ws_avdd_max_dvdd_max_temp_max_6 3.3 36.2 35.3 109.0 108.9 16.5 16.3 74.6 69.9 43.2 40.4 24.8

ws_avdd_min_dvdd_min_temp_min_7 3.9 85.0 80.3 107.7 107.7 11.6 12.7 80.5 74.3 36.6 33.9 20.2

ws_avdd_min_dvdd_min_temp_max_8 3.2 36.1 35.1 109.0 109.0 16.3 16.1 73.8 69.2 43.2 40.4 23.3

wo_avdd_max_dvdd_max_temp_min_9 4.1 93.4 89.0 107.5 107.5 11.8 12.5 77.3 71.1 36.1 33.7 17.3

wo_avdd_max_dvdd_max_temp_max_10 3.3 40.0 39.1 108.6 108.6 15.7 15.4 70.6 66.0 43.1 40.7 23.0

wo_avdd_min_dvdd_min_temp_min_11 4.0 92.5 88.1 107.5 107.6 11.8 12.4 76.2 70.0 36.1 33.8 16.5

wo_avdd_min_dvdd_min_temp_max_12 3.2 39.9 38.9 108.7 108.7 15.6 15.2 69.8 65.2 43.1 40.7 24.0

wz_avdd_max_dvdd_max_temp_min_13 4.7 103.1 97.8 104.7 104.7 12.8 13.7 82.3 76.2 36.2 33.7 18.2

wz_avdd_max_dvdd_max_temp_max_14 3.9 43.9 42.8 104.2 104.2 20.1 18.2 75.9 71.4 43.4 40.8 24.6

wz_avdd_min_dvdd_min_temp_min_15 4.6 101.9 96.5 104.8 104.8 12.8 13.6 81.1 75.0 36.1 33.7 17.2

wz_avdd_min_dvdd_min_temp_max_16 3.9 43.7 42.6 104.4 104.4 19.4 17.9 75.1 70.5 43.3 40.8 21.8

tm_avdd_min_dvdd_min_temp_typ_17 3.8 58.7 56.8 107.2 107.2 14.9 15.0 74.7 69.5 39.0 36.6 23.3

tm_avdd_max_dvdd_max_temp_typ_18 3.9 59.0 57.2 107.1 107.1 15.1 15.1 75.7 70.6 39.0 36.6 17.8

tm_avdd_typ_dvdd_typ_temp_min_19 4.4 98.1 93.2 106.4 106.3 12.1 13.0 79.1 73.1 36.1 33.7 17.0

tm_avdd_typ_dvdd_typ_temp_max_20 3.6 42.0 41.0 107.3 107.3 16.8 16.3 72.8 68.2 43.2 40.7 18.7

87

Appendix H: VREFN Buffer Results (Part 2)

VINMIN _0.1%

VINMAX _0.1%

VOUTMIN _0.1%

VOUTMAX _0.1%

PSRR 1_1

PSRR 1_2

PSRR 12_1

PSRR 12_2

Peak

Current

ON

Peak

Current

Power-off

AVDD

Current

OFF

Peak

Current

Power-on

V V mV V dB dB dB dB mA mA mA mA

Typical 0.722 3.300 7.8 3.288 41.1 41.1 19.7 19.7 4.2 6.5 705.1 5.4

wp_avdd_max_dvdd_max_temp_min_1 0.765 3.300 18.0 3.449 45.8 45.8 24.3 24.3 5.5 8.4 165.4 6.8

wp_avdd_max_dvdd_max_temp_max_2 0.616 3.281 47.1 3.440 40.0 40.0 18.4 18.3 4.3 6.7 563.2 6.9

wp_avdd_min_dvdd_min_temp_min_3 0.748 3.300 16.8 3.126 45.8 45.8 24.4 24.3 5.4 7.8 246.1 6.3

wp_avdd_min_dvdd_min_temp_max_4 0.590 2.976 45.4 3.118 40.0 40.0 18.4 18.3 4.2 6.1 551.9 6.7

ws_avdd_max_dvdd_max_temp_min_5 0.846 3.300 5.8 3.456 42.9 42.9 21.6 21.6 4.5 7.1 769.3 4.9

ws_avdd_max_dvdd_max_temp_max_6 0.693 3.448 10.3 3.448 37.2 37.2 16.0 15.9 3.5 5.6 1000.4 4.6

ws_avdd_min_dvdd_min_temp_min_7 0.833 3.300 5.2 3.127 42.9 42.9 21.7 21.6 4.5 6.7 865.1 4.6

ws_avdd_min_dvdd_min_temp_max_8 0.672 3.300 10.9 3.119 37.2 37.2 16.0 15.9 3.5 5.2 1042.9 4.5

wo_avdd_max_dvdd_max_temp_min_9 0.754 3.300 5.9 3.455 44.2 44.2 22.9 22.8 4.6 7.4 889.9 5.5

wo_avdd_max_dvdd_max_temp_max_10 0.588 3.367 10.0 3.447 38.3 38.3 17.0 16.9 3.6 6.0 534.2 4.9

wo_avdd_min_dvdd_min_temp_min_11 0.742 3.300 5.3 3.126 44.2 44.2 22.9 22.9 4.6 6.9 780.2 5.1

wo_avdd_min_dvdd_min_temp_max_12 0.561 3.057 10.4 3.118 38.3 38.3 17.0 16.9 3.5 5.5 667.3 4.7

wz_avdd_max_dvdd_max_temp_min_13 0.856 3.300 18.3 3.455 44.4 44.4 23.0 23.0 5.4 7.9 376.7 6.3

wz_avdd_max_dvdd_max_temp_max_14 0.723 3.354 73.8 3.446 38.8 38.8 17.3 17.2 4.3 6.5 588.8 6.9

wz_avdd_min_dvdd_min_temp_min_15 0.839 3.300 16.7 3.127 44.4 44.4 23.0 23.0 5.3 7.4 839.6 5.8

wz_avdd_min_dvdd_min_temp_max_16 0.703 3.051 70.0 3.120 38.8 38.8 17.3 17.2 4.2 6.1 633.6 6.6

tm_avdd_min_dvdd_min_temp_typ_17 0.713 3.300 7.8 3.123 41.1 41.1 19.8 19.7 4.2 6.4 730.8 5.2

tm_avdd_max_dvdd_max_temp_typ_18 0.731 3.300 8.1 3.452 41.1 41.1 19.7 19.7 4.2 6.7 676.8 5.6

tm_avdd_typ_dvdd_typ_temp_min_19 0.797 3.300 8.2 3.291 44.3 44.3 23.0 23.0 5.0 7.4 780.0 5.8

tm_avdd_typ_dvdd_typ_temp_max_20 0.637 3.212 12.7 3.283 38.6 38.6 17.2 17.1 3.9 6.0 568.6 5.6

88

89

Appendix I: VREFP Other Facility Results (Part 1)

CONSO_1 GBW_1 GBW_2 GDC_1 GDC_2 MGAIN_1 MGAIN_2 MPHASE_1 MPHASE_2 NRMS_1 NRMS_2 SETTLING _0P5LSB14

mA MHz MHz dB dB dB dB deg deg μV μV ns

Typical 3.7 55.4 51.8 105.5 105.5 15.4 17.3 76.7 72.9 39.0 36.1 22.0

wp_avdd_max_dvdd_max_temp_min_1 4.0 95.1 88.1 104.1 104.0 12.7 14.2 76.8 71.8 36.4 33.4 18.1

wp_avdd_max_dvdd_max_temp_max_2 4.2 50.2 48.0 86.4 86.3 17.8 19.4 73.9 69.0 44.5 41.6 17.5

wp_avdd_min_dvdd_min_temp_min_3 4.0 93.1 87.0 103.9 103.9 12.9 14.2 75.6 73.9 36.1 34.0 18.4

wp_avdd_min_dvdd_min_temp_max_4 4.1 49.7 47.1 87.6 87.5 17.9 19.9 73.2 69.1 44.3 41.5 22.6

ws_avdd_max_dvdd_max_temp_min_5 3.2 68.6 62.0 107.4 107.3 12.4 14.3 80.3 77.4 36.0 32.8 23.1

ws_avdd_max_dvdd_max_temp_max_6 3.5 36.3 34.4 104.8 104.8 17.2 19.3 76.6 72.1 43.0 39.9 23.3

ws_avdd_min_dvdd_min_temp_min_7 3.2 67.3 63.6 107.3 107.3 12.6 13.8 79.3 77.3 35.7 33.8 31.5

ws_avdd_min_dvdd_min_temp_max_8 3.4 35.9 34.7 104.7 104.7 17.3 18.6 75.9 73.5 42.8 40.9 35.7

wo_avdd_max_dvdd_max_temp_min_9 3.5 76.2 70.7 107.7 107.6 12.7 14.2 77.1 72.2 35.5 32.5 37.8

wo_avdd_max_dvdd_max_temp_max_10 3.6 40.6 38.8 103.8 103.7 17.5 19.0 73.0 68.0 42.8 39.8 23.9

wo_avdd_min_dvdd_min_temp_min_11 3.4 74.8 69.8 107.6 107.6 12.8 14.1 76.0 74.3 35.2 33.1 26.1

wo_avdd_min_dvdd_min_temp_max_12 3.6 40.2 38.1 103.9 103.8 17.6 19.5 72.2 68.1 42.6 39.9 25.9

wz_avdd_max_dvdd_max_temp_min_13 3.8 85.1 77.1 103.8 103.7 12.6 14.5 80.2 77.2 36.7 33.6 21.6

wz_avdd_max_dvdd_max_temp_max_14 4.1 44.3 42.1 84.7 84.7 17.5 19.7 77.2 72.7 44.2 41.1 21.7

wz_avdd_min_dvdd_min_temp_min_15 3.7 83.3 78.9 103.6 103.6 12.8 13.9 79.2 77.2 36.4 34.5 23.2

wz_avdd_min_dvdd_min_temp_max_16 4.0 43.9 42.3 85.8 85.7 17.7 19.0 76.5 74.1 44.1 42.0 28.2

tm_avdd_min_dvdd_min_temp_typ_17 3.7 55.1 52.7 105.4 105.3 15.4 16.7 76.2 74.0 38.9 36.9 26.9

tm_avdd_max_dvdd_max_temp_typ_18 3.7 55.8 52.6 105.6 105.5 15.3 17.2 77.2 72.3 39.1 36.0 21.8

tm_avdd_typ_dvdd_typ_temp_min_19 3.6 79.9 73.0 105.8 105.8 12.7 14.2 78.1 76.3 36.0 33.3 22.9

tm_avdd_typ_dvdd_typ_temp_max_20 3.8 42.4 40.2 99.3 99.3 17.6 19.6 74.8 70.5 43.4 40.5 18.5

The obtained results with AIDA-C regarding only two different corners is presented in the previous and following tables:

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Appendix J: VREFP Other Facility Results (Part 2)

PSRR1_1 PSRR1_2 PSRR12_1 PSRR12_2

dB dB dB dB

Typical 40.1 40.1 18.5 18.6

wp_avdd_max_dvdd_max_temp_min_1 43.7 43.7 22.2 22.2

wp_avdd_max_dvdd_max_temp_max_2 39.9 39.9 18.1 18.2

wp_avdd_min_dvdd_min_temp_min_3 43.7 43.7 22.2 22.2

wp_avdd_min_dvdd_min_temp_max_4 39.8 39.8 18.1 18.1

ws_avdd_max_dvdd_max_temp_min_5 40.5 40.5 19.1 19.2

ws_avdd_max_dvdd_max_temp_max_6 36.8 36.8 15.3 15.4

ws_avdd_min_dvdd_min_temp_min_7 40.5 40.5 19.1 19.2

ws_avdd_min_dvdd_min_temp_max_8 36.8 36.8 15.3 15.3

wo_avdd_max_dvdd_max_temp_min_9 41.9 41.9 20.5 20.5

wo_avdd_max_dvdd_max_temp_max_10 38.1 38.1 16.5 16.6

wo_avdd_min_dvdd_min_temp_min_11 41.9 41.9 20.5 20.5

wo_avdd_min_dvdd_min_temp_max_12 38.1 38.1 16.4 16.5

wz_avdd_max_dvdd_max_temp_min_13 42.2 42.2 20.7 20.8

wz_avdd_max_dvdd_max_temp_max_14 38.5 38.5 16.8 16.9

wz_avdd_min_dvdd_min_temp_min_15 42.2 42.2 20.7 20.7

wz_avdd_min_dvdd_min_temp_max_16 38.5 38.5 16.8 16.8

tm_avdd_min_dvdd_min_temp_typ_17 40.1 40.1 18.5 18.6

tm_avdd_max_dvdd_max_temp_typ_18 40.1 40.1 18.6 18.6

tm_avdd_typ_dvdd_typ_temp_min_19 42.1 42.1 20.6 20.7

tm_avdd_typ_dvdd_typ_temp_max_20 38.3 38.3 16.7 16.7

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