Design of a Secondary Side Regulated LLC Based Integrated PEV Onboard Charger with Full ZVS Range

Zhiqing Li, Student Member, IEEE and Haoyu Wang, Member, IEEE School of Information Science and Technology

ShanghaiTech University Shanghai, China

wanghy@shanghaitech.edu.cn

ABSTRACT — This paper proposes an integrated onboard charger architecture for plug-in electric vehicles (PEVs). In this architecture, the phase shifted full bridge topology (PSFB) with voltage doubler rectifier serves to charge the high voltage battery pack. A half-bridge secondary side regulated LLC based topology (SSR-LLC) is employed to supply power to the onboard auxiliary battery. The half-bridge SSR-LLC converter shares its primary side switching network with the PSFB converter. This switches’ reuse guarantees that the lagging leg switches of the PSFB converter operate under full zero voltage switching (ZVS) condition. The voltage regulations of the PSFB converter and the SSR-LLC converter are achieved by phase shift and duty cycle modulation of the secondary side switch, respectively. Hence, the outputs of the two converters can be controlled independently. In the integrated onboard charger, all the MOSFETs can achieve full range ZVS and all the power diodes work under zero current switching (ZCS) condition. A 250 kHz, 390 V input, 250-420 V/1 kW, 14 V/300 W outputs converter prototype is designed to verify the proof of concept. The PSFB converter in the integrated architecture demonstrates large efficiency improvement compared with the conventional PSFB converter.

Keywords—onboard charging; PEV; PSFB; SSR-LLC; ZVS;

I. INTRODUCTION

In modern PEVs, a high voltage battery pack is installed onboard mainly to drive the propulsion motor. Additionally, a low voltage battery is employed to supply power to the conventional low-voltage loads such as head lamps, wiper blade motor, electronic power steering, stereo system [1], [2] etc. In the typical two-stage onboard charger, an isolated dc/dc converter is used to link the dc bus and the propulsion battery. Besides, a dc/dc converter with high step down ratio serves as the interface between the dc bus and the auxiliary battery [1], [3]. The system volume, weight and efficiency of the onboard charger are highly restrained. Especially, to improve the power density and efficiency, a high switching frequency with good soft switching feature is recommended.

Over the past years, many ZVS topologies have been proposed as the second stage dc/dc converter of the PEV onboard charger. In [4], a LLC-based multi-resonant converter is adopted. In [5], a ZVS full-bridge converter with trailing edge pulse width modulation and capacitive output filter is proposed. While in [6], a resonant converter is cascaded by a discontinuous conduction mode buck converter.

The PSFB topology with voltage doubler rectifier is also a good candidate to achieve the dc/dc conversion in the second stage of the onboard charger. This is mainly due to its advantages such as: simple structure, high efficiency, good voltage regulation capacity and clamped voltage stresses of the rectifier diodes [7]–[12]. However, under light load conditions, with the increase of the phase shift angle, the lagging leg switches of the PSFB converter lose ZVS feature. This phenomenon increases the switching losses and constrains the switching frequency. Many techniques have been proposed to extend the ZVS range of the PSFB converter [13]–[19]. In [13]–[17], either active or passive auxiliary circuits are used to guarantee ZVS of the lagging leg switches at light loads. However, all those converters suffer from increased components count. In [18], a magamp secondary-side control method is employed to achieve ZVS with minimal circulating power. However its control complexity is significantly increased. In [19], a saturable inductor replaces the leakage inductor to enhance the ZVS performance. However, the saturable inductor also raises heat issues.

This paper proposed a reconfigurable PEV onboard charger. The lagging leg switches of the PSFB converter are reused by the SSR-LLC converter. When the ZVS condition of the SSR-LLC converter is satisfied, all the switches of the PSFB converter including the lagging leg switches can achieve ZVS simultaneously. Besides, the body diode of the secondary auxiliary switch in the SSR-LLC converter conducts prior to the turning on of the channel, ZVS of this auxiliary switch can be also realized. Moreover, ZCS and almost zero reverse recovery losses can be achieved by all the power diodes in the integrated charger. This integrated architecture is featured with the following advantages: 1) full soft switching for all the semiconductor devices; 2) high efficiency; and 3) high power density.

II. PROPOSED SELF-RECONFIGURABLE INTEGRATED PEV

ONBOARD CHARGER

The proposed reconfigurable PEV onboard charger is depicted in Fig. 1. The PSFB converter with voltage doubler rectifier serves to charge the high voltage battery park. The output of the PSFB converter is regulated by varying the phase shift angle between the leading leg switches (S1, S2) and the lagging leg switches (S3, S4). The half-bridge SSR-LLC converter is a high step-down ratio dc/dc converter to supply power to the auxiliary battery and some other onboard low-voltage loads. By switching the two channel contractor from vde

This work was supported in part by the National Natural Science Foundation of China under Grant 51607113, and in part by the Shanghai SailingProgram under Grant 16YF1407600.

978-1-5090-5366-7/17/$31.00 ©2017 IEEE 1394

to vbc, the primary half bridge of the SSR-LLC converter can be reconfigured to the lagging leg of the PSFB converter. It should be noted that the voltage regulation of the SSR-LLC converter is achieved by the duty cycle modulation of S5.

According to the state of the contractor, and the direction of the power flow, the reconfigurable PEV onboard charger has two operation modes. In the first mode, the contractor is attached to vbc; the power is delivered from the dc bus to the high voltage battery and the auxiliary battery. While in the second mode, the contractor is attached to vde; the high voltage battery serves to charge the auxiliary battery. Since the operation principles of the SSR-LLC converter in the second mode are covered by the first mode, the following analysis is based on the first mode. The equivalent circuit of the first mode is illustrated in Fig. 2.

Fig. 3 shows the driving waveforms of S1-5 in the first mode. The switching frequency (fs) of S1-5 is constant and equal to the resonant frequency (fr) between Lr and Cr. The switching signals of the primary same leg switches are complementary with certain deadband (tdead). The phase shift angle (ϕ) between S1-2 and S3-4 is used to regulate the output of the PSFB converter. Besides, a minor delay (tdelay) is enforced between the turning on of S5 and the deadband between S3 and S4. In the SSR-LLC converter, by actively controlling the duty ratio (D) of S5, the output voltage changes accordingly.

A. Operation Modes of the PSFB converter

The PSFB converter employs a voltage-doubler rectifier without output filter inductor. This simple structure brings some benefits: 1) zero duty cycle losses, 2) low conduction losses, and 3) clamped voltage stresses of the rectifier diodes. According to the current waveform of the primary-side inductor (LLk), the

PSFB converter has two possible operation modes, namely continuous-conduction mode (CCM), and discontinuous-conduction mode (DCM), respectively.

1) CCM When the PSFB converter operates with high power and

small ϕ, it operates in CCM. Assuming that all the switches and passive components are ideal, and the deadband is ignored, the key waveforms are illustrated in Fig. 4. α is defined to be the equivalent phase angle during which iL returns to zero from the negative rising edge of vab. In CCM, α ≥ 0.

2) DCM The key waveforms of the DCM operation are plotted in Fig.

5. As shown, iL returns to zero before the negative rising edge of vab. β is defined to be the equivalent phase angle during which iL returns to zero after vab changes to be zero.

In the PSFB converter, Po and Io are the output power and load current, respectively; Ts is the switching period. The normalized gain (G) is defined as,

2

Hbat

Bus

nVG

V= (1)

In CCM, according to the voltage-second balance of LLk,

( ) ( )1 ( ) 1G G Gπ α ϕ ϕ α− − − = + + (2)

The intervals of (π - α - ϕ), α and ϕ are represented by t1, t2 and (0.5Ts - t1 - t2),

( )1 2

sTt

π α ϕπ

− −= 2 2

sTt

απ

= (3)

Fig. 1. The proposed reconfigurable PEV onboard charger.

Fig. 2. Equivalent circuit when power flows from the dc bus to the high voltage battery and the auxiliary battery.

Fig. 3. Switch pattern of S1-5.

Fig. 4. The key waveforms of the PSFB converter in CCM.

1395

Assuming zero power losses, the load current is equal to the average current value through D1, Io can be expressed,

( ) ( ) ( ) ( ){ }21 1 2 2 1 2 1 21 2 1 1 1

2 2

Busoo

Bus s Lk

nV G t G t Gt t G t Gt t tnPI

GV T L

− + − − + − − − − = = (4)

Since equations (2)-(4) are nonlinear, it is difficult to derive an analytical expression of G. While its numerical values can be easily solved in MATLAB.

In DCM, according to the voltage-second balance of LLk,

( )1 ( )G Gπ ϕ β− − = (5)

The intervals of (π - β - ϕ) and β are represented by t3 and t4,

( )3 2

sTt

π ϕπ−

= 4 2sT

tβπ

= (6)

Io can also be derived in DCM,

( ) ( )3 3 41

2 2Buso

oBus s Lk

nV G t t tnPI

GV T L

− += = (7)

Combining equations (5)-(7), G in DCM can be solved analytically,

22

1

2

Lk o

s Bus

L PG

T Vπ ϕ

π

= −−

(8)

Correspondingly, the curve of the normalized gain versus phase shift angle is plotted in Fig. 6. As shown, with the decrease of power level, the PSFB is prone to enter into DCM. It should be noted that the boundary between CCM and DCM happens when t2 = 0 or t3 + t4 = Ts/2.

B. Half-bridge SSR-LLC converter

The SSR-LLC converter is derived from the conventional LLC topology with secondary side pulse width modulation. Co3 and Co4 are two large filter capacitors. Compared with the topology proposed in [20], the inductor in the secondary side is removed. Besides, a minor delay (tdelay) is enforced between the turning on of S5 and the deadband between S3 and S4. The steady state waveforms of the half-bridge SSR-LLC converter are plotted in Fig. 7. Each switching period can be divided into six modes.

Mode I: [t0, t1). Mode I includes the deadband of S3-4 and tdealy. At the beginning of Mode I, ir charges and discharges the output capacitors of S3-4. S4 turns on with zero voltage. vCr can be seen constant. Hence, vbc and vs,l decreases simultaneously. When vs,l reaches zero, the secondary side conducts and the output capacitor of S5 starts to be discharged by is,l. Since is,l decreases from zero and is small, tdealy is added to ensure the ZVS of S5. At the end of Mode I, S5 turns on with zero voltage.

Fig. 5. The key waveforms of the PSFB converter in DCM.

Fig. 6. The normalized gain versus phase shift angle under different power level.

Fig. 7. The steady state operation waveforms of the half-bridge SSR-LLC converter.

1396

Mode II: [t1, t2). In Mode II, vbc is zero and –VCo4 is connected to the secondary side of the transformer. Cr and Lr resonate.

Mode III: [t2, t3). S4 is turned off. ir begins to discharge the output capacitor of S3. S3 turns on with zero voltage. At the end of Mode III, is,l increases to be zero.

Mode IV: [t3, t4). In Mode IV, vbc is equal to VBus; is,l increases from zero. VCo3 is connected to the secondary side of the transformer.

Mode V [t4, t5). Mode V starts as S5 is turned off at t4. Since the inductor current is continuous, the current is switched from S5 to D5. Hence, VLbat is directly connected to the secondary side of the transformer. Since VLbat is much larger than VCo3, it incurs is,l to decrease. Mode V ends when is,l reaches zero.

Mode VI [t5, t6). At t5, is reaches zero and the circuit enters into Mode VI. Since S5 is still off, is,l stays at zero. Thus, all the semiconductors on the secondary side are off. Mode VI ends when the switch pattern of S3, S4 is inverted again, which marks the start of next switching cycle.

C. The integrated charger

When power is delivered from the dc bus to the high voltage battery pack and auxiliary battery, the PSFB converter and the SSR-LLC converter work synergistically. The working conditions of the two converters are independent with each other except that the currents through S3,4 are equal to the sum of iL and ir. The corresponding key waveforms are plotted in Fig. 8.

III. DESIGN CONSIDERATIONS

To design the proposed integrated PEV onboard charger, the optimizations of soft switching, power density, and system efficiency should be considered.

A. Soft-switching characteristics

1) Active switches In order to realize ZVS, the current through the corresponding switch should be sufficiently negative to fully discharge the output capacitor before the channel conducts. According to the operation principles of the PSFB converter, the body diodes of the primary leading leg switches (S1-2) always conduct before the conduction of MOSFET channels, no matter in DCM or CCM. Therefore, ZVS can be achieved

easily for S1 and S2. However, at light load condition in CCM, or in DCM, the lagging leg switches (S3-4) turn-on currents are small or zero, respectively. Hence, S3-4 lose ZVS feature. However, in the integrated charger, the joint force of iL and ir work together to enhance the lagging leg ZVS performance. It is illustrated in Fig. 9. The full ZVS range means that ZVS should be realized even when the PSFB converter works in DCM and the SSR-LLC converter works in very light load conditions. Hence, the responding turning on currents of the S3 and S4 can be approximated as,

3 4 2 4Bus s

s sm

V TI I

L≈ ≈ (9)

The current should be able to discharge MOSFETs’ output capacitors within deadband, which leads to the equation,

16s dead

moss

T tL

C≤ (10)

where, Coss is the output capacitance of S3 and S4.

As Fig. 7 shows, tdelay is the time duration between the turning on of S5 and the deadband of S3-4. In Mode I, is,l decreases from zero to discharge the output capacitor of S5, and then goes through its body diode. Therefore, when tdelay is large enough, it is ensured that the S5’ drain to source voltage decreases to zero before its channel conducts.

2) Power diodes In the PSFB converter, the currents through D1 and D2 are linear which are constrained by LLk. Hence, the currents of D1 and D2 always decrease to zero with small di/dt. is,l in the SSR-LLC converter is piecewise which equals to a sine-wave subtracting a triangular-wave. As shown in Fig. 7, the di/dt of is,l is also limited. Hence, D3-5 can also achieve ZCS turning off.

B. System efficiency

To design the charging system with high efficiency, the magnetic components (LLk, Lm) should be optimally designed. To determine the impact of LLk on the conduction losses in DCM, the relationship between RMS value of iL and LLk is derived as,

ids3

vgs3

t

t

ids4

vgs4

t

t

0

0

0

0

Fig. 8. The waveforms when a synergy is established between the operations of the SSR-LLC converter and the PSFB converter.

DS4

DS3

vc

VBus

vb

iL

ir

Coss3

Coss4

Fig. 9. The joint force of iL and ir during commutation of S3 and S4.

1397

1

4

1 1 1

4 2 2

3 1

4 4 (1 )2

3o s

Lrms

Lk Bus

P T GI

L G V

−= (11)

It can be seen when LLk increases, ILrms decreases, which responds to lower conduction losses. This is also true in CCM according to the numerical analysis. However, it should be noted that a significant increase of LLk leads to a much smaller decrease of ILrms. To select LLk, some other factors should be taken into consideration.

The voltage gain of the PSFB converter is highly relevant to LLk. When LLk increases, the voltage gain of the PSFB converter decreases in both DCM and CCM. Admittedly, n can be reduced to improve the voltage gain. However, this improvement is limited. With a fixed LLk, the maximum voltage gain exists no matter how small n is. The maximum voltage gain is provided with ϕ = 0, when the PSFB converter works in CCM. In such condition, to meet the requirements of output voltage and power rating, the following equation of n and LLk should be valid,

( )22

032

HbatBus s Bus s Hbat

o

Hbat Lk Bus

nVn V T V nT V

PI

V L V

− + Δ = − =

(12)

Graphical analysis helps to solve this equation. The curves of ΔΙ versus n are plotted in Fig. 10. When ΔΙ intersects with 0, Eq. (12) is satisfied and the maximum output voltage and power rating can be reached with the responding LLk and n. Some other conclusions can also be made from the graphical analysis:

1) When LLk is larger than a boundary value, Eq. (12) has no roots and the desired voltage gain can’t be achieved. For example, in Fig. 10 (a), when LLk is equal to 40 μΗ.

2) When switching frequency increases, the maximum LLk decreases. This can be observed by comparing Fig. 10 (a) with (b).

3) When power rating increases, the maximum LLk decreases. This can be observed by comparing Fig. 10 (b) with (c).

4) There may be two intersections with the same LLk. In Fig. 10 (b), Points n1 and n2 are labeled. However, the smaller n1 brings higher current stresses of iL with higher conduction losses. Hence, the larger n2 is preferred.

To conclude, with preset fs, maximum output voltage, and power rating, the maximum LLk can be obtained accordingly.

Meanwhile, how to design the physical inductor is another important factor when selecting LLk. If LLK is too large to be integrated into the transformer, an external inductor is needed. This degrades the power density and brings some extra core losses and copper losses. It is recommended to utilize the transformer leakage inductance and make it close to the maximum value defined by Eq. (12).

To minimize the switching losses, Lm needs to be sufficiently small to facilitate ZVS of switches. Meanwhile, the decrease of Lm responds to the increase of circulating current in the SSR-LLC converter. Hence, considering both conduction losses and switching losses, Lm is selected as its upper limit defined by Eq. (10).

It should be noted that this integrated structure helps to improve the efficiency. First, a half-bridge driver and its corresponding loss can be avoided. Second, the switching losses is reduced remarkably due to the realization of full range ZVS.

C. Magnetic components volume

Two inductors (LLk, Lr) are integrated into two transformers, respectively. Hence, no extra space is needed for large external inductors.

The maximum flux through T1 is when the PSFB converter works in CCM and output voltage is the maximum. To avoid the magnetic saturation,

0 0.5 1 1.5 2-2

-1

0

1

2

3

4

5

n

n1 n2

Po= 1000 Wfs = 100 kHz

(b)

LLk = 70 H LLk = 60 H LLk = 50 H

LLk = 40 H

LLk = 80 H

0 0.5 1 1.5 2-2

-1

0

1

2

3

4

5

n(a)

LLk = 40 H

LLk = 30 H

LLk = 20 H

Po= 1000 Wfs = 200 kHz

0 0.5 1 1.5 2-2

-1

0

1

2

3

4

5

n

LLk = 40 H

LLk = 50 H LLk = 60 H

(c)

Po= 1300 Wfs = 100 kHz

Fig. 10. ΔI versus n with various LLk in the PSFB converter. (VBus = 390 V, VHbat = 420 V)

1398

_ max

1 4Hbats

s es

VTB A

n> (13)

where, Bs is the core saturation flux density; np1, ns1 are the primary and secondary turns numbers in T1; Ae is the core cross-sectional area; VHbat_max is the maximum output voltage. As shown, only ns1 is constrained in Eq. (13). The relationship between np1:ns1 and LLk is described in Section III-B. For the preset LLk, np1, ns1 can be determined respectively.

Similar considerations are taken to design T2. The SSR-LLC converter works at the resonant frequency. Hence, the voltage applied to the primary side of T2 is approximately square wave with magnitude of 0.5VBus. Accordingly,

2 4s Bus

s p e

T VB n A > (14)

where, np2 is the primary turns numbers of T2.

In the integrated charger, higher switching frequency can be reached since soft switching is realized among all semiconductors. This leads to an increased power density.

IV. EXPERIMENTAL RESULTS

A 250 kHz, 390 V input, 250-420 V/1 kW, 14 V/300 W outputs converter prototype is built to verify the theoretical analysis. The key parameters of the prototype are listed in Table I. In the experiments, the high voltage battery pack and the low voltage battery are emulated by resistive loads (RH and RL), respectively.

In Fig. 11 (a), ϕ = 0 and the standalone PSFB converter works at full load condition (1000 W). The PSFB converter works in CCM and S1-4 all achieve ZVS. The system efficiency is measured as 94.5%. With constant RH, the increase of ϕ leads to the decrease of output voltage and power. When the power level decreases to 78% full load, the PSFB converter enters into DCM. Due to the hard switching and high switching frequency, the switching losses and EMI increases sharply. This causes the failures of IRFP460 MOSFETs. To resume the normal operation, in Fig. 11 (b), a synergy is established between the operations of the SSR-LLC converter at light load condition and the PSFB converter in DCM. ZVS of the lagging leg

switches can be realized as shown in Fig. 11 (c). The working condition of S3 is similar to that of S4. In Fig. 11 (d), the waveforms of vgs5, vds5 and ir are captured. S5 achieves ZVS. It is worthy to mention that a voltage spike occurs during the turning off transition of S5. This voltage spike or ringing is due to the resonance between the stray inductance and output capacitor of S5. With optimized printed circuit board design, the voltage spike should be mitigated. Meanwhile, by observing the current waveforms, there is no steep change. It means that the reverse recovery process can be eliminated during the turning off of D1-D5.

TABLE I DESIGN PARAMETERS OF THE PROTOTYPE

components Parameters Inductor (LLk) 20.4 μH

Resonant inductor (Lr) 9.5 μH Magnetizing inductor (Lm) 120 μH Turns ratio of T1 (np1 : ns1) 16:10

Turns ratio of T2 (np2 : ns2) 27:1

Resonant capacitor (Cr) 44 nF Filter capacitor (Co1-Co4) 120 μF

High voltage MOSFETs (S1-4) IRFP460

Low voltage MOSFETs (S5) IPB055N03L

High voltage diodes (D1-2) C3D10060A

Low voltage diodes (D3-5) MBRB4030G

Fig. 11. The steady state scope waveforms of the integrated charger: a) vab, vs,h and iL (CCM); b) vab, vs,h and iL (DCM); c) vgs4, vds4, iL and ir; and b) vgs5, vds5 and ir

1399

The system efficiency of the PSFB converter with enhanced ZVS performance is plotted in Fig. 12. It can be seen, even when the PSFB converter enters into DCM (<=780 W), it still maintains a high system efficiency. While, since Lm is designed to ensure the full range ZVS, it is relatively small. Therefore, the circulating current in the SSR-LLC converter is large. This degrades the efficiency of the SSR-LLC converter, especially at light load conditions. The efficiency of the whole integrated charger can only reach around 92.2%, when the SSR-LLC works at 20% load condition. The future work will focus on improving this situation. The tradeoff between conduction losses and switching losses should be considered to design optimal Lm.

V. CONCLUSIONS

In this paper, an integrated onboard charger architecture for PEVs is proposed. The PSFB converter and the SSR-LLC converter are adopted as the high voltage battery charger and the low voltage charger, respectively. The legging leg ZVS loss issue in the PSFB converter is eliminated with the switching network reuse. Meanwhile, in the integrated structure, all the power diodes and MOSFETs can achieve soft switching. Hence, the switching frequency can be increased to boost the power density. The voltage regulation of the SSR-LLC converter is achieved by duty cycle modulation of S5. This wouldn’t conflict with the phase shift modulation of the PSFB. Therefore, the primary full bridge operates at fixed switching frequency which ensures that the SSR-LLC works at the optimal resonant point. Experimental results of the prototype have verified the soft switching performance of the proposed structure and the efficiency improvement of the conventional PSFB converter.

REFERENCES

[1] C. Shi, H. Wang, S. Dusmez, and A. Khaligh, “A SiC-based, high-efficiency, isolated onboard PEV charger with ultra-wide dc link voltage range,” IEEE Trans. Ind. Appl., in press, DOI: 10.1109/TIA.2016.2605063

[2] A. Emadi and K. Rajashekara, “Power Electronics and Motor Drives in Electric, Hybrid Electric, and Plug-In Hybrid Electric Vehicles,” IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 2237–2245, 2008.

[3] H. Wang, M. Shang, and A. Khaligh, “A PSFB based integrated PEV onboard charger with extended ZVS range and zero duty cycle loss,” IEEE Trans. Ind. Appl., in press, DOI: 10.1109/TIA.2016.2615034

[4] H. Wang, S. Dusmez, and A. Khaligh, “Design and Analysis of a Full-Bridge LLC-Based PEV Charger Optimized for Wide Battery Voltage Range,” IEEE Trans. Veh. Technol., vol. 63, no. 4, pp. 1603–1613, May 2014.

[5] D. S. Gautam, F. Musavi, W. Eberle, and W. G. Dunford, “A Zero-Voltage Switching Full-Bridge DC--DC Converter With Capacitive Output Filter for Plug-In Hybrid Electric Vehicle Battery Charging,” IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5728–5735, Dec. 2013.

[6] J.-Y. Lee and H.-J. Chae, “6.6-kW Onboard Charger Design Using DCM PFC Converter With Harmonic Modulation Technique and Two-Stage DC/DC Converter,” IEEE Trans. Ind. Electron., vol. 61, no. 3, pp. 1243–1252, Mar. 2014.

[7] S. Dusmez, A. Cook and A. Khaligh, "Comprehensive analysis of high quality power converters for level 3 off-board chargers," in Proc. IEEE Vehicle Power and Propulsion Conference, Chicago, IL, 2011.

[8] W. Chen, F. C. Lee, M. M. Jovanovic and J. A. Sabate, "A comparative study of a class of full bridge zero-voltage-switched PWM converters," in Proc. IEEE Applied Power Electronics Conference and Exposition, Dallas, TX, 1995.

[9] W. J. Lee, C. E. Kim, G. W. Moon, and S. K. Han, “A new phase-shifted full-bridge converter with voltage-doubler-type rectifier for high-efficiency PDP sustaining power module,” IEEE Trans. Ind. Electron., vol. 55, no. 6, pp. 2450–2458, 2008.

[10] B. P. McGrath, D. G. Holmes, P. McGoldrick, and A. McIver, “Design of a Soft Switched 6kW Battery Charger for Traction Applications,” in Proc. IEEE Power Electronics Specialists Conference, Jeju, South Korea, 2006.

[11] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, “Design considerations for high-voltage high-power full-bridgezero-voltage-switched PWM converter,” in Proc. IEEE Applied Power Electronics Conference and Exposition, Los Angeles, CA, 1990.

[12] J. M. Zhang, X. G. Xie, X. K. Wu, and Z. Q. Z. Qian, “Comparison study of phase-shifted full bridge ZVS converters,” in Proc. IEEE Power Electronics Specialists Conference, Aachen, Germany, 2004.

[13] I. O. Lee and G. W. Moon, “Soft-switching DC/DC converter with a full ZVS range and reduced output filter for high-voltage applications,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 112–122, 2013.

[14] A. F. Bakan, N. Altintaş and İ Aksoy, “An improved PSFB PWM DC-DC converter for high-power and frequency applications,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 64–74, 2013.

[15] M. Pahlevaninezhad, P. Das, J. Drobnik, P. K. Jain and A. Bakhshai, "A Novel ZVZCS Full-Bridge DC/DC Converter Used for Electric Vehicles," IEEE Trans.Power Electron., vol. 27, no. 6, pp. 2752-2769, 2012.

[16] G. B. Koo, G. W. Moon, and M. J. Youn, “Analysis and design of phase shift full bridge converter with series-connected two transformers,” IEEE Trans. Power Electron. Power Electron., vol. 19, no. 2, pp. 411–419, 2004.

[17] H. S. Choi, J. W. Kim, and B. H. Cho, “Novel zero-voltage and zero-current-switching (ZVZCS) full-bridge PWM converter using coupled output inductor,” IEEE Trans. Power Electron., vol. 17, no. 5, pp. 641–648, 2002.

[18] R. Watson and F. C. Lee, “Analysis, design, and experimental results of a 1-kW zvs-fb-pwm converter employing magamp secondary-side control,” IEEE Trans. Ind. Electron., vol. 45, no. 5, pp. 806–814, 1998.

[19] G. Hua, F. C. Lee, and M. M. Jovanovic, “Improved full-bridge zero-voltage-switched PWM converter using a saturable inductor,” IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530–534, 1993.

[20] H. Wang, “A pulse width modulated LLC type resonant topology adpated to wide output voltage range,” in Proc. IEEE Applied Power Electronics Conference and Exposition, Long Beach, CA, 2016.

Fig. 12. Efficiency versus output power curves of the PSFB converter with enhance ZVS performance.

1400