Design of a Novel Envelope Detector for Fast-Settling Circuits

4 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 57, NO. 1, JANUARY 2008

Design of a Novel Envelope Detectorfor Fast-Settling Circuits

J. P. Alegre, Santiago Celma, Member, IEEE, Belén Calvo, and Jose Maria García del Pozo

Abstract—A novel envelope detector structure that overcomesthe traditional tradeoff required in these circuits, improving boththe tracking and keeping of the signal, which is specially advan-tageous for fast-settling circuits, is proposed in this paper. Themethod relies on holding the signal by two capacitors in parallel,discharging one when the other is in the hold mode and employingthe held signals to form the output. Results show a savings greaterthan 60% of the capacitor area for the same ripple (< 1%) anda release time constant that is 13 times smaller than that obtainedby conventional circuits.

Index Terms—Adaptive control, data acquisition, envelope de-tection, gain control, peak detectors.

I. INTRODUCTION

H IGH-PERFORMANCE envelope detectors are requiredto obtain the amplitude of the signal in a great variety

of circuits, mainly for gain control circuits and spectral energyestimation over a variety of applications, such as hearing aids,cochlear implants, speech recognition front ends [1], and, es-pecially, in wireless communication receivers [2]. Furthermore,some adaptive bias techniques for linearity enhancement and dccurrent reduction in radio frequency amplifiers are also basedon envelope power detection [3]. The design of an accurateenvelope detector is critical for an efficient magnitude lockedloop Q-tuning method used in high-Q high-frequency continu-ous time filters [4]. A new generation of dynamically varyinganalog circuits need high-performance envelope detectors tooptimize the signal-to-noise ratio (SNR) and power dissipation,such as dynamic gain scaling (syllabic companding) [5], dy-namic impedance scaling [6], dynamic biasing [7], and dynamicstructure variation [8].

The conventional diode-RC peak detector is very simpleand inefficient for these applications [9]. OpAmp- and diode-based envelope detectors have the problem of high distortionduring the zero crossing of the input signal as the OpAmps haveto recover during nonconduction/conduction transition with asmall finite signal dV/dt (slew rate). The envelope detectoris, thus, limited to a frequency performance well below thegain bandwidth product of the amplifier. An improvement is touse current mode rectifiers that can operate at higher frequen-

Manuscript received July 15, 2006; revised September 17, 2007. This workwas supported in part by the Ministerio de Educación y Ciencia (MEC) underGrant AP-2004-5895, by Diputación General de Aragón-Fondo Social Europeo(DGA-FSE) under Grant PIP187/2005, and by the MEC-Fondo Europeo deDesarrollo Regional (FEDER) under Grant TEC2005-00285/MIC.

The authors are with the Department of Electronic and CommunicationsEngineering, University of Zaragoza, 50009 Zaragoza, Spain (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/TIM.2007.909618

Fig. 1. Envelope detection principle. Voltage-to-current conversion, rectifica-tion, and amplitude detection.

cies than the diodes [10]. Other envelope detectors are basedon root-mean-square-type circuits. However, all mentionedschemes suffer from the same limitation: the tradeoff betweenthe keeping and the tracking of the signal that makes the useof filters at the output necessary to minimize the ripple of theenvelope at the cost of a higher settling time. In this paper, anovel envelope detector based on the scheme proposed in [11] isdeveloped. A high-performance conventional envelope detectoris projected and, after that, modified so that it overcomes thetraditional tradeoff required in these circuits, improving boththe tracking and the keeping of the signal.

This paper is organized as follows. In Section II, the con-ventional envelope detector and its limitations are introduced.The proposed modifications are explained in Section III. InSection IV, we present simulation results. Finally, in Section V,summarized conclusions are offered.

II. CONVENTIONAL ENVELOPE

DETECTOR ARCHITECTURE

Envelope detectors have made great improvements in per-formance since the conventional diode-RC peak detector wasproposed. Some recently published structures exhibit highaccuracy and linearity at higher frequencies. However, theremust still be some compensation between keeping and trackingoperations. If we want very good keeping of the signal, we canuse a very small time constant to obtain a small edge of sharpteeth (or ripple), but this way, we reduce the tracking capabilityfor the next peak. On the other hand, if we use a larger timeconstant, we improve the tracking capability but have a largeredge of sharp teeth.

This paper proposed a novel envelope detector scheme, fol-lowing the idea given in [11], which improves on the conven-tional counterpart. Thus, we first present an envelope detectorthat was built by following the latest techniques, and then, wemodify it using the technique proposed in this paper.

The objective in our work was to obtain a high-performanceenvelope detector with a performance frequency between 1and 10 MHz and input amplitudes above 300 mV. Since it

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ALEGRE et al.: DESIGN OF A NOVEL ENVELOPE DETECTOR FOR FAST-SETTLING CIRCUITS 5

Fig. 2. Schematic diagram of the full-wave precision rectifier.

Fig. 3. Schematic diagram of the mirrored cascode OTA.

Fig. 4. Schematic diagram of the proposed peak detector.

is not possible to use OpAmp- and diode-based rectifiers atthese frequencies, we have used open-loop configurations, asshown in Fig. 1 [12]. This kind of circuit makes use of anOperational Transconductance Amplifier (OTA) for voltage-to-current conversion, followed by a precision rectifier anda current mode peak detector, and differs from the originalprinciple in this latter stage, since originally, integration wasmade. Due to the fact that the OTA performs the voltage-to-current conversion in an open loop, this circuit is capable ofworking at higher frequencies. However, the basic cells havebeen chosen slightly differently.

A. Rectifier

The precision rectifier used for this work is based on theconfiguration proposed in [10], as shown in Fig. 2. This cellhas been chosen due to its linearity for frequencies of up to100 MHz and input signals above 150 µA. The bias voltage VBr


Fig. 5. Proposed envelope detection principle.

Fig. 6. Schematic diagram of the peak hold.

Fig. 7. Schematic diagram of the control path.

is used to bias M5a and M5b to have drain currents of 2.5 µA.The bias voltage in this rectifier is similar to a threshold currentand does not rectify signals below this current. Originally, a0.25-µA bias current was employed, but the direct coupling ofthe OTA demanded smaller input resistance and, consequently,a higher bias current. The solution to this problem was togenerate an offset current by the OTA with a value that isslightly higher than the bias current, so the signal is alwaysabove the threshold current.

B. OTA

As high input frequencies, direct coupling, and good controlof the output offset current are required, the design of the OTAis started with the fully differential version of the mirroredcascode OTA (see Fig. 3). The bias voltages VB1 and VB2

control the offset current required for the next stage and,

indirectly, the common-mode voltage at the output of the OTA.Due to the direct coupling between the OTA and the rectifier,the offset current biases the diode-form transistor at the inputof the rectifier, whereas the rectifier’s input resistance fixes thecommon-mode voltage at the output of the OTA. This makesthe common-mode feedback circuit unnecessary.

C. Peak Detector

Fig. 4 shows the cell of the peak detector that is suitablefor operation up to frequencies of 10 MHz. The peak detectorconsists of a slow source follower composed of M3, IL, CL, andthe feedback transistor M1a [13]. The transistor M1b outputsa copy of the current in M1a, whereas transistors M2a,b areintroduced to obtain a higher output resistance and, thus, tominimize the offset current at the output. The source followercan rapidly follow descending signals in the input voltagebecause of the exponential dependence of the current of M3

on its gate voltage. However, the small current IL is slow incharging capacitor CL; as a result, during ascending signals inthe input, the output signal is slow to respond. Consequently,the ripple and time constant τ are controlled by IL and CL.

III. PROPOSED ENVELOPE DETECTOR ARCHITECTURE

Fig. 5 shows the conceptual scheme of the proposed envelopedetector. As can be seen, the circuit works in parallel, as


Fig. 8. Ripple of the conventional (dashed line) and the proposed envelope(solid line) detectors for an input voltage of 300 mV at 10 MHz and a totalcapacitance of 3.2 pF.

Fig. 9. Tracking of (- -) ideal, (- .) conventional, and (–) proposed envelopedetectors for a step signal at 10 MHz and a ripple of 1%.

proposed in [11]. In this section, we demonstrate that it isunnecessary to duplicate all the circuits; in fact, no more than apart of the peak hold circuit is duplicated, as will be shown later.

To obtain the modified circuit, peak hold circuits are em-ployed instead of the peak detector to obtain a smaller ripple.The switches at the peak holds and the output are managed by asquare signal provided by two control circuits. The control pathchanges the phase of the input signal by 90 before generatingthe digital signal by a few inverters. Thus, the peak hold is inthe hold mode just when the signal has reached its maximumvalue. This characteristic allows us to employ smaller loadcapacitance without spoiling the dc level obtained during thehold mode. To obtain the envelope of the signal, two peak holdswork in parallel, with one of them always providing a signal inthe hold mode at the output.

In return for this increase in the circuit complexity, thenew envelope detector offers the following high-performancecharacteristics: 1) a much smaller configurable release time

Fig. 10. (o) DC and (-) 10 MHz transfer characteristics for the conventionaland the proposed envelope detectors.

constant; 2) a smaller ripple that is independent of the dischargecurrent IL; 3) smaller capacitances; and 4) a significant reduc-tion in the circuit area.

The OTA and the rectifier are the same ones employed forthe conventional envelope detector. In the following, the controlpath and the peak hold shown in Fig. 5 are introduced.

A. Peak Hold Circuit

The proposed peak hold circuit is shown in Fig. 6. Theadvantage of using current mirrors makes it unnecessary toduplicate all the circuits to obtain two peak holders. Bothcircuits work with the same discharge path during differentperiods: When the first peak holder is in the hold mode, thesecond one is discharging, and vice versa. VC1 and VC2 arethe signals provided by the control path, which manage theswitches of the peak holds.

The power consumption is increased by 50% at this stage.However, we have to consider that more than 90% of the powerconsumption of the circuit is due to the OTA; consequently,this increase is insignificant. Furthermore, two capacitances areemployed instead of one, but the total capacitance is muchsmaller than the original. On the other hand, this configurationhas a great advantage: The release time constant is given by CL

and IL, whereas the ripple depends on CL and the equivalentresistance of the switches when working in subthreshold. Thisresistance is very high and offers the possibility of using muchsmaller capacitances, in addition to obtaining smaller ripple.

B. Control Path

The control path consists of a passive RC differentiator,followed by a few inverters, as shown in Fig. 7. The principalproblem of this stage is that after deriving the input signal toobtain a phase delay of 90, it is necessary to amplify the signalby the inverters to obtain a signal that is capable of managingthe switches. Consequently, noise is also amplified, and simu-lation results have shown that part of this noise is transmittedto the output through the switches. To minimize this effect,


TABLE ICOMPARISON OF PRINCIPAL CHARACTERISTICS

two control paths are employed instead of a fourth inverter,and a capacitance CO is connected at the output (see Fig. 5),working as a first-order low-pass filter and, thus, providing anSNR no less than 60 dB. The necessity for a capacitance atthe output could be considered as a drawback; nevertheless, thetotal silicon area in this circuit is much smaller than needed ina conventional counterpart, and tracking is still much faster, aswe shall see.

IV. SIMULATION RESULTS

To verify the circuit performance, SPECTRE is used tosimulate the proposed circuit using AMS 0.35-µm technology.The proposed envelope detector has been designed with thefollowing component values: CL = 0.6 pF, CC = 0.1 pF, andCO = 1.6 pF; IL = 1 µA, RC = 10 KΩ, and RL = 2 kΩ.Thus, the ripple is around 0.3% when Vin = 300 mV for atotal capacitance CT = 3.2 pF. On the other hand, if we usean equivalent capacitance area at the conventional circuit, i.e.,CL = 3.2 pF, the minimum ripple to be reached is around3%, as depicted in Fig. 8, and if we use the same IL toobtain a similar time constant, then the ripple is ten times thatpercentage. To compare the release time constant, the rippleis fixed at around 1%; consequently, the conventional circuitneeds a huge load capacitance of 10 pF, while the proposedcircuit maintains previous values. A step-type signal at 10 MHzis employed in both circuits, which abruptly descends from apeak of 300 down to 30 mV; results are shown in Fig. 9. Ascan be seen, the proposed circuit is much faster in tracking thesignal than the conventional one, and in addition, it is possibleto configure the desired release time constant by IL withoutchanging the ripple of the envelope. The release time constantsτ , defined as the time required by the signal to respond to 99%of a 20-dB stepwise change, are, in this case, τ = 27.5 µs forthe conventional circuit and τ = 0.4 µs for the proposed circuit.Fig. 10 shows dc and 10-MHz transfer characteristics.

As seen, both envelope detectors are linear for amplitudes ofup to 300 mV. The proposed envelope detector obtains a loweramplitude at a high frequency since there is a gap between thepeak holder input signal and the control path signal, and thehold mode starts just after the signal has reached its maximum.However, this gap can be minimized with careful matching ofthe phase of both signals.

Table I summarizes the principal characteristics of bothenvelope detectors. The proposed envelope detector has 17%

higher power consumption, and its SNR is lower due to thesimple control path employed. However, in return, it obtainsmuch better performance in keeping and tracking at the sametime. This leads to simplifying the circuits that are requiredafter the detector, as well as obtaining a faster circuit. Moreover,the capacitance area needed to obtain the same ripple is, forthis configuration, a third of that needed by the conventionalcircuit. When at the output, we connect a capacitor so thatboth circuits use the same area (CO = 8.4 pF), the SNR of theproposed circuit is 75 dB, and τ (99%) is maintained at 2.1 µs,which is still ten times smaller than that of the conventionalcircuit.

V. CONCLUSION

A new concept for the envelope detector, whose principaladvantage is to overcome the inherent tradeoff between thekeeping and the tracking that are exhibited by conventionalcounterparts, has been proposed. Furthermore, it offers thepossibility of reducing the capacitance needed for the sameperformance, thus achieving a great savings in circuit area. Thiscircuit is especially advantageous when fast-settling envelopedetectors are required or when the dynamic range is increasedin another way, e.g., with companding or adaptive biasingtechniques.

REFERENCES

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[2] C. Guo, C.-W. Lo, Y.-W. Choi, I. Hsu, T. Kan, D. Leung, A. Chan, andH. C. Luong, “A fully integrated 900-MHz CMOS wireless receiver withon-chip RF and IF filters and 79-dB image rejection,” IEEE J. Solid-StateCircuits, vol. 37, no. 8, pp. 1084–1089, Aug. 2002.

[3] V. W. Leung, J. Deng, P. S. Gudem, and L. E. Larson, “Analysis of en-velope signal injection for improvement of RF amplifier intermodulationdistortion,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1888–1894,Sep. 2005.

[4] J. M. Stevenson and E. Sanchez-Sinencio, “An accurate quality factortuning scheme for IF and high-Q continuous-time filters,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1970–1978, Dec. 1998.

[5] Y. P. Tsividis, V. Gopinathan, and L. Toth, “Companding in signal process-ing,” Electron. Lett., vol. 26, no. 17, pp. 1331–1332, Aug. 1990.

[6] F. Behbahani, A. Karimi-Sanjaani, W.-G. Tan, A. Roithmeier, J. C. Leete,K. Hoshino, and A. A. Abidi, “Adaptive analog IF signal processor for awide-band CMOS wireless receiver,” IEEE J. Solid-State Circuits, vol. 36,no. 8, pp. 1205–1217, Aug. 2001.

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[9] M. H. Rashid, Microelectronic Circuits. Boston, MA: PWS, 1999.[10] S. Khucharoensin and V. Kasemsuwan, “A high performance CMOS

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J. P. Alegre received the B.S. degree in physics in2003 from the University of Zaragoza, Zaragoza,Spain, where he is currently working toward thePh.D. degree.

He is a member of the Group of Electronic Design,Department of Electronic and Communications En-gineering, University of Zaragoza. He was with theAragon Institute of Technology in ElectromagneticCompatibility (EMC). His research interests includemixed analog–digital microelectronic circuit design,autotuning circuits, device modeling, and electronicsfor high-frequency communications.

Santiago Celma (S’92–M’92) was born inZaragoza, Spain. He received the B.Sc., M.S., andPh.D. degrees from the University of Zaragoza in1987, 1989, and 1993, respectively, all in physics.

He is currently an Associate Professor with theDepartment of Electronic and Communications En-gineering, University of Zaragoza. He is a coauthorof more than 50 technical papers and 150 interna-tional conference contributions. His research inter-ests include circuit theory, mixed-signal integratedcircuits, wireless sensor networks, and intelligentinstrumentation.

Belén Calvo received the B.Sc. degree in physicsand the Ph.D. degree in electronic engineering fromthe University of Zaragoza, Zaragoza, Spain, in 1999and 2004, respectively.

She is currently an Assistant Professor with and amember of the Group of Electronic Design, Depart-ment of Electronic and Communications Engineer-ing, University of Zaragoza. Her research interestsare related to analog and mixed-mode CMOS ICdesign: low-voltage low-power wideband amplifiersand on-chip programmable circuits.

Jose Maria García del Pozo received the B.S.degree in physics in 2005 from the University ofZaragoza, Zaragoza, Spain, where he is currentlyworking toward the Ph.D. degree.

His research interests include analog and mixed ICdesign and optoelectronics for ultrahigh-frequencycommunications. He is a member of the Group ofElectronic Design in the University of Zaragoza.

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Design of a Novel Envelope Detector for Fast-Settling Circuits