Design of a Low-Power Potentiostatic Second …pserra/cnm/2017 - Design of a Low-Power...Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC for Electrochemical Sensors

Low-power potentiostat 2nd Order CT ADC for ECS

J. Aymerich Gubern PRIME 2017

Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC

for Electrochemical SensorsJoan Aymerich Gubern

[email protected]

Integrated Circuits and Systems (ICAS)Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

June 2017

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Trillion-Sensor Vision

Sensors/year

Year

56%/year

21%/year

222%/year

Electrochemical sensors are growing exponentially due to potential of miniaturization and mass production

2/26

Several organizations created visionsfor continued growth to trillion(s) sensors

Applications in biosensors, quality control, ...

Expected sensor production growth per year

$15 trillion by 2022

www.tsensorssummit.org

Monolithic or hybrid integrationonto CMOS platforms



3/26

1 Amperometric Electrochemical Sensors

Conclusions

2 Potentiostatic Modulator architecture

3

4

5

Proposed architecture

Design methodology and trade-offs



4/26


Conclusions


3

4

5





5/26

Amperometric Electrochemical Sensors

Measurement independent of the R and C impedances.

Three electrodes:

Rct = charge-transfer resistanceCdl = double-layer capacitance

Interaction with microorganismsInteraction with microorganismsSelectivity by functionalization

Reduced speed and life timePotentiostatic and amperometricoperations

Electrochemical time constant:



Classic circuit implementation

A1 establishes the control loop toaccomplish potentiostat operation

&

Requires multiples OpAmps + ADC

A2 converts sensor current to voltage for digitization and readout

Large area and power consumption

Potentiostat

Amperometry

6/26



7/26



Conclusions

3

4

5





Behaviour similar to low-pass first-ordersingle-bit CT A/D modulator

Error current converted into voltage and shaped in frequency by the electrochemical sensor itself

High oversampling ratios (OSR>100)can be easly obtained with kHz-rangeclock frequencies fS

8/26

Potentiostatic

Amperometric read-out through the modulation of output bit stream by chemical input



Behaviour similar to low-pass first-ordersingle-bit CT A/D modulator

Error current converted into voltage and shaped in frequency by the electrochemical sensor itself

High oversampling ratios (OSR>100)can be easly obtained with kHz-rangeclock frequencies fS

Monolithic CMOS integrationInexpensive 2.5 in-house CMOS technology (CNM25)developed by ICAS group at IMB-CNM(CSIC)

9/26

Electrochemical sensor

Potentiostatic

Potentiostatic

Amperometric read-out through the modulation of output bit stream by chemical input



Typical tonal component of 1st orderTypical tonal component of Quantization error and input signal correlation

Potentiostat operation not well-definedPotentiostatic error influenced by the input signal

Electrochemical sensor

10/26

Quantizer

Potentiostatic



11/26

3 Proposed architecture


Conclusions


4

5




Higher resolution: 2nd order noise shaping

Idle tones attenuation

Potentiostatic operation well-defined

New design trade-offs!

Incremental work: Addition of electronic integration

Stability compensation is required

A zero must be added in the loop filter to compensate the phase shift

Proposed amperometric potentiostatic M

Electronic integrator forces

12/26



Stability compensationDistributed FeedBack Topology

Loop Filter Zero frequency location

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High frequency path




fZ depends on sensor time constant

8/15

Frequency [Hz]

Loop

filte

r ga

in [d

B]

Loop Filter (s)

fZ Leading to instability!!

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0.025

0.02

0.015

0.01

0.005

0

-0.005

-0.01

-0.015

-0.02

-0.025 0 -0.2 -0.4 -0.6 -0.8 -1 0.2 0.4 0.6 0.8 1

DC Input [Full Scale]

Potentiostatic voltage strongly influenced by the sensor input signal

8/15

Frequency [Hz]

Loop

filte

r ga

in [d

B]

Distributed feedback1st Order

fZ depends on sensor time constant


fZ Leading to unstability!!

15/26

Loop Filter (s)



Stability compensationFeed-Forward Topology


Variations in the sensor time constant do not compromise the stability of the system!

Loop Gain dB20Loop Gain dB20 0.015

Loop Gain dB20 0.15

Loop Gain dB20 1.5

NameVisC c

104- 3

10- 2

10- 1

100

102

105

103

101

Stabi li ty Response

Frequency [Hz]

Loop

gai

n [d

B]

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High frequency path



Stability compensationFeed-Forward Topology

Variations in the sensor time constant do not compromise the stability of the system!

0.025

0.02

0.015

0.01

0.005

0

-0.005

-0.01

-0.015

-0.02

-0.025 0 -0.2 -0.4 -0.6 -0.8 -1 0.2 0.4 0.6 0.8 1

DC Input [Full Scale]

Distributed feedbackFeedforward1st order

Electronic integrator forces its input to have DC zero component.

Loop Gain dB20Loop Gain dB20 0.015

Loop Gain dB20 0.15

Loop Gain dB20 1.5

NameVisC c

104- 3

10- 2

10- 1

100

102

105

103

101

Stabi li ty Response

Frequency [Hz]

Loop

gai

n [d

B]

17/26

Loop Filter (s)




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4


Conclusions


3

5





Stability condition:

Rea

l axi

s p

oles

loca

tion

/ fs

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-0.4

-0.2

0

0.2

0.4

0.6

(a)(b)

(c)

(a)

(b)(c)

Root locus analysis: Closed-loop poles moves as quantizer gain changes

Small-Signal Stability AnalysisLinear model

Stability region as a function of fZ/fS

19/26

Linear model

Quantizer Gain

DAC



Stability condition:

Linear model

Quantizer Gain

DAC Rea

l axi

s p

oles

loca

tion

/ fs

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-0.4

-0.2

0

0.2

0.4

0.6

(a)(b)

(c)

(a)

(b)(c)



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Less safety stability marginBetter noise shaping

Power Spectrum as function of zero location

Root locus analysis: Closed-loop poles moves as quantizer gain changes

(More 1st order behaviour)



Potentiostat Voltage Ripple

Feedback current DAC (IFS) charges/discharges Cdl

TS is the only degree of freedom to minimize ripple

(Cdl and IFS are fixed by the application)

Voltage ripple may be required to be kept below certain minimum

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SQNR vs input signal

22/26

Top-level simulation



Low-power circuit implementation

Electronic integrator: Gm1-C1

Feed-Forward path

Latch comparator for 1-bit quantization

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Feedback current DACPower consumption mainly determined by current DAC FS,allowing chemical reaction take place

D-type flip-flop for S/H

Flexible and modular to be mapped into differentCMOS technologies



Cyclic Voltammetry

Simulation Results

Performance simulation results

Triangular waveform is applied to the Reference-electrode, while the sensor current is measured simultaneously.VerilogA model

Power consumption mainly determined by current DAC FS

Rest of circuit blocks

Method for studying electrochemical reactions

Ferrocyanide Cyclic Voltammetry

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CMOS technology



25/26

Conclusions5



3

4





Conclusions

High resolution with kHz-range clock frequencies:

26/26

Compact architecture thanks to the electrode-electrolyte interface used as an integrator stage in the structure

Minimalist analog circuits fully integrable in purely digital CMOS technologies

Ultra low-power ( ) operation compared to sensor consumption



Conclusions

High resolution with kHz-range clock frequencies:

26/26

Compact architecture thanks to the electrode-electrolyte interface used as an integrator stage in the structure

Energy storageElectrochemical sensor<1mm2 ASIC: Potentiostat RF antennas

Smart tags for food quality control

Wireless contact lens for health monitoring

Minimalist analog circuits fully integrable in purely digital CMOS technologies

Future work

Ultra low-power ( ) operation compared to sensor consumption



Power Consumption Comparison

1/15ECS Design Trade-offs Circuit Simulation Conclusions



Linear model

Quantizer Gain

DAC

Rea

l axi

s p

oles

loca

tion

/ fs

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-0.4

-0.2

0

0.2

0.4

0.6

(a)(b)

(c)(d)

From stable situation


1/15ECS Design Trade-offs Circuit Simulation Conclusions

Root LocusStability region as a function of KWorst-case scenario when K is maximum

Root Locus

Real Axis (seconds -1 )

Imag

inar

y Ax

is(s

econ

ds-1

)


Sweep input: 0 to FS to find maximumquantizer gain Kmax (worst-case)

Sweep fS/fZ and check if Kmax iswithin the stable region

Stability is ensured if:

Documents

Design of a Low-Power Potentiostatic Second …pserra/cnm/2017 - Design of a Low-Power...Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC for Electrochemical Sensors