Design of a high performance narrowband low noise amplifier …journals.tubitak.gov.tr/elektrik/issues/elk-20-28-1/elk... · TUMMA and NISTALA/Turk J Elec Eng & Comp Sci 0 10 20 30

Turk J Elec Eng & Comp Sci(2020) 28: 45 – 60© TÜBİTAKdoi:10.3906/elk-elk-1903-185

Turkish Journal of Electrical Engineering & Computer Sciences

http :// journa l s . tub i tak .gov . t r/e lektr ik/

Research Article

Design of a high performance narrowband low noise amplifier using an on-chiporthogonal series stacked differential fractal inductor for 5G applications

Sunilkumar TUMMA∗, Bheemarao NISTALADepartment of Electronics and Communication Engineering, National Institute of Technology, Warangal, India

Received: 30.03.2019 • Accepted/Published Online: 31.10.2019 • Final Version: 27.01.2020

Abstract: Inductors play a crucial role in the design of radio frequency integrated circuits (RFICs) and they typicallyconsume a considerably large area and have a low-quality factor at high frequencies. The employment of fractal structurein on-chip inductors helps in improving the quality factor and also reduces the overall area besides improving theinductance value. In this paper, an orthogonal series stacked differential fractal inductor is proposed and the same isused to design a low noise amplifier (LNA) for 5G band (27–30 GHz) applications. The proposed inductor is fabricated ona multilayer printed circuit board and the measurement results demonstrate twice the enhancement in inductance, 56%improvement in quality factor, and 33% reduction in series resistance when compared to the conventional series stackedfractal inductor for the equivalent on-chip area. The LNA using cascode topology with inductive source degeneration isdesigned and simulated at a center frequency of 28 GHz in 90 nm CMOS technology using the tool Advanced DesignSystem. The inductors in the LNA are replaced with the proposed on-chip inductor for different layers, which contributesto high gain, better input matching, and low noise figure compared to the state-of-the-art LNAs.

Key words: Quality factor, noise figure, input matching, gain, inductance, source degeneration

1. IntroductionOn-chip inductors are a significant component of radio frequency integrated circuits (RFICs) with application inoscillators, impedance matching networks, emitter degeneration circuits, filters, and low noise amplifiers (LNAs)[1]. Due to technology scaling, there has been a huge demand for on-chip inductors with small size, high-qualityfactor, and large inductance, making it an emerging field of research. In contrast, conventional planar inductorsrequire a large on-chip area to achieve high inductance values. Fractal geometry-based inductors act as a feasiblesolution to achieve higher inductance due to longer trace lengths [2–4]. The conventional series stacked fractalinductor (CSSFI) improves the inductance and self-resonance frequency (fSR ) and reduces the quality factor(Q) [5–7]. Differential excitation of inductors leads to higher Q compared to single-ended excitation as they areless affected by substrate parasitics [8–10]. An orthogonal series stacked differential fractal inductor (OSSDFI)with a high quality factor and significant improvement in inductance is proposed.

The LNA is an important building block of wireless communication systems [11]. It is used to amplify thereceived signal to acceptable levels with minimum self-generated additional noise [12]. As the development of5G wireless networks continues, the performance of the front end of the radio is an increasingly critical elementin the RF receiver signal path, particularly with respect to the LNA. Millimeter wave (mm-Wave) frequency∗Correspondence: [email protected]

This work is licensed under a Creative Commons Attribution 4.0 International License.45

https://orcid.org/0000-0001-6943-2133

TUMMA and NISTALA/Turk J Elec Eng & Comp Sci

bands for 5G mobile services include a 26-GHz band (24.25â27.5 GHz) and a 28-GHz band [13]. The signallinearity, gain, input/output matching, stability, power consumption, and noise figure are key performancemetrics of the LNA [14, 15]. Several LNA topologies were proposed in the literature and they have theirown merits and demerits. The resistive terminated LNA [16] and common gate LNA [17] have good inputmatching but the noise figure (NF) is exceptionally high. Furthermore, shunt-resistive feedback [18, 19] andcurrent reuse [20, 21] techniques have good performance in terms of NF but they are not stable and have alarge input/output impedance issue. The cascode LNA circuit topology with inductive source degeneration hasbetter input matching, high gain, good stability, and low NF [22–28]. The on-chip inductor implementation ofLNA reduces the spectral noise and provides good input and output matching [29, 30].

In the present work, the LNA is designed for 27–30 GHz frequency range with 28 GHz as the centerfrequency (fo ) in cascode circuit topology with inductive source degeneration. The replacement of inductorswith the proposed OSSDFI improves the performance of the LNA in terms of NF, gain, input matching, andthe required on-chip area. Section 2 describes the construction and testing of the proposed inductor, Section3 explains the design of the LNA, Section 4 deals with the simulation results of the LNA, and finally theconclusions are given in Section 5.

2. Orthogonal series stacked differential fractal inductor

The proposed OSSDFI is implemented in three layers based on 2nd order Hilbert space-filling curves [2] asshown in Figure 1. The 0th, 1st, and 2nd order Hilbert curves are depicted in Figure 2. The phase difference ofthe top layer with intermediate and bottom layers is 90 and 180 , respectively. The layers in the inductor areconnected in a series stack using vias. In contrast with the CSSFI, the current directions in adjacent layers arenot opposite for the proposed OSSDFI, resulting in a reduction in negative mutual inductance and a significantincrease in total inductance.

Figure 1. Proposed orthogonal series stacked differentialfractal inductor.

Figure 2. Order of Hilbert curves.

The quality factor of an inductor is an indication of the amount of energy stored in the inductor and itis represented in (1).

Q =ωLT

Rs

Rp[(ωLT /Rs)

2+ 1

]Rs

[1− R2

s (Cs + Cp)

LT− ω2LT (Cs + Cp)

], (1)

46


where ω is the angular frequency at which stored energy is measured, LT is the total inductance, Rs isthe series resistance, Rp is the substrate parasitic resistance, Cs is the interlayer capacitance, and Cp is thesubstrate parasitic capacitance. The orthogonal arrangement of metal layers in the proposed inductor reducesthe overall parasitic capacitance (Cp ), which in turn improves Q. The self-resonance frequency of an inductoris the point where it ceases to work as an inductor and it is represented in (2).

fSR =1

2π√LTCeq

, (2)

where Ceq is the equivalent parasitic capacitance, which includes Cp and Cs . The fSR of the proposedinductor is reduced as the increase in inductance is greater than the reduction in parasitic capacitance.

2.1. Simulation results of the proposed OSSDFI

The proposed inductor is designed and simulated using Advanced Design System (ADS) in 90 nm CMOStechnology with an outer diameter of 200 µm and the width of the conductor is 10 µm. The on-chip area isdirectly proportional to the outer diameter. The input impedance (Z), quality factor, total inductance, andseries resistance for differential excitation are evaluated using Y-parameter analysis [10] as shown in (3),(4),(5),and (6), respectively. In (3), Y11 denotes the short circuit input admittance and Y22 denotes the short circuitoutput admittance.

Z = 0.5 ∗ ( 1

Y11+

1

Y22), (3)

Q =imag (Z)

re (Z), (4)

LT =imag (Z)

ω, (5)

Rs =1

re(Y12), (6)

where Y12 denotes the short circuit reverse transfer admittance. Figures 3 and 4 show the inductanceand quality factor plots for the series stacked spiral inductor, CSSFI, and OSSDFI. The proposed OSSDFI hashigh inductance and high Q compared to the series stacked spiral inductor and CSSFI. The simulation resultsdemonstrate that the OSSDFI shows twice the rise in inductance and 56% improvement in Q when comparedto the CSSFI. The performance summary of the proposed inductor and its comparison with existing inductorsare given in Table 1. From Table 1, it is observed that the OSSDFI has very low series resistance comparedwith the inductors reported in the literature. The self-resonance frequency of the proposed inductor is 40 GHz,which makes it suitable for 5G applications as service providers use a 24.25–27.5-GHz band and a 28-GHz band.

2.2. Measurement results of the fabricated OSSDFIThe proposed inductor is fabricated on a multilayer printed circuit board (PCB) using FR4 material with adielectric constant of 4.4 and area of 10 ×10 mm2 . The thickness of the copper and the overall thickness of thePCB are 0.035 mm and 1.60 mm with spacing of 0.197 mm between the metal layers. The fabricated inductoris shown in Figure 5 and the experimental setup is shown in Figure 6.

47


0 10 20 30 40 50 60 70

-4

-2

0

2

4

6

Ind

uc

tan

ce

(n

H)

Series stacked spiral inductor CSSFI OSSDFI

Frequency (GHz)

Figure 3. Comparison of inductance.

0 10 20 30 40 50 60 70

0

3

6

9

12

Qu

ali

ty F

acto

r

Frequency (GHz)

Series stacked spiral inductor

CSSFI

OSSDFI

Figure 4. Comparison of Q.

Table 1. Performance comparison of the proposed inductor with existing state of the art.

Parameter [4] [6] [7] [5] OSSDFIInductance (nH) 0.9 2.45 0.5 1.61 3.23Quality factor 8.67 7.25 15 7.63 12.3Outer diameter (µm) 200 200 400 200 200Series resistance (Ω) 250 180 160 150 100

Figure 5. OSSDFI fabricated on a multilayer PCB. Figure 6. Experimentation using a network analyzer.

Due to technology scaling from micrometers to millimeters the frequency of operation is reduced fromGHz to MHz. Therefore, the proposed inductor is simulated in the mm scale and the overall examination ofmeasurement results is done by using a vector network analyzer. The comparison of simulated and measuredinductances is illustrated in Figure 7. It is clear from the plots that the measured inductances are in goodconcurrence with the simulated ones with inductance equal to 225 nH. Similarly, Figure 8 shows the comparison

48


of simulated and measured results of Q with the maximum quality factor approximately equal to 38 at 60 MHz.The pre- and postmeasurement results for the OSSDFI implemented on the multilayer PCB are tabulated inTable 2. From Table 2, it is observed that the measured results are in good agreement with the simulatedresults. Therefore, the proposed inductor is observed to be well suited for utilization as an on-chip inductor inthe CMOS process.

0 40 80 120 160-1000

-500

0

500

1000

Ind

uct

an

ce(n

H)

Frequency (MHz)

Simulated Results

Exper imental Results

Figure 7. Simulated and measured inductance.

0 40 80 120 160

0

10

20

30

40

Qu

ali

ty F

act

or

Frequency (MHz)

Simulated Results

Experimental Results

Figure 8. Simulated and measured Q.

Table 2. Simulated results vs. measured results.

Parameter Simulated results Measured resultsInductance (nH) 230 225Quality factor 38 36Self-resonance frequency (MHz) 125 124

3. Design of the LNA

The cascode LNA with inductive source degeneration is the best topology used to obtain high gain, low NF,and good input/output matching [27] and it is shown in Figure 9. The first stage of the LNA consists ofthe bandpass filter to tune the LNA for the required frequency of operation. The second stage is the cascodestage, where transistor M1 is in common source mode and transistor M2 is in common gate mode. Cascodearchitecture is used to increase forward gain while decreasing the reverse gain besides providing better isolationbetween input and output ports. The source inductor (Ls ) provides negative feedback and stabilizes the gain.The gate inductor (Lg ) provides input matching and the large value of gate inductance reduces the NF [30].The drain inductance (L) is used to control the gain of the LNA. The third stage is the buffer stage, used toprovide better output matching at the output of the LNA [31]. The design specifications for the LNA are givenin Table 3.

49


Figure 9. Cascode LNA with inductive source degeneration.

Table 3. Design specifications of the LNA.

Parameter RangeOperating frequency 27–30 GHzCenter frequency (fo) 28 GHzNoise figure <3 dBGain 33 dBInput matching <10 dBTechnology 90 nmPower supply (VDD) 2.2 VPower dissipation (PD) <10 mW

3.1. Design of the bandpass filterThe constant-k LC bandpass filter is used to tune the LNA for the required frequency of operation and it isshown in Figure 10. The inductances L1 , L2 are obtained by using (7) and (8) and the capacitances C1 , C2

are obtained by using (9) and (10). In this design, upper cut-off frequency (f2 ) is equal to 30 GHz and lowercut-off frequency (f1 ) is equal to 27 GHz, where Z0 is the characteristic impedance.

Figure 10. LC bandpass filter.

L1 =Z0

2π(f2 − f1). (7)

50


L2 = Z0(f2 − f1)

4πf2f1. (8)

C1 =2(f2 − f1)

4πf2f1Z0. (9)

C2 =1

Z0π(f2 − f1). (10)

3.2. Design of Ls , Lg , and Cgs

The input impedance (Zin ) is defined as the ratio of input voltage (Vin ) to input current (Iin ) given in (15).The input impedance of the common source inductive degenerated LNA is computed from the equivalent circuitas shown in Figure 11.

Vin = IinsLg + Iin1

sCgs+ (Iin + gmVgs)sLs, (11)

Vgs =IinsCgs

, (12)

Vin = IinsLg + Iin1

sCgs+ (Iin +

gmIinsCgs

)sLs, (13)

Vin = Iin[s(Lg + Ls] +1

sCgs+

gmLs

Cgs], (14)

where s, Lg , Ls , Cgs , and gm are complex frequency, gate inductance, source inductance, gate to sourcecapacitance, and transconductance, respectively.

Figure 11. Input equivalent circuit of the inductive degeneration architecture.

Zin =Vin

Iin= [s(Lg + Ls] +

1

sCgs+

gmLs

Cgs]. (15)

At resonance (ω=ωo ), Im(Zin) = 0 and Re(Zin) = Rs .

ωo(Lg + Ls) =1

ωoCgs=⇒ ωo =

1√(Lg + Ls)Cgs

=⇒ ω2o(Lg + Ls)Cgs = 1. (16)

51


Rs =gmLs

Cgs. (17)

Rs = ωTLs. (18)

ωT =gmCgs

. (19)

For better input matching choose the smallest possible value of Ls and compute unity gain angularfrequency (ωT ) using (18). Consider gm=5 mA/V and substitute in (19) to obtain Cgs . The gate inductanceLg is obtained by substituting center frequency fo , Cgs , and Ls in (16).

3.3. Gain of the LNAThe gain of the LNA is defined as the ratio of output voltage (Vout ) to input voltage (Vin ) and it is given in(20). It is computed from Figure 11 as follows:

Vout

Vin=

−GmsL

1− ω2Cgs(Lg + Ls) + s.Ls.Gm. (20)

Gm =ioutVin

. (21)

Substituting (16) in (20), the simplified gain is equal to

Gain =Vout

Vin=

−L

Ls. (22)

Gain(dB) = 20 log(Vout

Vin). (23)

The gain of the LNA is the ratio of load inductor (L) at the drain to the source inductor (Ls ). To obtainhigh gain the value of L chosen is large but it depends upon the maximum inductance allowed by the technology.For 90 nm the maximum inductance is obtained as 10 nH. In order to obtain 33 dB gain compute the L valueusing (23).

3.4. Calculation of the noise figure

The noise factor is defined as the ratio of signal to noise ratio at the input of the network (S/N)in divided bythe signal to noise ratio at the output of the network (S/N)out as shown in (24). Noise factor expressed indecibels is called noise figure and is computed as

F =(S/N)in(S/N)out

. (24)

NF (dB) = 10 log(F ). (25)

52


The noise figure of the common source inductive source degeneration [15] at center frequency (fo ) isgiven as

NF = 1 +γ

Rsgmω2o(RsCgs + gmLs)

2. (26)

Substitute (16) and (17) in (26) to get the simplified expression for NF:

NF = 1 + γ4(gmLs)

2

Rsgm

1

Cgs(Lg + Ls), (27)

NF = 1 +4γLs

Ls + Lg, (28)

where γ is known as the bias dependent coefficient of channel thermal noise and it varies between 2 and3 [15]. The noise figure is dependent on Ls and Lg . The selection of small Ls and large Lg leads to low NF.

3.5. Stability

Stability is one of the important factors in the design of RF amplifiers. It is obvious that an LNA may becomean oscillator if it is unstable in circuit performance. After circuit design, its stability is examined using theStern stability factor [14] based characterization given as

K =1− |S11|2 − |S22|2 − |∆|2

2 |S12| |S21|, (29)

∆ = |S11| |S22| − |S12| |S21| , (30)

where S11 , S12 , S21 , and S22 are known as S-parameters of the two-port network. S11 is the reflectioncoefficient at the input port, S12 is the reverse isolation, S21 is the forward voltage gain, and S22 is the reflectioncoefficient at the output port.

If K > 1 and | ∆ | < 1, then the amplifier is considered to be stable. In recent years, K and ∆ havebeen replaced by the µ factor, which is defined by (31). For an LNA to be stable µ should be greater than 1in the desired frequency of operation.

µ =1− |S11|2

|S22 −∆conj(S11)|+ |S12 ∗ S21|. (31)

3.6. Calculation of the optimal width of the transistors

The optimal width (Wopt ) is also known as the maximum allowable width for each transistor in the circuit [14].It is obtained by using (32), where Cox is the gate capacitance per unit area [F/m2 ] and Lmin is the minimumchannel length, which is equal to 90 nm; ωo (2π fo ) is the angular frequency at center frequency (fo ).

Wopt =1

3ωoLminCoxRs, (32)

53


Cox =ϵoxtox

=Koxϵotox

, (33)

where ϵox=permittivity of gate oxide Sio2 [F/m], Kox=relative permittivity of gate oxide Sio2=3.9,ϵo=permittivity of vacuum (8.85*10−12 )[F/m], tox=thickness of gate oxide=3.45*10−11 [m]. Find Cox using(33) and substitute in (32) to find Wopt .

3.7. Calculation of power dissipation

The effective voltage applied to MOSFET is computed from (34). The gate to source voltage Vgs is varied from0.5 V to 1 V and the threshold voltage (Vth ) is varied from 0.2 V to 0.3 V [32].

Veff = Vgs − Vth. (34)

The bias current ID is calculated by substituting Veff and gm in (35),

ID = 0.5 ∗ gm ∗ Veff . (35)

The power dissipation (PD ) is calculated as (36),

PD = VDDID. (36)

The width of the transistor (M1 ) is chosen as 45 µm, nearly equal to optimal width. The minimal lengthof every transistor is 90 nm. The width of the transistor (M2 ) should be less than the width of the transistor(M1 ) to reduce the parasitic capacitance. However, it has a lower limit to reduce the noise contribution of thedevice [31]. The width of the transistor M2 is chosen as 30µm. The load inductor L and load resistance RL

are used to control the gain. The buffer stage (M3 and M4 ) is used to drive 50 Ω load. When both transistorsM3 and M4 are in saturation the computed widths are 40 µm and 15 µm, respectively [14]. W1 , W2 , W3 ,and W4 are widths of the transistors M1 , M2 , M3 , and M4 , respectively. The values of the components forthe LNA designed at a center frequency of 28 GHz are given in Table 4.

Table 4. Designed component values of the LNA operating at center frequency.

Component ValueL1, L2, C1, C2 2.65 nH, 14.74 pH, 11.79 fF, 2.12 pFLs, Lg, L 0.1 nH, 3.13 nH, 4.46 nHWopt 50 µmLmin 0.09 µmW1, W2, W3, W4 45 µm, 30 µm, 40 µm, 15 µmVbias (input transistor) 816.5 mVVbias(cascode transistor),Vbias(buffer stage) 1.1 V, 545.23 mVCox, Cgs 8.42 mF/m2, 10 fFVDD 2.2 VR 60 Ω

54


4. Simulation results of the LNA using the OSSDFI

The LNA executed using the designed components and proposed OSSDFI is shown in Figure 12. The inductorsLg , Ls , and L are simulated in layout level as shown in Figures 13, 14, and 15, respectively, and the same isextracted to circuit level simulation. The inductor Ls has lower inductance; hence it is implemented using asingle layer differential fractal inductor with an on-chip area of 25 µm × 25 µm. The inductors Lg and L

shown in Figure 9 are replaced by a three-layer and a four-layer OSSDFI, respectively, with an on-chip area of100 µm × 100 µm. The simulated inductance plot for the proposed OSSDFI for the different layers is shownin Figure 16. The simulated inductance values for Ls , Lg , and L are 0.12 H, 3.2 nH, and 4.98 nH, respectively.

S-PARAMETERS

Mu

L

Term

Term

LsBSIM1_Model

Mu

S_Param

V_DC

MOSFET_NMOS

MOSFET_NMOS

R

V_DC

V_DC

C

C

L

L

T_NMOS

ET_NMOS

I__37

Term2

Term1

I__34MOSFETM1

Mu1

SP1

SRC4

MOSFET3

MOSFET4

Rl

SRC6

SRC5

C2

C1

L2

L1

ET1

Z=50 Ohm

Num=2

Z=50 OhmNum=1

AllParams=Imelt=

Imax=

N=

Rg=Ffe=

Af=

Kf=

Gdsnoi=1Nlev=

Xpart=

Cgbo=

Cgdo=

Pbsw=

Pb=Mjsw=

Cjsw=

Mj=

Cj=Tox=

Wnd=

Lnd=

Nd=Wnb=

Lnb=

Nb=

Wn0=

N0=

Wx3ms=Lx3ms=

X3ms=

Wx2ms=

Lx2ms=X2ms=

Wmus=

Lmus=

Mus=Wx3u1=

Lx3u1=

X3u1=

Wx2u1=

X2u1=

Wx2u0=Lx2u0=

X2u0=

Wx3e=

Lx3e=X3e=

Wx2e=

Lx2e=

X2e=Wx2mz=

Lx2mz=

X2mz=

Wu1=

U1=

Wu0=Lu0=

U0=

Weta=

Leta=Eta=

Wk2=

Lk2=

K2=Wk1=

Lk1=

K1=

Wphi=

Phi=

Wv"=Lv"=

V"=

Vdd=

Dw=Dl=

Muz=

Trise=

Temp=Js=

Rsh=

PMOS=no

NMOS=yes

Mu1=mu(S)

SortNoise=Sort by name

CalcNoise=yes

Step=1.0 MHzStop=30 GHz

Start=25 GHz

Vdc=545.23 mV

Width=28.23 umLength=0.09 um

Model=MOSFETM1

Width=57.95 um

Length=0.09 um

Model=MOSFETM1

R=60 Ohm

Vdc=2.2 V

Vdc=816.5 mV

C=2.12 p

C=11.79 fF

R=0 Ohm

L=14.74 pH

R=0 OhmL=2.65 nH

50.31 um0.09 um

MOSFETM1

=80.16 um

=0.09 um

=MOSFETM1

Figure 12. Inductive source degeneration LNA using the proposed OSSDFI.

Figure 13. Single layer (Ls ). Figure 14. Three layer (Lg ).

55


Figure 15. Four layer (L).

0 10 20 30 40 50

-8

-4

0

4

8

12

Ind

uct

an

ce(n

H)

F requency (GHz)

Single layer differential fractal inductor

Three layer OSSDFI

Four layer OSSDFI

Figure 16. Simulated inductances for the multilayer OSS-DFI.

Comparison of the designed and simulated inductances for different layers with an on-chip area is givenTable 5.

The proposed OSSDFI achieves high inductance for the given on-chip area as the orthogonal arrangementof fractal metal layers reduces the negative mutual inductance. In order to accomplish similar inductance valuesas illustrated in Table 5 the series stacked spiral inductor and CSSFI require large on-chip area. Consequently,the effective on-chip area to implement an LNA using the proposed OSSDFI is much less.

Table 5. Comparison of designed and simulated inductances.

Inductance Designed Simulated No.of On-chipinductance inductance metal layers area

Gate inducatnce (Lg) 0.1 nH 0.12 nH 1 25 µm × 25 µmSource inducatnce (Ls) 3.13 nH 3.2 nH 3 100 µm × 100 µmLoad inducatnce (L) 4.46 nH 4.98 nH 4 100 µm × 100 µm

The multilayer implementation reduces the series resistance of the inductor [30]. The proposed OSSDFIhas very low series resistance as shown in Table 2. Therefore, it has good input matching (S11 ) of –10.438 dBat 28.46 GHz as shown in Figure 17. The gate inductor (Lg ) is far higher compared to source inductance (Ls );hence it has a very low noise figure of 0.724 dB at 28.54 GHz as shown in Figure 18. The designed gain of theLNA is 33 dB, which is the ratio of load inductance to gate inductance. The simulated gain (S21 ) is 30.66 dB at28.51 GHz as shown in Figure 19. The 3-dB bandwidth is equal to 2.3 GHz as shown in Figure 19. The stabilityfactor plot is shown in Figure 20 and the LNA is stable in the entire frequency range from 27 to 30 GHz as µ isgreater than 1. The LNA has 5 mW power dissipation from the supply voltage of 2.2 V as the gm is small. Thecomparison of the LNA with the existing state-of-the-art LNAs [22–28, 30, 31, 34–37] is presented in Table 6.The proposed LNA has high gain, low power dissipation, low noise figure, and good input matching comparedto the LNAs reported in the literature. The fractional bandwidth is defined as the ratio of bandwidth to the

56


center frequency. If the fractional bandwidth is less than 20% , the range of frequencies is known as narrowband[33]. The fractional bandwidth of the proposed LNA is 8%; hence it acts as a narrowband LNA.

Figure 17. Input matching. Figure 18. Noise figure.

Figure 19. Gain. Figure 20. Stability factor.

5. ConclusionA novel OSSDFI is designed that demonstrates improvements in inductance, quality factor, and series resistanceof 200%, 56%, and 33%, respectively, over the CSSFI. The proposed OSSDFI is fabricated on a multilayer PCBand the measurement results are in good concurrence with the simulated results, demonstrating the robustnessof the design. Therefore, the proposed inductor is found to be suitable for use as an on-chip inductor in theCMOS process. The LNA is designed for 27–30 GHz using the proposed OSSDFI and the circuit simulationswere done using ADS in 90 nm CMOS technology. At 28 GHz, the LNA achieves a high gain of 30.668 dB, low

57


Table 6. Performance summary and comparison of the proposed LNA with state-of-the-art LNAs.

Ref. S11

Ê[dB]S21

[dB]NF[dB]

Operatingfreq. [GHz]

PD

[mW]SupplyVoltage

CMOSTech.

Topology

[22] –18 12.4 4.4–6.5 0.4–10 12 1.8 V 180 nm WB, CG+CS[23] –9 12.5 3–7 2.6–10.2 7.2 1.2 V 90 nm WB, current reuse+

cascode[26] –9 11.9 3.6 26–42 40.8 2.4 V 90 nm WB, cascode[27] –18 14.8 3.8 29–44 18 1.2 V 90 nm WB, cascode[28] –10 21 4.67 30–50 20.4 1.2 V 90 nm WB, cascode[31] –10 11 2.6 3–10 15.4 1.8 V 180 nm WB, cascode[30] –18 11 2.6 15 15 1.3 V 130 nm NB, cascode[24] –20 13.1 3.9 24 14 1 V 180 nm NB, cascode[25] –11 12.86 5.6 24–26 30 1.8 V 180 nm NB, cascode[34] –21 15 6 24 30 1.5 V 180 nm NB, CGRF[35] –18 12.5 5.4 60 4.4 1 V 90 nm NB, transformer

feedback[36] –26 21 7.6 52–56 15.1 1.5 V 130 nm NB, gate-inductive

gain-peaking[37] –16 15.69 2.8 9.75–10.25 8.44 1.8 V 180 nm NB, cascodeThis work –10.438 30.668 0.724 27–30 5 2.2 V 90 nm NB, cascode

WB: Wideband, NB: Narrowband, CG: Common gate, CS: Common source, CGRF: Common gate with resistive feedthrough

noise figure of 0.724 dB, and good input matching of –10.438 dB. The LNA has power dissipation of 5 mW froma 2.2-V power supply and it has 3-dB bandwidth equal to 2.3 GHz. These results show that the LNA realizedusing the proposed OSSDFI is appropriate for 5G communication standards.

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