Design Methodologies (throughput and clock frequency) Power … · 2010-10-06 · Compilation Hand CodingHand Coding Architectural Design Synthesis Standard Proc. ... – Power Consumption

Digital IC Design

Design Methodologies

Viktor ÖwallViktor ÖwallDept. of Electrical and Infomation Technology

Lund UniversityLund University

Parts of this material was adapted from the instructor material to Jan M. Rabaey, Digital Integrated Circuits: A

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

material to Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall International Editions

Digital IC Design

Design Trade-offs• Speed (throughput and clock frequency)

• Power Consumption• Power Consumption

• Areaand

• Design time (time to market)Design time (time to market)

• Price

Do not design for maximum performance,design for required performance!


design for required performance!

Digital IC Design

Design GapDesign GapP t ti l D i C l it d D i P d ti it

1 000 000

10,000,000Potential Design Complexity and Designer Productivity

K)

1,000,000

100,000

C l it th ter C

hip

(K

1,000

10,000 Complexity growth rate58%/year

sist

ors

pe

Design Gap

10

100 Productivity growth rate21%/year

ogic

Tra

ns

981

991

989

987

985

983

001

999

997

995

993

009

007

005

003

1

0

Lo (Source: sematech97)


19 1919191919 2019191919 20202020

Digital IC Design

System Design to HardwareS t D i

ArrhythmiaClass.

Combine

Oth

Threshold

System Design• MATLAB• SystemC• CatapultCOther

sensors

Compilation Hand Coding

CatapultC

Compilation Hand CodingArchitectural

Design Synthesisg

Standard Proc.ASIC


Digital IC Design

System Design to HardwareS t D i

ArrhythmiaClass.

Combine

Oth

Threshold

System Design• MATLAB• SystemC• CatapultCOther

sensorsCatapultC

Design GAP!

Standard Proc.ASIC


Digital IC Design

“Early”DesignDesign Methodology ?Evolution


Next, i.e. now: Design Reuse, IP Reuse, Platform based design etc

Digital IC Design

Design Analysis, Specification and V ifi tiVerification

• Accounts for Largest fraction of Design timeAccounts for Largest fraction of Design time (or at least should)

• More effective on higher levels of abstraction

• Most design failures due to error in spec.


Digital IC Design

Design gMethodologyThree abstractions:Three abstractions:Behavioral, structuraland geometrical


and geometrical

Digital IC Design

Design Methodology, contnd.

Moving betwen the domainsAmount of AutomatizationAmount of Automatizationincrease


Digital IC Design

“Standard” Design Flow of T d


Today

Digital IC Design

Standard Processors vs. Special Purpose

Algorithm

SpecialPurpose

Standard Processor Processor Cores

D i S ifiDomain SpecificProcessors

etc.• Programmable• Low Design cost

• Flexible Architecture• High Calculation Capacity

L PLow Design cost• Standard Interface• Good supply of tools

• Low Power• User defined Interface• Variable Wordlength


• Low Price at Volume

Digital IC Design

Software or Hardware?• Flexibility• Performance Requirements• Performance Requirements

– Power ConsumptionTh h t– Throughput

• Cost– Volume– Know how– Time to Market


Digital IC Design

E Effi iEnergy EfficiencyEnergy efficiency(MIPS/mW)(MIPS/mW)

100 ?

10

4 orders of

0 1

1 4 orders ofmagnitude

0.01

0.1

Pentium StrongARM TI-DSP Dedicated

High Low


Flexibility FlexibilityAcknowledgement: Bob Brodersen

Digital IC Design

E /A ffi iEnergy/Area efficiency10000

Energy Efficiency (MOPS/mW) Area Efficiency (MOPS/mm2)

1000

10000

ies

10

100

ea E

ffici

enci

1

10

rgy

and

Are

MicroprocessorsD di t d

0.1

Ene

pDedicatedDesignsGeneral

Purpose DSP’s

0.011 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Chip Number (see Table II)


Courtesy: Professor Bob Brodersen, UC Berkeley

Digital IC Design

Results in fully parallel solutionsResults in fully parallel solutionsReducing supply voltage saves energy: E = CV2

Energy Area

64-point FFTE

16-State Viterbi Decoder

64-point FFTT f d

16-State Viterbi DecoderEnergy per

Transform (nJ) Decoder

Energy per Decoded bit (nJ)

Transforms per second per unit area

(Trans/ms/mm2)

DecoderDecode rate per unit

area (kb/s/mm2)

Direct-Mapped Hardware 1.78 0.022 2,200 200,000

FPGA 683 5.5 1.8 100

Low-Power DSP 436 19.6 4.3 50

High-Performance DSP 1700 108 10 150

(numbers taken from vendor-published benchmarks)Orders of magnitude lower efficiency

even for an optimized processor architecture

1000

5000


even for an optimized processor architectureCourtesy Ning Zhang, Berkeley Wireless Research Center (BWRC)

Digital IC Design

To reach efficient solutions

algorithm/hardware codesign

is crucial!


Digital IC Design

This is an Advertisement

DSP Design

6 credits6 credits

P i d 2 F llPeriod 2, Fall


Digital IC Design

ScopeHow to get from a signal processing algorithm to an EFFICIENT

implementation using

– Different numbering systems– Pipelining

P ll li– Parallelism– Strength reduction, i.e. complexity of operations.– etc, etc,...

in a structured way!

Case studies: FFT, image filtering, acoustic echo cancellation, pacemakers,...


p ,

Digital IC DesignFrom Algorithm to Implementation

( )FIR-filter

g pMany paths! How do we get there?

Time-multiplexedD D Dx(n)

h0 h3h2h1 cMUX

architecture

y(n)in Signal Processing book REG

D x(2k-1)x(2k)x(2k+1)

DD

b0

x(2k-2)

y(2k)

b1 b2

y(2k)

y(2k+1)

b0 b1 b2


Parallel architecture

Digital IC DesignFrom Algorithm to Implementation

( )FIR-filter

g pMany paths! How do we get there?

Time-multiplexedD D Dx(n)

h0 h3h2h1 cMUX

architecture

y(n)in Signal Processing book processorREG

D x(2k-1)x(2k)x(2k+1)

DD

b0

x(2k-2)

y(2k)

b1 b2

y(2k)

y(2k+1)

b0 b1 b2 ”ASIC”


Parallel architecture FPGA

Digital IC Design

Architectural DesignArchitectural Design

Allocation - determine architectural resourcesAssignment - binding operations to hardwareAssignment binding operations to hardwareScheduling - determine execution order

plus transformations

pipelining, software pipelining, loop unrolling, etc...and

parallelism, hierarchy, etc...


Digital IC Design

Problems in DSP Design (contd)

Supplying the MIPS is not the biggest problem but how to getproblem but how to get

the correct data, to the correct processing elementto the correct processing element,

at the right time

at

Low Power


Low Power

Digital IC Design

Implementation TechniquesImplementation Techniques

SpecialSpecialPurpose

FPGA ASICFPGAGate Array

ASIC

Field ProgrammableGate Arrays

R fi bl

yApplication/AlgorithmSpecific Integrated Circuit

• Reconfigurable• Fast Turn Around• Prototyping

• High Calculation Capacity• High Utilization• Low Power


• Low Price at Volume

Digital IC Design

VirtexVirtexBANK 0 BANK 1Block RAM

NK

7

NK

2

IOB

BAN

BAN IOB

CLBCLB

BAN

K 6

BAN

K 3

Routing

BANK 5 BANK 4Timing

Routing


g

Digital IC Design

Example: Xilinx FPGAsExample: Xilinx FPGAs

CLB CLBCLB CLB

Horizontal

Switchingmatrix

HorizontalRoutingChannel

Interconnectpoint Configurable Logic Block

CLBCLBpoint Configurable Logic Block

R

Combinational logic Storage elements

VerticalRoutingChannel

R

Q 1D

CE

F

GF

D in

F

A

B/Q 1 /Q 2

C/Q 1 /Q 2

D

A

Any function of up to 4 variables

R

Q 2D

CE

F

GG

Clock

GB/Q 1 /Q 2

C/Q 1 /Q 2

D

E

Any function of up to 4 variables


CE

Digital IC Design

Basic Spartan Architecture –Low End FPGALow End FPGA


Digital IC DesignXilinx Virtex-II Pro –Xilinx Virtex-II Pro –

Heterogeneous Programmable PlatformsFPGA Fabric

Embedded PowerPcEmbedded memories

Hardwired multipliersHardwired multipliers

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.seCourtesy XilinxHigh-speed I/O

Digital IC DesignEmbedded System IP blocksEmbedded System IP blocks

PowerPC™ Processor 400+ MHz clock rate

High-speed Serial Transceivers

622 Mbps to 10 Gbps

MGT MGT

LVDS Technology

MGT MGT

VCCIO

High Performance RAMEmbeddedMult-Acc Logic Cells

18 Bit

18 Bit36 Bit

Z

VCCIO

Z

Z

ImpedanceControl


* Pricing for 100,000 units in 2004* Pricing for 100,000 units in 2004

Mult Acc Logic Cells

Courtesy: Ivo Bolsens, CTO Xilinx

Digital IC Design


Digital IC Design


Digital IC Design


Digital IC Design

Th C t/V l CThe Cost/Volume Crossover1000

100

e Cos

t

10

100

ASIC Cost

Relat

ive 10FPGA Cost

1

0.1

10 100 1,000 10,000 100,000 1,000K

Unit Volume

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.seCourtesy: Ivo Bolsens, CTO Xilinx

Digital IC DesignGate Arrays – “the old way”Gate Arrays – the old way

Fabricating with an array of n- and p-transistors and using design specific metalizationand using design-specific metalization in routing channels.

Before metalization After metalization


Before metalization

Digital IC DesignSea-of-GateSea-of-Gate

Fabricating with an array of n- and p-transistors d i d i ifi t li tiand using design-specific metalization

on top of primitive cells.Turn of gates to achieve

Oxide-isolationTurn of gates to achieveGate-isolation


Digital IC Design

Gate Array

RandomLogicg

Memorysectionsection

Gate ArrayLSI Logic


(LEA300K)

Digital IC DesignThe return of gate arrays?The return of gate arrays?

Structured ASICs.“Structured ASICs are based on a predefined logic fabric — in essence, an array of prebuilt logic cells

Via programmable gate array

Structured ASICs are based on a predefined logic fabric in essence, an array of prebuilt logic cells and an arrangement of configurable memory blocks. This array can be fabricated up through the first few metal layers, as if it were a standard product, almost as a cross between an FPGA and a gate array. Then the base wafers can be warehoused, waiting for an order.” Ron Wilson of EE Times,

Via programmable gate array(VPGA)

Via-programmable cross-point

metal-5metal-6

programmable via


programmable via

[Pileggi02]Exploits regularity of interconnect

Digital IC Design

Design Strategies for ASIC/DSPDesign Strategies for ASIC/DSP

ASIC

F ll C tS th i Full CustomSynthesisSemi Custom

Behavioral orStructural Synthesis

Design for Performance• Flexible• Highest Calculation Capy

• Fast Design Process• Simplified re-design

• Highest Calculation Cap.• Lowest Power• Smallest area

Highest Design Cost


• Highest Design Cost

Digital IC Design

Cell based design

• Macrocell (PLAs memories etc )• Macrocell (PLAs, memories, etc…)

• Standard Cell• Standard Cell

• Datapath compilationDatapath compilation

• Compiled Cellp


Digital IC Design

Macros: Memories, mults,...

RAMRAM

Part of Mult


Digital IC Design

Standard Cell Design

• Provided Cell library (including macros?)

• Layout is generated

– cells of equal height placed in rows

automatic placement strategies– automatic placement strategies

– routing strategies depends on interconnect layers


Digital IC Design

Example of Standard Cell LayoutLogic cellVdd & GND

RoutingChannel

Cel

ls

FeedthroughDepends on n mberw

s of

C

Depends on numberof metal layersFunctional

Module(RAM, ROM,

Mult )

Row

Mult, ...)


Digital IC Design

CDatapath Compilation Approach

• Provided Cell library (including macros?)

• Bit-sliced approachBit sliced approach

– hierarchical design

– structure is kept to minimize interconnect

– abutment or routing in rows

– routing strategies depends onrouting strategies depends on interconnect layers and placement


Digital IC Design

D t th C il ti A h t dDatapath Compilation Approach, contnd.

MUXMUX MUX

REG1Routing orAbuttment

REG1 REG2

REG2

REG3

ADD

REG3 REG3


Digital IC Design

C ll b d d i St d d C ll DiCell based design, Standard Cell Die

1k FFT (S. He)

More metal layers, synthesis Image convolution processor (V Öwall) Cell-structure hidden underinterconnect layers

Image convolution processor (V. Öwall)Few metal layers, bit-sliced datapaths structure clearly seen


Part of Complex Mult (A. Berkeman)

Digital IC Design

Abutment vs RoutingAbutment vs. Routing

Abutment RoutingAbutment Routing

“N I t t” Routing between cells“No Interconnect”Exact fit between cells

Routing between cells

A lDenser designLarge cell library

Area lossSmaller cell library


Large cell library

Digital IC Design

Floorplanning

Macrocell

Interconnect BusFloorplan: Interconnect BusFloorplan:Defines overalltopology of design,relative placement of

Routing Channel

relative placement ofmodules, and global routes of busses,supplies, and clockspp ,


Digital IC Design

E ampleExample

MemoriesAbutmentAbutment

Bit slicedData Paths


Digital IC Design

Layout EditorsPolygon PushingPolygon Pushing

TILT (LTH)Magic (Berkeley)


Digital IC Design

What is dominant today?at s do a t today


Digital IC DesignVHDL Based DesignVHDL Based Design

A state machine into VHDLlibrary IEEE;use IEEE STD LOGIC 1164 all;library IEEE;use IEEE.STD_LOGIC_1164.all;entity state_machine is

generic (m : integer := 2) -- Used to process bus width port (clk : in STD_LOGIC;

reset : in STD_LOGIC;

combinatorial : process (input,output,state,next_state) -- Combinatorial partbegin

next_state <= state;next_output <= output; case (state) is -- Current state and input dependent

when st0 => if (input = ’1’) theninput : in STD_LOGIC_VECTOR(m-1 downto 0);output : out STD_LOGIC_VECTOR(m-1 downto 0);

end state_machine;architecture implementation of state_machine is

type state_type is (st0, st1,st2, st3); -- defines the states;

when st0 => if (input = 1 ) then next_state <= st1;next_output <= ”01”

end if;when st1 => if (input = ’0’) then

next_state <= st2;t t t ”11”signal state, next_state : state_type;

signal output, next_output STD_LOGIC_VECTOR (m-1 downto 0);

begin sequential : process (clk)

next_output <= ”11”end if;

when st2 => if (input = ’1’) then next_state <= st3;next_output <= ”10”

en if;sequential : process (clk)begin

if clk’event and clk = ’1’ thenif reset = ’1’ then

state <= st0;t t ”00”

;when st3 => if (input = ’1’) then

next_state <= st0;next_output <= ”00”

end if;when others => next_state <= next_state; -- Default

next output <= ”00”;output <= ”00”;else

state <= next_state;output <= next_output; -- registered outputs

end if;

next_output <= 00 ;end case;

end process;

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.seHugo Hedberg, Matthias Kamuf, Dept. of Electroscience, Lund University, {hhg,mkf}@es.lth.se

end if;end process;

end architecture;

Digital IC Design

Th th i d t ASIC FPGAThen synthesized to ASIC or FPGA


Digital IC Design

D i Fl i lifi d iDesign Flow: a simplified viewHDL (VHDL/Verilog/...)( g )

Simulation

Cell library Synthesis

P&R

Configuration Post-layout sim.

Fabrication


Digital IC Design

Compiled Cell approachCompiled Cell approachNo predefined Cell library but cells are compiledNo predefined Cell library but cells are compiled according to requirements

Compiled layoutSchematic


Compiled layout

Digital IC Design

Stick Diagram to Layout

DiemensionlesDiemensionles

Layout is generatedLayout is generated


Digital IC Design

H t t f Al ith t Sili ?How to get from Algorithm to Silicon?• Complete Specification/SimulationComplete Specification/Simulation• Quantization

– wordlenghtsg– “simple” coefficients

• Architecture (Implementation technique?)– PartitioningPartitioning– Dataflow– Hardware mapped or microcoded– Memory requirementsy q

• Cell library, clocking, ...• Netlist• Layout

What can/should be automated?Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

What can/should be automated?

Digital IC Design

Design Analysis and Simulation

• Circuit simulation (Spice )• Circuit simulation (Spice,…)

• Switch Level simulation (IRSIM )• Switch-Level simulation (IRSIM,…)

Gate level/Functional simulation (St t l VHDL)• Gate-level/Functional simulation (Structural VHDL)

More in Advanced Digital IC DesingViktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

More in Advanced Digital IC Desing.

Digital IC Design

Circ it Sim lation (Spice)Circuit Simulation (Spice)VDDDD

IN OUT

• Non-linear elements• Non-linear elements• Continuous waveform• Solving Differential Equations


• Solving Differential Equations

Digital IC Design

Switch-level Simulation (IRSIM)VV

V0 1 0Vdd

VM

t1 t2 t


Digital IC Design

Ti i V ifi tiTiming Verification- static timing analysis -

Critical Path

• A simulation is the result of the applied signal pattern and does not guarantee the critical path.

• A timing verifier traverses the network and ranks paths which is a very complex task.


Digital IC Design

The “Design Closure” Problem

Iterative Removal of Timing Violations (white lines)


Courtesy Synopsys

Documents

Design Methodologies (throughput and clock frequency) Power … · 2010-10-06 · Compilation Hand CodingHand Coding Architectural Design Synthesis Standard Proc. ... – Power Consumption