Design approaches for VCSELs and VCSEL-based smart · PDF fileservices digital network ~B-ISDN!. ... optical communication systems. ... rays are reviewed, and the maximum pixel number

Design approaches for VCSEL’sand VCSEL-based smart pixels towardparallel optoelectronic processing systems

Takashi Kurokawa, Shinji Matso, Tatsushi Nakahara, Kota Tateno, Yoshitaka Ohiso,Atsushi Wakatsuki, and Hiroyuki Tsuda

The technical issues involved in applying vertical-cavity surface-emitting lasers ~VCSEL’s! to paralleloptical interconnection systems are discussed from the viewpoint of their application to asynchronoustransfer mode switching and parallel computer systems. We also discuss approaches to designing aVCSEL array structure for high-speed modulation and the effect of pixel-performance homogeneity on thetransmission bandwidth and power consumption. We review monolithic and hybrid integration tech-nologies for VCSEL-based smart-pixel arrays, and we estimate the maximum pixel number and input–output throughput allowed in a chip, considering the power consumption and pixel homogeneity. Weshow that a one-chip optoelectronic parallel processing system comprising more than 1000 processorelements is possible when smart-pixel arrays are fabricated under the 0.25-mm complementary metal-oxide semiconductor design rule. © 1998 Optical Society of America

OCIS codes: 140.3460, 200.4650, 220.4880.

1. Introduction

Progress in Si-based technologies has remarkably im-proved the performance of computer systems. Clus-ters of high-performance workstations are oftenconnected to public optical communication networks.In the near future these workstations will be intercon-nected to one another by parallel optical fiber linkswith multigigabit per second data rates. This will bethe first generation of optically interconnected com-puter systems. Furthermore, board-to-board andchip-to-chip optical interconnections by use of vertical-cavity surface-emitting lasers ~VCSEL’s! and smartpixels will permit the realization of highly integratedoptoelectronic parallel processing systems in whicheach processor element will be connected by means ofhigh-density and broadband interconnections.

On the other hand, innovative photonic technologiessuch as ultralow-loss optical fibers, high-performancesemiconductor lasers, and optical amplifiers have con-

The authors are with NTT Optoelectronics Laboratories, NipponTelegraph and Telephone Corporation, 3-1, Morinosato-Wakamiya,Atsugi, Kanagawa 243-01 Japan.

Received 7 April 1997; revised manuscript received 25 August1997.

0003-6935y98y020194-11$10.00y0© 1998 Optical Society of America

194 APPLIED OPTICS y Vol. 37, No. 2 y 10 January 1998

tributed to the installation of the broadband integratedservices digital network ~B-ISDN!. Future B-ISDNservices to every household will require very high-capacity asynchronous transfer mode ~ATM! switchingsystems with terabit throughput, incorporating high-speed-switching large-scale integrated circuits ~LSI’s!.Such systems will inevitably incorporate optical tech-nology to overcome the bottleneck at interboard andintraboard interconnection levels that arise from thelimitations of electric wiring. As a result the innova-tion of optical interconnection technologies will lead tothe fusion of telecommunications, computer, andbroadcasting services, providing innovative megame-dia services.

Time-division multiplexing ~recently wavelength-division multiplexing has become popular! has gener-ally been used to increase the total throughput inoptical communication systems. However, spatiallyparallel optical interconnection technologies will bemore effective over short distances ~i.e., less than a fewhundred meters!. This is because data transmissionin a parallel format makes system integration simple,reducing the latency of multiplexing–demultiplexing~mux–demux! functions and thus resulting in lowerpower consumption and lower cost. VCSEL’s arevery important for constructing parallel optical inter-connection systems because they can emit a number ofbroadband optical signals simultaneously. In addi-

tion to their one- or two-dimensional structures, theyhave advantages such as a low cost potential, low op-erating current, and surface-normal emission. Thesurface-normal structure makes it easy to introduce anoptical input–output ~IyO! into a LSI, which is ex-tremely important for constructing high-density opti-cal interconnection systems.1

In this paper the three types of parallel opticalinterconnection systems—parallel optical fiber links,free-space optical interconnects, and opticalwaveguide circuits—are reviewed from the viewpointof their application to ATM-switching and parallelcomputer systems, and the technical issues involvedin applying VCSEL’s to these optical interconnectsare discussed. We also discuss approaches to de-signing a VCSEL array structure for high-speed mod-ulation and the effect of pixel-performancehomogeneity on the transmission bandwidth andpower consumption. Monolithic and hybrid integra-tion technologies for VCSEL-based smart-pixel ar-rays are reviewed, and the maximum pixel numberand IyO throughput allowed on a chip are estimatedby consideration of the power consumption and pixelhomogeneity. We show that a one-chip optoelec-tronic parallel processing system comprising morethan 1000 processor elements is possible when smart-pixel arrays with homogeneous characteristics arefabricated under the 0.25-mm complementary metal-oxide semiconductor ~CMOS! design rule.

2. Parallel Optical Interconnections for Switching andComputer Systems

B-ISDN’s based on ATM protocols will handle high-speed digital communication services not only forpublic telecommunication networks but also for pri-vate customer networks. ATM-switching systemswith throughputs of 10 and 40 Gbitsys are currentlyavailable,2 having been achieved in fabrics that in-corporate multichip packaging technologies. Futurefiber-optic access networks providing 155-Mbitys ser-vices to every household ~fiber-to-the-home services!will surely require ATM-switching systems withterabit-class throughput and above. The keys to de-veloping such high-capacity systems are advances inVLSI and optical interconnection technologies.3ATM-switching LSI chips with 10-Gbitys serial IyOhave already been demonstrated.4 As the capacityof board-mountable switching chips increases, wefirst meet a bottleneck in the interconnections.5Terabit ATM-switching systems are developed by theexploitation of optical interboard and intraboard con-nections, as shown in Fig. 1.

It is clear that advanced computer systems will alsohave bottlenecks at the interconnection level; however,the criteria for introducing optical interconnections arenot always simple. In clusters of high-performanceworkstations dispersed within distances of a few hun-dred meters, the workstations will be interconnectedby parallel optical fiber links with multigigabit persecond data rates.6 This will be the first generation ofoptically interconnected computer systems.

When we extend optical interconnections into ge-

neric parallel processing systems in which a set ofboard-mountable processor nodes are connected overa high-performance interconnection network, someproblems, however, will arise. These are related tohandshake protocols, the bandwidth of the commu-nication buffer, and the protocol-processing over-head.7 The latency of the interface bottleneck inparallel processing architectures will manifest itselfas a new bottleneck in hardware–software handshak-ing because of the increased throughput of opticalinterconnections. This means we have to developnovel interface architectures, matching the broad-band optical implementation. This is a quite differ-ent set of conditions from the case of opticallyinterconnected ATM-switching systems.

One way to achieve optical connection-intensivecomputing systems is through massively parallel pro-cessing, in which many processor elements with op-tical IyO ports are integrated onto one chip.Compact high-performance processor elements couldbe optically interconnected by means of smart pixelsand could efficiently handle the inherent two-dimensional data format, as shown in Fig. 2.

3. Hardware Architecture of Optical Interconnections

Parallel optical interconnections have the advantageof simple system integration with a reduction of the

Fig. 1. Optical interconnection scheme in ATM-switching sys-tems.

Fig. 2. Optical interconnection scheme in parallel computer sys-tems.

10 January 1998 y Vol. 37, No. 2 y APPLIED OPTICS 195

Table 1. Characteristics of Typical Parallel Fiber Link Systems

System LD ArrayOpticalFibera Throughput

Transmission LengthConsumed Power

OptoelectronicsTechnology VCSEL GI-MMF 16 Gbitsys 100 mConsortium8 32 pixels ~500 Mbitsys 3 32 channels! 400 mWychannel

~850 nm!Parallel

Optical Link VCSEL GI-MMF 6.2 Gbitsys 300 mOrganization 10 pixels ~622 Mbitsys 3 10 channels! 150 mWychannelConsortium6 ~980 nm!

Motorola9 VCSEL SI-MMF 1.5 Gbitsys 30 m10 pixels ~150 Mbitsys 3 10 channels! 100 mWychannel~850 nm!

Hitachi10 Edge-emitting SMF 3 Gbitsys 100 m12 pixels ~250 Mbitsys 3 12 channels! 200 mWychannel

~1300 nm!

aGI-MMF, graded-index multimode fiber; SI-MMF, step-index multimode fiber; SMF, single-mode fiber.

latency of the mux–demux functions. This lowerspower consumption and cost. There are three types ofoptical implementations: parallel optical fiber links,free-space optical interconnects, and waveguide cir-cuits. Here we discuss the technical issues in theseimplementations from the viewpoint of unit-to-unit,board-to-board, and chip-to-chip interconnections inATM-switching systems and parallel computer systemapplications, reviewing several reported systems.

A. Parallel Optical Fiber Links

Synchronous optical data from a laser diode ~LD!array are transmitted through a fiber ribbon overdistances of less than a few hundred meters. Thisoffers large total throughput and small and simpletransmitter and receiver circuit schemes that con-sume little power compared with that used by theserial optical links employed in conventional localarea network systems. The expected applicationsare the unit-to-unit and the board-to-board intercon-nects for both switching and computer systems. Thetechnical concerns are reducing the total skew andreducing the threshold current of a LD array to in-crease bandwidth and transmission distance. Thetotal skew is mainly due to the variations of light-propagation time in fibers and lasing delay time ofLD’s among channels. The lasing delay timestrongly depends on the threshold current, and it isdifficult to control the bias current of each pixel indi-vidually in the array, so the variation of the thresholdcurrent across the array is required to be small.

Table 1 shows the some examples of the parallelfiber link systems developed so far. Most systemsemploy short-wavelength ~0.8–1.0-mm! VCSEL ar-rays.6,8,9 A testbed in which parallel links are usedhas actually been demonstrated for the transmissionof high-resolution images between workstations.On the other hand, some optical links in which edge-emitting LD arrays are used have been successfullydeveloped.10 Advantages of edge-emitting LD ar-rays are long-emission wavelengths ~1.3 and 1.5 mm!that match the wavelengths of optical communication


networks and reliability assurance. These are im-portant for applications to communications equip-ment.

B. Free-Space Optical Interconnects

High-density optical signals from two-dimensionalVCSEL or smart-pixel arrays are distributed intoseveral ports over distances shorter than 1 m. Free-space optics are free from the topological limitationsof one-dimensional wiring only from the boundary ofthe boards. That is, boards can be densely intercon-nected to one another across the free space. Suchfree-space implementation permits high-densitybroadband interconnections between boards onwhich switching LSI chips are mounted. In parallelcomputer systems, however, free-space interconnec-tions among boards on which processors are mountedmust have reconfigurable or dynamic switching func-tions.

One concern with free-space optics is packaging.Another is how to provide reconfigurable functionsfor parallel processing systems. Optical switchingnetworks that use self-electro-optic devices ~SEED!or exciton absorption–reflection switch ~EARS! de-vices are typical examples of free-space fabrics thatare compactly packaged and that possess dynamicswitching functions.11,12 However, they lack theversatility required for general implementation.Printed circuit boards ~PCB’s! are generally remov-able, so it is difficult to maintain good connectionalignment between them. One way to maintain reg-istration is through the use of active alignment, asshown in Fig. 3, and a few optomechanical feedbacksystems have been proposed.13,14 Another way tomaintain alignment is to design a rigid backplanesystem.

The first optical backplane was demonstrated in aparallel processing system called COSINE, in whichthe transmitter and receiver modules are mechani-cally installed each on 36 boards.15 An optical busarchitecture that uses a backplane-integrating

graded-index lens system has also been proposed.16

This transparent backplane has been extended to cre-ate the Hyperplane backplane architecture in whichoptical data are regenerated by smart pixels on eachboard.17,18 In all cases smart pixels incorporatingVCSEL’s and photodetectors ~PD’s! are the mostpromising devices for implementing free-space opti-cal interconnections.

C. Optical Waveguide Circuits

High-bandwidth optical signals are interconnectedthrough the waveguide circuits on a board. It isdifficult to connect electrically several arbitral pointsat data rates of 600 Mbitsys on a PCB. The conceptof optical PCB’s was first proposed during the earlywork on organic optical waveguides.19 Later, paral-lel processing systems with optical ring busses wereproposed in which the processor chips with LED’swere interconnected with polyimide waveguides.20

Fig. 3. Schematic of free-space optical interconnections betweenboards.

VCSEL’s are appropriate for waveguide intercon-nects because their surface-normal operationmatches that of the PD’s. Such devices are good forplanar packaging technology because the verticalalignment problems associated with waveguide de-vices are eliminated, as shown in Fig. 4.

Silica and organic materials are promising candi-dates for the waveguide circuits. Multimodewaveguides are preferred for interconnects that useVCSEL’s because most available VCSEL’s are multi-mode and a large alignment tolerance is required forcoupling waveguides with VCSEL’s and PD’s. Poly-mer waveguides are good for fabricating large multi-mode circuits. Several multigigabit per secondswitching LSI’s mounted on the board could be inter-connected by means of waveguide circuits withVCSEL’s and PD’s mounted on LSI chips. Therewould be, however, a lot of intersections in the opticalcircuits interconnecting switching LSI’s, as shown inFig. 1. So the loss produced at these intersectionsshould be considered, although the transmission lossof waveguides is quite small ~less than 0.1 dBycm!.When 64 3 64 banyan networks are constructed bythe installation of 16 switching LSI’s with eight inputand eight output ports on the optical circuit board,the maximum number of intersections for onewaveguide is 49. The estimated intersecting loss ofmultimode waveguides is approximately 0.2 dB forone intersection,21 so the maximum intersection lossfor a waveguide would be 10 dB, which could be al-lowed for error-free interconnections of 2.5-Gbitysdata rates. This would mean that switching net-works with a total throughput of 160 Gbitsys could beachieved on a board. For increasing switching ca-pacity low-loss waveguide intersection structuresshould be investigated.

Fig. 4. Schematic of optical waveguide circuit interconnections between LSI chips on which VCSEL’s and PD’s are mounted.


4. Design of Vertical-Cavity Surface-Emitting LaserArrays for Optical Interconnect Applications

From the viewpoint of optical interconnect applica-tions VCSEL’s have several advantages22: ~1! Thestructure can be integrated in two-dimensional ar-rays that enable high-density optical interconnects;~2! low threshold currents enable high-density ar-rays; ~3! surface-normal emission, nearly identical tothe PD geometry, eases the integration with LSIchips and waveguides; ~4! good optical coupling withoptical fibers results in simpler packaging; ~5! there isa low-cost potential because the devices are com-pleted and tested at the wafer level; and ~6! they havea lower temperature sensitivity compared with thatof edge-emitting LD’s.23

That leaves us with the following question:Which of the above features will be appropriate foreach application to parallel fiber links, free-space op-tics, and waveguide circuits? Low cost, low operat-ing current, and temperature insensitivity are muchdesired for all implementations because parallel op-tical interconnections should have a simple systemconfiguration with low power consumption and notemperature control.

For VCSEL’s to be competitive in the area of par-allel fiber link applications the above features mustbe complemented by a high efficiency, long lifetime,and long-wavelength emission ~1.3–1.5 mm!, becauseedge-emitting LD arrays already have good charac-teristics.24 For the application to free-space andwaveguide circuits, the advantages of VCSEL’s arerather clear from the points of view of the two-dimensional array configuration and ease of integra-tion with electronic circuits. Next we discussseveral important technical issues in designingVCSEL arrays for optical interconnections.

A. Vertical-Cavity Surface-Emitting Laser Array Design:Wavelength and Structure

Only 0.8–1.0-mm-wavelength VCSEL’s are foresee-able for practical use for optical interconnects in thenear future. VCSEL’s at 850 nm can be used withmore sensitive Si- or GaAs-based receivers, whereas980-nm VCSEL’s can achieve a somewhat higher per-formance because of their strained-quantum-wellstructure and bottom-emitting capability, which en-ables flip-chip bonding. However, 850-nm VCSEL’sseem to be a better choice because PD compatibility isimportant, especially when VCSEL’s and PD’s areintegrated, as in smart pixels. A surprising reduc-tion of threshold current has been achieved recentlyby use of oxide-confinement technology,25,26 althoughthe reliability has not yet been proved. However,this does suggest the possibility of extremely largepixel numbers on a single chip by the provision ofgood optical and electrical confinement.

VCSEL arrays permit much higher pixel densities,especially in free-space optics in which two-dimensional arrays can be usefully applied. Flip-chip bonding is an effective technology for reducingthe capacitance as a result of metallization tracks


and for integrating the arrays with electronic cir-cuits. Flip-chip-bonded 850-nm VCSEL arrays havebeen developed by use of transparent AlGaAssubstrates, which enable bottom emission.27 AnAl0.1Ga0.9As substrate has more than 95% transpar-ency at 850 nm. An 8 3 8 VCSEL array has showna threshold current of 2.1 mA, a maximum outputpower of 4.2 mW at 25 °C, and a maximum temper-ature of 130 °C for cw operation. The 8 3 8 arraywas mounted in a facedown configuration on an alu-minium nitride ~AlN! substrate, as shown in Fig. 5~a!,and the utility of flip-chip bonding for high-speedmodulation was demonstrated. The small-signalmodulation response of a center pixel in the array isshown in Fig. 5~b!. The conventional top-emittingVCSEL array had a high capacitance ~the highestvalue is 9 pF for the center pixel! because of large-area metallization tracks on the GaAs chip. So the

Fig. 5. Flip-chip-bonded 8 3 8 VCSEL array on an AlGaAs sub-strate: ~a! Flip-chip-bonded structure of VCSEL arrays. ~b!Comparison of small-signal modulation response of a center pixelin the array. The solid curve indicates a flip-chip-bonded arraywith a bottom-emitting structure operated at 2.6 times the thresh-old current. The dotted curve indicates a wire-bonded array witha top-emitting structure operated at 3 times the threshold current.AR, antireflection.

modulation bandwidth was only 250 MHz at 3 timesthe threshold current density because of acapacitance–resistance constant. On the otherhand, for the flip-chip-bonded bottom-emittingVCSEL array, the capacitance of all pixels was re-duced to less than 0.5 pF. The 3-dB down-modulation bandwidth was therefore improved tomore than 2.6 GHz at only 4.2 mA. Such bottom-emitting 850-nm VCSEL arrays are very attractivefor hybrid integration with driver circuits.

The hybrid integration of VCSEL’s and CMOS isanother way to get high-speed modulation. Thistechnology is described in Section 5 because it is alsoapplicable to smart pixels.

Long-wavelength ~1.3–1.5-mm! lasers based on InPsystems have many advantages, such as good reli-ability, the possibility of a buried structure, andwavelength matching with optical communicationsystems, even though many technological difficultiesremain. The 39 °C cw operation of 1.55-mmVCSEL’s fabricated by wafer-fusion technology hasrecently been demonstrated,28 which indicates thepotential of long-wavelength VCSEL’s.29

B. Requirements for Pixel Uniformity in an Array

Figure 6 shows the variation of VCSEL’s thresholdcurrents and PD sensitivities across an 8 3 8 array.The GaAs p-i-n–PD array has a quite uniform photo-sensitivity, and the threshold current of all pixels inthe VCSEL array is distributed within 615% of theaverage. It is important to consider the effect of pixel-performance homogeneity across the array because itis difficult to control both the bias current of eachVCSEL and the discrimination level of each compara-tor individually in parallel interconnection systems.The common bias current and discrimination levelmust be supplied to all pixels. Therefore the varia-tion of both threshold current and differential effi-ciency of pixels in an array will increase the skewamong channels and lower the signal-to-noise ratio.

For the low-bias-current mode ~the bias current Ibis set lower than the average threshold current Ith inan array!, the maximum bandwidth is not limited bythe signal-to-noise ratio but is generally limited bythe variation of the lasing delay time when the com-mon peak current is kept constant. The lasing delaytime td is given by

td 5 tn lnIp 2 Ib

Ip 2 Ith, (1)

where tn is the electron lifetime and Ip is the commonpeak current to the VCSEL’s. If the threshold cur-rent value of all VCSEL’s in an array are in the rangeof ~1 6 x!Ith, the maximum delay time in the array isgiven by

tdmax 5 tn ln

Ip 2 ~0.9 2 x!Ith

Ip 2 ~1 1 x!Ith, ~0 # x , 0.9!, (2)

as the common bias current is

Ib 5 Ith 2 ~x 1 0.1!Ith, (3)

where the margin difference between the bias currentand the minimum threshold current in the array isset at one-tenth the average threshold current. Theskew caused by the lasing delay time should be lessthan 5% of a 1-bit pulse width, and the allowed max-imum transmission bandwidth B is given by

B 5 ~20tdmax!21. (4)

For the high-bias-current mode ~the bias current Ibis set higher than the average threshold current Ith!,on the other hand, the lowering of the extinction ratioof the modulated laser signal limits the bandwidth.The extinction ratio is determined by the variation ofthe threshold current and differential efficiency h of

Fig. 6. Histogram of ~a! the threshold current of 64 elementsacross a VCSEL array on an AlGaAs substrate and ~b! the photo-sensitivity of 64 elements across a GaAs p-i-n–PD array withoutantireflection ~AR! coating. The diameters are 16 mm for theVCSEL and 50 mm for the p-i-n–PD array.


VCSEL’s in the array. The thermal noise s of thePD, including that of the amplifier following it, isproportional to the bandwidth, i.e.,

s 5 ~80kTeCPD!1y2B, (5)

where the response time determined by the PD ca-pacitance CPD and load resistance also should be lessthan 5% of a 1-bit pulse width. Therefore the al-lowed maximum bandwidth B is given by

B 5ahhPD

Q~80kTeCPD!1y2 @~0.45 2 x!~Ip 2 Ith! 2 ~x 1 1!

3 ~x 1 0.1!Ith 2 2xIth#, (6)

where a is the optical coupling efficiency between aVCSEL and a PD, hPD is the photosensitivity of thePD’s, and Q is the error probability coefficient. It isassumed that the discrimination level has the non-decision width with one-tenth its level height andthat the differential efficiency h varies the same asthe threshold current ~Dhyh 5 DIthyIth 5 x!.

The calculated bandwidths for both high- and low-bias-current modes versus variations of threshold cur-rent and differential efficiency are shown in Fig. 7, inwhich the horizontal axis indicates the variation value@represented as x in Eq. ~6!# of the threshold current,Ip 5 5 mA, and the differential efficiency, Ith 5 1 mA.In low-bias-current mode operation the highest band-width is 1 Gbitys for no variation of the thresholdcurrent, and it abruptly decreases with the incrementof the variation. In high-bias-current mode operationthe maximum bandwidth strongly depends on thetransmission loss between a VCSEL and a PD. Notethat high-bias mode operation achieves a quite higherbandwidth than the low-bias one when the variation issmall, although the power consumption become larger.Because the peak current should be set at a small

Fig. 7. Calculated maximum bandwidth dependence on varia-tions of the threshold current and the differential efficiency forhigh- and low-bias-current mode operations. In both modes, Ith 51 mA and Ip 5 5 mA. In the low-bias mode operation, tn isassumed to be 2 ns. In the high-bias mode operation, the requiredbit-error rate is assumed to be less than 10212. The assumedparameters are a 5 0.03, h 5 0.4, hPD 5 0.4, CPD 5 0.5 pF, Te 51500 K, Q 5 7.


value to suppress total power consumption, loweringthe threshold current and its variation as well as in-creasing the differential efficiency will be importantissues. If other parameters such as optical couplingand the photosensitivity of PD’s, have variations in thearray, such variations will make the results worse.

5. Issues of Smart Pixels for Interboard and IntraboardInterconnections

The integration of electronic circuits and surface-normal photonic devices has great potential for use ininterboard and intraboard interconnections. In ap-proaches to smart pixels there seem to be two choicesfor the photonic device, i.e., a multiple-quantum-well~MQW! modulator30 or an active emitter. So far theformer has more intelligent functions and has beendemonstrated successfully in digital multistageswitching networks. However, recent progress withVCSEL’s makes it possible to realize active emitter-based smart pixels. VCSEL smart pixels will sim-plify the optical implementation of interconnectionsystems because of the absence of bias light and theirlarge wavelength tolerance.

A. Monolithic and Hybrid Integration Technologies forVertical-Cavity Surface-Emitting Laser-Based Smart Pixels

There are two kinds of VCSEL-based smart pixels:One has a monolithic and the other a hybrid integratedstructure. Monolithic smart pixels that integrateVCSEL’s, PD’s, and metal-semiconductor field-effecttransistors ~MESFET’s! on a semi-insulating GaAssubstrate have been developed31 ~Fig. 8!. TheMESFET’s and metal–semiconductor–metal ~MSM!PD layers are deposited by molecular beam epitaxy.The highly doped InGaP etch-stop layer, the GaAsbuffer layer, and the VCSEL layers are deposited bymetal-organic chemical-vapor deposition. A selec-tive etching technique is used to fabricate theVCSEL’s and ensure a smooth surface for fabricationof the MESFET’s and the MSM PD.

There are three MESFET’s with a gate length of1 mm, a 20 mm 3 20 mm MSM PD, and a VCSEL witha 15-mm diameter in a 250 mm 3 250 mm pixel. Thethree MESFET’s perform thresholding and amplifierfunctions. In this device both NOR and OR types ofoperation can be performed with the same circuit byswitching the polarity of the voltages applied to theresistor and the PD. The device has a high 3-dBbandwidth of 220 MHz with a 300-mW input power.Such GaAs-based monolithic smart pixels may be re-quired for optical interconnections between switchingLSI chips because it is vital to maximize the opera-tion speed for ATM-switching systems.4

The tremendous progress in VLSI technology willenable an enormous computational bandwidth,which creates an increasing demand for a high-bandwidth optical IyO to a VLSI circuit.32 Severalhybrid integrations of VCSEL’s on Si have been dem-onstrated by means of technologies such as flip-chipbonding, epitaxial lift-off,33 and a thinned and drilledCMOS wafer.34 However, both VCSEL’s and PD’sshould be integrated on Si circuits with good align-

ment in a wafer-scale fabrication process, which isbeneficial in terms of yield and cost.

A novel hybrid integration technology that usespolyimide bonding has recently been proposed.35,36

The structure of the proposed hybrid smart pixel isshown in Fig. 9. The epitaxial layer for the VCSEL’s

Fig. 8. Structure of a monolithic VCSEL-based smart pixel: ~a!Schematic cross section of the device. ~b! Scanning electron mi-croscope image of the device. MSM, metal–semiconductor–metal;DBR, distributed Bragg reflector.

and the PD’s on a GaAs substrate is bonded to a Sicircuit with a polyimide. After the GaAs substrate isremoved by means of wet etching, only the epitaxiallayer remains on the polyimide layer. The VCSEL’sand the PD’s are then fabricated in a wafer-scale fab-rication process in which the photolithography for fab-ricating the photonic devices employs marks on the Sisubstrate. This eliminates the need for alignment inthe wafer-bonding process. The photonic devices andthe Si circuit are electrically connected by three-dimensional contacts with electroplated Au. Both theMSM PD and the VCSEL arrays were fabricated on aSi substrate with this technology. The MSM photo-detectors have a photorespositivity of 0.3 AyW. In theVCSEL array the threshold current is 3.1 mA and themaximum output power is 2.5 mW for a 15-mm-diameter mesa. These results show that hybrid inte-gration by means of polyimide bonding is suitable forfabricating VCSEL-based smart pixels.

Hybrid VCSEL-based smart pixels with a Si CMOSare strongly expected to be used to optically connectprocessor elements in parallel computer systems.Actually, it would be very difficult to install a thou-sand electric pins with a few hundred megabit-per-second data rate on a LSI chip. Microprocessorswith optical IyO ports will be interconnected at theinterboard or intraboard level. If the microproces-sor can be designed compactly to fit within a smallpixel, massively parallel processing systems could beachieved on the board.

B. Power Consumption Limit of a Vertical-CavitySurface-Emitting Laser-Based Smart-Pixel Array

We should discuss how many pixels would be possibleto fit on a chip and how much IyO throughput couldbe achieved, considering the power consumption.Let us consider a one-chip optoelectronic parallel pro-cessing system consisting of a smart-pixel array inwhich each pixel has a processor element and anoptical IyO port. In such systems the processor ele-ment should have a simple structure to make it com-

Fig. 9. Structure of a hybrid VCSEL-based smart pixel with polyimide bonding.


pact, and a general-purpose processor element wasactually implemented by use of 337 gates.37

Suppose smart-pixel arrays in which each pixel hasa compact processor element with a 150-MHz clockfrequency and consisting of 200 gates and an opticalIyO port with a 300-Mbitys transmission bandwidth.The power consumption of one pixel PSP is given by

PSP 5 PCMOS 1 PIyO, (7)

where PCMOS is the power consumption of the Si-CMOS circuit and PIyO is the optical IyO power con-sumption. The power consumption of the CMOScircuit in a pixel is given by

PCMOS 5 gNf, (8)

where N is the gate number of one pixel, f is the clockfrequency, and g is the proportional constant. Theterm g depends on the loading capacitance per onegate and the supply voltage. If the smart-pixel ar-ray were fabricated under the 0.25-mm design rule,CMOS and g would be set at 6 3 10213 ~WyHz!ygatefor the supply voltage of 2.2 V, and the power con-sumption of the CMOS circuit would be approxi-mately 18 mW in one pixel.

The IyO power consumption, on the other hand, isthe sum of the power consumed by the transceiverand the receiver, and the VCSEL driving voltageshould be under 2.2 V. The transceiver power con-sumption PTX is almost equal to the VCSEL powerconsumption in the low-bias mode and can be ex-pressed by

PTX <12

IpV. (9)

When the variation of the VCSEL threshold current~5x! becomes large, the VCSEL driving peak currentIp must be increased to keep the transmission band-width constant. According to Eqs. ~2! and ~4!, it canbe represented as

Ip 5@~x 1 1! 2 ~0.9 2 x!exp~21y20Btn!#Ith

@1 2 exp~21y20Btn!#. (10)

Figure 10~a! shows the CMOS and IyO power con-sumption dependence on the variation of the VCSELthreshold current when the receiver power consump-tion is assumed to be almost constant, at 5 mW.38

The IyO power consumption is half of that of theCMOS for no variation of the threshold current, andit becomes almost equal to the CMOS power con-sumption when the variation becomes 30%. Thenumber of pixels on a chip is limited by the totalpower dissipation of the chip. Figure 10~b! showsthe maximum pixel number dependence on varia-tions of the VCSEL threshold current, assuming amaximum power dissipation of 30 W from a chip. Aone-chip parallel processing system with more than1000 processor elements would be possible even if thevariation of the VCSEL threshold current is approx-


imately 10%. The total IyO throughput would beapproximately 600 Gbitsys at maximum.

Finally, the two types of smart pixels, i.e., thosebased on the MQW modulator39 and those based onthe VCSEL, should be compared briefly with regardto switching time and power consumption.40 Gener-ally speaking, VCSEL-based smart pixels will makethe optical implementation of interconnection sys-tems easy because of the absence of bias light andtheir large wavelength tolerance. With regard todevice design flexibility, the modulator type is advan-tageous because the switching time can be reduced ifa large amount of electric power is supplied, whereasthere are lower limits for both the switching time andthe electric power consumption in the VCSEL type.Both types have the potential for a total throughputof more than 1 Tbit s21 cm22 assuming 10-Wycm2

cooling. As the operating current and voltage arereduced, VCSEL-based smart pixels become muchmore attractive.

6. Conclusion

In the development of advanced information systemssuch as parallel processing computers and ATM-switching systems, the speed and capacity of board-mountable processors and switches will increase

Fig. 10. Dependence on variations of the threshold current: ~a!CMOS and IyO consumption power. ~b! Maximum number ofprocessor elements. Low-bias mode operation with Ith 5 1 mA,power-supplied voltage of 2.2 V, receiver power consumption of 5mW, and a power dissipation limit of 30 W are assumed.

considerably through advances in VLSI technology.Parallel optical interconnections will make possiblebroadband and high-density wiring in such systemsbecause they can reduce the latency of mux–demuxfunctions, resulting in low power consumption andlow cost. VCSEL’s are the key devices for construct-ing parallel optical interconnection systems becausethey have a two-dimensional array configuration andlow operation current, and they can easily be inte-grated with electronic circuits.

The technical issues involved in applying VCSEL’sto three types of optical interconnects ~parallel opticalfiber links, free-space optical interconnects, andwaveguide circuits! have been discussed. For paral-lel fiber link applications VCSEL’s will need a higherefficiency, longer lifetime, and a long-wavelength-emission ability ~1.3–1.5 mm! to be competitive, be-cause edge-emitting LD arrays already have goodcharacteristics. The advantages of VCSEL’s arerather clear for the application to free-space andwaveguide circuits from the viewpoints of the two-dimensional array configuration and ease of integra-tion with electronic circuits and waveguides.

It is important that VCSEL’s have a structure inwhich the PD’s can be integrated on the same sub-strate and flip-chip bonding technology can be ap-plied. High-speed modulation was demonstrated inthe 850-nm VCSEL array on an AlGaAs substrate,satisfying both conditions. VCSEL arrays also re-quire good homogeneity because the common biascurrent and the discrimination level must be suppliedto all pixels. The effect on the transmission band-width of the variation of pixel performance in thearray was estimated. High-bias-mode operationachieves quite a higher bandwidth than does the low-bias one when the variation is small. If the peakcurrent is set at a small value to suppress total powerconsumption, lowering the threshold current and itsvariation as well as increasing the deferrential effi-ciency will be important issues.

Smart pixels, especially VCSEL’s integrated withLSI chips, will be key devices for the construction ofsuch optical free-space and waveguide circuit sys-tems. VCSEL-based smart pixels will make the op-tical implementation of interconnection systems easybecause of the absence of bias light and their largewavelength tolerance. Monolithic and hybrid inte-gration technology for VCSEL-based smart-pixel ar-rays have been reviewed, and the maximum pixelnumber and IyO throughput allowed on a chip areestimated by consideration of the power consumptionand pixel homogeneity. A one-chip optoelectronicparallel processing system consisting of more than1000 processor elements is possible when the smart-pixel arrays are fabricated under the 0.25-mm CMOSdesign rule. The total IyO throughput would be ap-proximately 600 Gbitsys at maximum. Such an op-toelectronic parallel processing system will showgreat ability if a connection-intensive parallel com-puter architecture is reconstructed to make it freefrom the latency of interface bottlenecks that are dueto high-speed optical interconnections.

The authors thank T. Ikegami, T. Izawa, K. Hashi-moto, and H. Iwamura for their encouragement.The authors also thank their many colleagues at NTTLaboratories who have contributed to the develop-ment of surface-normal photonic devices and opticalswitching systems for their valuable discussions andtechnical support.

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