“Design and Simulation Strategies for Fractional-N

“Design and SimulationStrategies for Fractional-NFrequency Synthesizers”

by

Vıctor Rodolfo Gonzalez Dıaz

Thesis submitted as a partial fulfillment of therequirements for the degree of

DOCTOR IN ELECTRONICS

at the

National Institute for Astrophysics, Opticsand Electronics

August 2009Tonantzintla, Puebla

Supervised by:

Dr. Guillermo Espinosa Flores VerdadDr. Miguel Angel Garcıa Andrade

c©INAOE 2009All rights reserved to INAOE

Design and Simulation Strategies for Fractional-N

Frequency Synthesizers

Vıctor Rodolfo Gonzalez Dıaz

19th August 2009

3

Dedico este trabajo

A mi familia.

Mis padres:

Eloisa Dıaz Gonzalez

y

Vıctor Rodolfo Gonzalez Analco

Mis hermanos:

Oscar,

Elo,

y

Edith

A mi esposa Marıa Magdalena

4

Agradecimientos

A Dios.

A mis asesores: al Dr. Guillermo Espinosa Flores-Verdad y al Dr. Miguel

Angel Garcıa Andrade por su gran soporte y sobre todo por la confianza

que me tuvieron en todo momento. Por sus consejos y su amistad.

A los doctores: Dr. Roman Salinas Cruz, Dr. Jose Alejandro Dıaz

Mendez, Dr. Alejandro Dıaz Sanchez, Dr. Victor Champac Vilela y Dr.

Jose Mariano Jimenez Fuentes por ser parte de mi jurado de examen pro-

fesional y por sus valiosos comentarios. Al profesor Franco Maloberti de

la Universida de Pavia Italia, por los valiosos comentarios para mejorar el

trabajo de investigacion.

A todos los investigadores de la coordinacion de electronica que siempre

me motivaron; muy especialmente al Dr. Jose Alejandro Dıaz Mendez.

Tambien de manera especial, a los doctores: Dr. Monico Linares Aranda

y Dr. Reydezel Torres Torres por darnos las facilidades para hacer algunas

mediciones en el laboratorio. Un sincero agradecimiento a la Lic. Claudia

Juarez Corona por su gran ayuda en la instalacion y uso de los kits de

diseno.

A todos mis companeros de doctorado con los que he convivido todo

este tiempo. Especialmente a Gregorio, Emanuel, Marco, Edgar, Jorge,

Nestor, Salvador, Oscar y Uriel.

5

6

Al Instituto Nacional de Astrofısica, Optica y Electronica (INAOE), por

brindarme la oportunidad de continuar preparandome. Al Dr. Roberto

Murphy por todo el soporte que nos ha brindado cuando mas lo hemos

necesitado. Tambien agradezco la ayuda del Dr. Arturo Sarmiento que

con su labor en la coordinacion de electronica ayudo a la realizacion de

este trabajo. A todo el personal tecnico, administrativo y de operacion

del instituto, por su labor indispensable en nuestro trabajo.

A mis compatriotas mexicanos que mediante el Consejo Nacional de Cien-

cia y Tecnologıa (CONACyT), brindaron el apoyo economico para la re-

alizacion de este trabajo, a traves de la Beca para Estudios de Doctorado

con numero de registro 181644.

A mi Esposa Marıa Magdalena, a mis papas Eloisa y Victor Rodolfo, a

mis hermanos: Oscar, Elo, Edith y Jose Domingo por hacerme tan feliz.

Contents

1 On the frequency synthesizers. 23

1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2 Frequency synthesizers categories. . . . . . . . . . . . . . . . . . . . . 25

1.3 PLL based Frequency Synthesizers . . . . . . . . . . . . . . . . . . . 26

1.4 Fractional Frequency Synthesizers. . . . . . . . . . . . . . . . . . . . 28

1.4.1 Characteristics of the Fractional Synthesizer. . . . . . . . . . . 31

1.5 Fractional Frequency Synthesizers Limitations and Content of this

Thesis Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.5.1 Fractional Frequency Synthesizers limitations. . . . . . . . . . 33

1.5.2 Content of this thesis. . . . . . . . . . . . . . . . . . . . . . . 33

2 Mathematical and Behavioral Models for Frequency Synthesizers. 35

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2 Spectral purity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2.1 Phase-Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.2 Phase-Noise measure. . . . . . . . . . . . . . . . . . . . . . . . 39

2.2.3 Direct and Reciprocal Mixing. . . . . . . . . . . . . . . . . . . 41

2.3 Phase Noise and Jitter in Frequency Synthesizers. . . . . . . . . . . . 42

2.3.1 Time Domain Jitter Noise . . . . . . . . . . . . . . . . . . . . 43

2.3.1.1 Jitter in autonomous circuits. . . . . . . . . . . . . . 44

2.3.1.2 Jitter in non autonomous circuits. . . . . . . . . . . . 45

2.3.2 Frequency Domain Phase noise. . . . . . . . . . . . . . . . . . 46

7

8 CONTENTS

2.4 Frequency Synthesizer Behavioral model. . . . . . . . . . . . . . . . . 47

2.4.1 Voltage Controlled Oscillator (VCO). . . . . . . . . . . . . . . 47

2.4.1.1 VCO’s time domain Jitter model . . . . . . . . . . . 47

2.4.1.2 VCO’s noise source addition model . . . . . . . . . . 48

2.4.1.3 Models Comparison . . . . . . . . . . . . . . . . . . 49

2.4.2 Phase-Frequency-Detector and Charge-Pump. . . . . . . . . . 51

2.4.2.1 Time domain Jitter model . . . . . . . . . . . . . . . 51

2.4.2.2 The noise addition model . . . . . . . . . . . . . . . 51

2.4.2.3 Models comparison . . . . . . . . . . . . . . . . . . . 52

2.4.3 The programmable frequency divider and Σ∆ modulator. . . . 53

2.5 Application to a Fractional-N frequency synthesizer. . . . . . . . . . . 53

2.6 Trade-Offs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3 Effective Dithering MASH Σ∆ Modulators for Fractional Frequency

Synthesizers 57

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.2 Σ∆ Modulators for Fractional Synthesizers . . . . . . . . . . . . . . . 58

3.2.1 Hybrid Architectures. . . . . . . . . . . . . . . . . . . . . . . . 59

3.2.2 Loop architectures. . . . . . . . . . . . . . . . . . . . . . . . . 60

3.2.2.1 Single-Loop architectures . . . . . . . . . . . . . . . 60

3.2.2.2 Multi-Loop architectures . . . . . . . . . . . . . . . . 61

3.2.2.3 Chebyshev loop . . . . . . . . . . . . . . . . . . . . . 63

3.2.3 MASH architectures. . . . . . . . . . . . . . . . . . . . . . . . 63

3.2.4 Comparison between architectures. . . . . . . . . . . . . . . . 64

3.3 Spur Tones Reduction in MASH modulators . . . . . . . . . . . . . . 66

3.3.1 Prime modulus quantizer . . . . . . . . . . . . . . . . . . . . . 66

3.3.2 Output feedback . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.3.3 Modified Error Feedback Modulator (MEFM) . . . . . . . . . 67

3.3.4 Shaped additive LFSR dither . . . . . . . . . . . . . . . . . . 67

3.4 Dithering MASH Σ∆ modulators with LFSRs . . . . . . . . . . . . . 68

CONTENTS 9

3.4.1 Dither with LFSR in a digital accumulator. . . . . . . . . . . 68

3.4.2 Dither in Multi-Stage-Noise-Shaping. . . . . . . . . . . . . . . 70

3.4.3 Effective LFSR dither for the MASH modulator. . . . . . . . . 72

3.5 Experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.6 Application in a Fractional Frequency Synthesizer. . . . . . . . . . . . 81

3.7 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4 Design of the main blocks for the Fractional Synthesizer. 83

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2 The Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . 85

4.2.1 LC-Tank VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.2.2 Crossed coupled differential pair. . . . . . . . . . . . . . . . . 87

4.2.3 Noise in the VCO (NMOS or PMOS?) . . . . . . . . . . . . . 88

4.2.4 Monolithic inductors in CMOS technology. . . . . . . . . . . . 90

4.2.5 Increasing the linear tuning range in the VCO. . . . . . . . . . 91

4.2.6 VCO non-linear analysis. . . . . . . . . . . . . . . . . . . . . . 95

4.2.7 VCO silicon implementation. . . . . . . . . . . . . . . . . . . . 98

4.2.8 Simulation results. . . . . . . . . . . . . . . . . . . . . . . . . 99

4.2.9 Experimental results. . . . . . . . . . . . . . . . . . . . . . . . 101

4.3 The Programable Frequency Divider . . . . . . . . . . . . . . . . . . 102

4.3.1 The multi-modulus programable divider. . . . . . . . . . . . . 104

4.3.2 The glitch-free design consideration. . . . . . . . . . . . . . . . 105

4.3.3 The high frequency division cells . . . . . . . . . . . . . . . . 108

4.3.4 The medium frequency divide by 2 cells . . . . . . . . . . . . 110

4.3.5 Design for the process variation robustness. . . . . . . . . . . 112

4.3.6 Experimental Results of the Programable-Divider . . . . . . . 115

5 The frequency synthesizer loop design. 119

5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.2 Frequency domain design. . . . . . . . . . . . . . . . . . . . . . . . . 120

10 CONTENTS

5.2.1 The Loop Filter Transfer function . . . . . . . . . . . . . . . . 121

5.2.2 The Stability Criteria . . . . . . . . . . . . . . . . . . . . . . . 123

5.2.3 Design of Parameters . . . . . . . . . . . . . . . . . . . . . . . 123

5.3 The Loop Filter Circuit Implementation. . . . . . . . . . . . . . . . . 125

5.4 The Phase-to-Frequency-Detector. . . . . . . . . . . . . . . . . . . . . 129

5.4.1 The effect of the PFD delay in the reset signal. . . . . . . . . 130

5.4.2 Probabilistic analysis for the PFD. . . . . . . . . . . . . . . . 131

5.4.3 Accurate estimation of the PFD Frequency Limit. . . . . . . . 133

5.4.4 The effect of the Σ∆ modulation. . . . . . . . . . . . . . . . . 135

5.4.5 High frequency analysis. . . . . . . . . . . . . . . . . . . . . . 137

5.5 The Charge-Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.6 The Fractional Frequency Synthesizer circuit. . . . . . . . . . . . . . 144

5.6.1 The Phase-Noise Approximation. . . . . . . . . . . . . . . . . 147

5.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

6 Conclusions. 155

6.1 The simulation strategies. . . . . . . . . . . . . . . . . . . . . . . . . 155

6.2 Effective dithering the MASH Σ∆ modulators. . . . . . . . . . . . . . 157

6.3 The fractional synthesizer loop. . . . . . . . . . . . . . . . . . . . . . 158

6.4 Future work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

A Pseudo Random Generators 161

A.1 Linear Feedback Shift Register (LFSR). . . . . . . . . . . . . . . . . . 161

A.2 Maximally length LFSR. . . . . . . . . . . . . . . . . . . . . . . . . . 162

A.3 Circuit implementation. . . . . . . . . . . . . . . . . . . . . . . . . . 164

B Resumen en extenso 167

B.1 Introduccion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

B.2 Capıtulo 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

B.3 Capıtulo 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

B.4 Capıtulo 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

CONTENTS 11

B.5 Capıtulo 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

B.6 Capıtulo 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Bibliography 173

12 CONTENTS

List of Figures

1.1 Basic scheme of a transceiver. . . . . . . . . . . . . . . . . . . . . . . 24

1.2 PLL based frequency synthesizer. . . . . . . . . . . . . . . . . . . . . 26

1.3 Fractional PLL based frequency synthesizer. . . . . . . . . . . . . . . 29

1.4 Waveforms where the modulus factor is changed. . . . . . . . . . . . 29

1.5 Symbol and block diagram of a digital accumulator. . . . . . . . . . . 30

1.6 Digital accumulator’s scheme and carry out power spectral density. . 31

1.7 Fractional synthesizer with periodicity in the controller. . . . . . . . . 32

2.1 Power spectrum degradation due to phase modulation terms. . . . . . 38

2.2 Power spectral density of a noisy sinusoidal signal. . . . . . . . . . . . 38

2.3 One sided transformation from Signal’s Power Spectral Density to

Phase-Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.4 Direct and reciprocal mixing. . . . . . . . . . . . . . . . . . . . . . . 42

2.5 Jitter and its distribution in a signal . . . . . . . . . . . . . . . . . . . 43

2.6 Autonomous circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.7 Autonomous circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.8 Synthesizer’s equivalent frequency-domain model. . . . . . . . . . . . 47

2.9 VCO and Loop Filter noise addition. . . . . . . . . . . . . . . . . . . 49

2.10 Simulation results for the VCO behavioral models. . . . . . . . . . . . 50

2.11 Phase noise from an integer synthesizer. . . . . . . . . . . . . . . . . 52

2.12 Simulation results of the proposed behavioral models. . . . . . . . . . 54

13

14 LIST OF FIGURES

3.1 Hybrid architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.2 Multi-Phase divider with hybrid Σ∆. . . . . . . . . . . . . . . . . . . 60

3.3 Single loop digital Σ∆ modulator. . . . . . . . . . . . . . . . . . . . . 60

3.4 Comparison of single-loop and MASH noise shaping functions. . . . . 61

3.5 Multi-Loop architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6 Multi-Loop architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.7 Chebyshev architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.8 MASH architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.9 Noise shaping comparison of digital Σ∆ modulators. . . . . . . . . . . 65

3.10 Digital accumulator model. . . . . . . . . . . . . . . . . . . . . . . . . 68

3.11 Dither addition in a digital accumulator. . . . . . . . . . . . . . . . . 70

3.12 Dithering the MASH 1-1-1. . . . . . . . . . . . . . . . . . . . . . . . 71

3.13 Dithered MASH 1-1-1 output spectrum. . . . . . . . . . . . . . . . . 73

3.14 Dithering the MASH 1-1-1. . . . . . . . . . . . . . . . . . . . . . . . 74

3.15 Dithered MASH 1-1-1 output spectrum. . . . . . . . . . . . . . . . . 75

3.16 The Σ∆ modulator contribution to phase-noise. . . . . . . . . . . . . 76

3.17 Microphotograph of the digital modulator. . . . . . . . . . . . . . . . 77

3.18 PCB designed to test the digital Σ∆ modulator. . . . . . . . . . . . . 77

3.19 Experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.20 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.21 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.22 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.1 PLL based Σ∆ fractional synthesizer. . . . . . . . . . . . . . . . . . . 83

4.2 Frequency domain model for the fractional frequency synthesizer. . . 84

4.3 VCO feedback block diagram. . . . . . . . . . . . . . . . . . . . . . . 86

4.4 Compensated LC-tank. . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.5 Crossed coupled differential pair. . . . . . . . . . . . . . . . . . . . . 87

4.6 LC-tank based CMOS VCO’s. . . . . . . . . . . . . . . . . . . . . . . 88

4.7 Cross coupled pair noise analysis . . . . . . . . . . . . . . . . . . . . 89

LIST OF FIGURES 15

4.8 Integrated inductor in 0.35µm process. . . . . . . . . . . . . . . . . . 90

4.9 CMOS VCO with NMOS as varactors. . . . . . . . . . . . . . . . . . 91

4.10 MOS capacitances in transistors used as varactors. . . . . . . . . . . . 92

4.11 Comparison of MOS capacitance when in depletion and triode. . . . . 94

4.12 Comparison of linear ranges for a PMOS varactor. . . . . . . . . . . . 94

4.13 VCO tuning range for different output offset DC value. . . . . . . . . 95

4.14 VCO with PMOS varactors. . . . . . . . . . . . . . . . . . . . . . . . 96

4.15 Drain current as the DC value changes. . . . . . . . . . . . . . . . . . 97

4.16 Schematic view of the VCO. . . . . . . . . . . . . . . . . . . . . . . . 98

4.17 Layout view of the VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.18 Post-Layout simulations of the VCO for Typical Mean, Worst Speed

and Worst Power cases. . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.19 VCO voltage to frequency transference curves. . . . . . . . . . . . . . 101

4.20 Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . . . . . . . 102

4.21 Voltage Controlled Oscillator transfer curve . . . . . . . . . . . . . . . 102

4.22 Dual Modulus Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.23 Phase selection concept for the programable divider. . . . . . . . . . . 104

4.24 Phase selection for the multi-modulus divider. . . . . . . . . . . . . . 104

4.25 Programable frequency divider logic . . . . . . . . . . . . . . . . . . . 105

4.26 Glitch generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.27 Phase arrangements comparison and their time scheme for smooth

transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.28 Multi-modulus programable divider. . . . . . . . . . . . . . . . . . . . 108

4.29 High Frequency divide by 2 cell schematic. . . . . . . . . . . . . . . . 108

4.30 High Frequency divide by 2 cell layout view. . . . . . . . . . . . . . . 109

4.31 Post-Layout simulations of the Divide by 2 circuit for Typical Mean,

Worst Speed and Worst Power cases. . . . . . . . . . . . . . . . . . . 110

4.32 Schematic view for the MF divide by to cell and the signal boos circuits.110

4.33 Medium Frequency divide by 2 cell layout view. . . . . . . . . . . . . 111

16 LIST OF FIGURES

4.34 Post-Layout simulations of the Divide by 4 circuit. . . . . . . . . . . 112

4.35 Process variations unsensitive Phase-Select logic. . . . . . . . . . . . . 112

4.36 Layout of the programable divider. . . . . . . . . . . . . . . . . . . . 113

4.37 Post-Layout simulations of the programable divider. . . . . . . . . . . 113

4.38 Post-Layout simulations of the programable divider. . . . . . . . . . . 114

4.39 Microphotograph of the programable divider and the VCO. . . . . . . 115

4.40 Setup for the measurements. . . . . . . . . . . . . . . . . . . . . . . . 115

4.41 Experimental results of the programable divider. . . . . . . . . . . . . 116

4.42 Experimental results of the programable divider. . . . . . . . . . . . . 117

5.1 Synthesizer’s equivalent frequency-domain model. . . . . . . . . . . . 120

5.2 Low-Pass filter for the frequency synthesizer. . . . . . . . . . . . . . . 122

5.3 Bode analysis for the Fractional Synthesizer. . . . . . . . . . . . . . . 124

5.4 Non ideal Low-Pass filter for the frequency synthesizer. . . . . . . . . 125

5.5 Non ideal Low-Pass filter for the frequency synthesizer. . . . . . . . . 126

5.6 Operational Transconductance Amplifier. . . . . . . . . . . . . . . . . 126

5.7 OTA Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.8 Capacitor and resistor layout. . . . . . . . . . . . . . . . . . . . . . . 127

5.9 OTA Frequency response. . . . . . . . . . . . . . . . . . . . . . . . . 128

5.10 Low-Pass-Filter Frequency response. . . . . . . . . . . . . . . . . . . 130

5.11 The PFD and its waveforms. . . . . . . . . . . . . . . . . . . . . . . . 131

5.12 Waveforms for fref ≥ fdiv. . . . . . . . . . . . . . . . . . . . . . . . . 132

5.13 Layout of the PFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.14 Waveforms for a bad PFD detection. . . . . . . . . . . . . . . . . . . 134

5.15 Waveforms for a correct PFD detection. . . . . . . . . . . . . . . . . 135

5.16 Distribution function of the div transition for fractional synthesis. . . 135

5.17 Normalized value of (u − d)2

for differen σ values. . . . . . . . . . . . 139

5.18 Ideal Charge-Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.19 Charge-Pump schematic and layout views. . . . . . . . . . . . . . . . 141

5.20 Non-overlapped signals for the switching control. . . . . . . . . . . . . 142

LIST OF FIGURES 17

5.21 Network to obtain the control switching signals. . . . . . . . . . . . . 142

5.22 PFD-CP pos-layout simulation. . . . . . . . . . . . . . . . . . . . . . 143

5.23 PFD-CP-LPF pos-layout simulation. . . . . . . . . . . . . . . . . . . 144

5.24 Layout view of the chip designed to test the Fractional Synthesizer. . 145

5.25 Pos-Layout transient simulation of the Fractional Frequency synthesizer.146

5.26 Pos-layout simulation for a big frequency step. . . . . . . . . . . . . . 147

5.27 Simulated Phase-Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.28 Microphotograph of the chip. . . . . . . . . . . . . . . . . . . . . . . 148

5.29 Test setup schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.30 Measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.31 Measurement result when the fractional synthesizer is “locked”. . . . 150

5.32 Signal spectrum when the fractional synthesizer is at 1.45369GHz. . . 150

5.33 Signal spectrum when the fractional synthesizer is at 1.45369GHz. . . 151

5.34 Phase-Noise figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

5.35 Phase-Noise figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

A.1 Linear feedback shift register concept. . . . . . . . . . . . . . . . . . . 161

A.2 2-bits LFSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

A.3 LFSR operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

A.4 Autocorrelation for 4 bit LFSR . . . . . . . . . . . . . . . . . . . . . 165

A.5 Autocorrelation Sequences . . . . . . . . . . . . . . . . . . . . . . . . 165

18 LIST OF FIGURES

List of Tables

2.1 VCO characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.2 Fractional-N frequency synthesizer’s characteristics . . . . . . . . . . 53

3.1 Σ∆ Architectures comparison. . . . . . . . . . . . . . . . . . . . . . . 64

3.2 Σ∆ hardware comparison. . . . . . . . . . . . . . . . . . . . . . . . . 80

3.3 Characteristics of the fabricated digital Σ∆ modulator. . . . . . . . . 80

4.1 CMOS process inductor model parameters. . . . . . . . . . . . . . . . 90

4.2 Id First Fourier coefficients . . . . . . . . . . . . . . . . . . . . . . . . 97

4.3 Size of transistors in the VCO . . . . . . . . . . . . . . . . . . . . . . 99

4.4 VCO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.5 Size of transistors in the High Frequency divide by 2 cell . . . . . . . 109

4.6 Size of transistors in the High Frequency divide by 2 cell . . . . . . . 111

4.7 Programable divider characteristics . . . . . . . . . . . . . . . . . . . 117

5.1 Frequency synthesizer loop parameters. . . . . . . . . . . . . . . . . . 124

5.2 Loop filter parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3 Fractional Frequency Synthesizer parameters. . . . . . . . . . . . . . 147

5.4 Fractional Frequency Synthesizer parameters. . . . . . . . . . . . . . 154

5.5 Σ∆ Architectures comparison. . . . . . . . . . . . . . . . . . . . . . . 154

19

20 LIST OF TABLES

Abstract

This thesis presents a methodology to design a Fractional Frequency Syn-

thesizer. The research lead to many problems that where not completely

solved up to the publication time of this work. The main objective of the

research was the reduction of spur tones in the total phase noise figure due

to the periodicity in the digital Σ∆ modulator. The proposed solution for

the spur tones reduction is an efficient way to add a dither signal in a

MASH 1-1-1 architecture.

The behavioral models are a good tool to model this mixed signal systems

but it is difficult to include all the noise sources in the system. New

simulation scripts are developed to improve the accuracy in the phase

noise prediction. Also, the proposed behavioral models are more direct

from the circuit designer’s point of view.

New design considerations where developed for the voltage controlled os-

cillator to improve the linear tuning range. The programable frequency

divider was designed to be unsensitive to the process, voltage and temper-

ature variations. Finally a statistical model was developed for the phase

to frequency detector which helps to design a delay in the gates building

this digital circuit. All the design considerations can be used to improve

the performance of this mixed signal circuit and even used for other ap-

plications to innovate the integrated circuit design to solve the people

problems.

21

Chapter 1

On the frequency synthesizers.

1.1 Introduction.

The present and future trend for electronic systems is the portability. This has make

necessary to design the integrated circuits with more restricted specifications. Also it

is desirable to integrate analog and digital systems into the same chip. To accomplish

this goal it is necessary to use advanced technologies and design techniques, as well as

to process the signals in a more efficient fashion. For instance, in many communication

systems it is necessary to generate a signal with intermediate frequency to translate

high frequency signals to a frequency range where they are processed easier. The

translation operation is necessary because if the signal processing were done in the

high frequency domain (as the signals in the reception block) it would be very difficult

to design the circuits capable to process the signal at that frequency and the power

consumption would be enormous.

A basic scheme for a wireless communication system is shown in figure 1.1 where

a data signal in a transmitter is modulated on a carrier frequency cos(ωot) and trans-

mitted trough the electromagnetic channel. The receiver amplifies the signal in a Low

Noise Amplifier (LNA) and translates the signal to a range where it can be processed

by the demodulator. Although the main goal is not to explain the complete architec-

ture of a transceiver it is worth to note that the frequency translation operation is

23

24 1.1. Introduction.

Data in Encoder Decoder

Data out

Transmiter Receiver

LNA IRF

Figure 1.1: Basic scheme of a transceiver.

necessary in wireless communications and/or for portable systems.

For those systems the frequency translation can be achieved by the mixing op-

eration between a high frequency signal x(t) and the signal generated in the system

cos(ωot). The mixing operation of this signals can be expressed as:

F [x(t)cos(ωot)] =1

2F

[x(t)

(e+jωot + e−jωot

)]=

1

2[X (f + fo) + X (f − fo)] (1.1)

The block generating the mixing signal (cos (ωot)) in this systems is the Frequency

Synthesizer. A frequency synthesizer can generate a square or sinusoidal signal and

alike a single oscillator it changes its output frequency by an analog or digital control

with an accuracy depending on the synthesizer’s architecture and application. The

use of a frequency synthesizer is not restricted to the transceiver as the one shown

in figure 1.1. The frequency synthesizer can also be used in modulation schemes [1]

and in automatic control for clock distribution networks; to cite some of the different

applications.

The signal cos(ωot) generated by the frequency synthesizer must be pure in order

to avoid the corruption of the translated signal X(f) due to direct and/or reciprocal

mixing [2], [3]. The corruption of the signals can cause impulsive noise in audio

systems, image distortion in video broadcasting and an unacceptable bit-error-rate in

digital transmission systems. In the next chapter the fundamentals on spectral purity

are reviewed.

1. On the frequency synthesizers. 25

1.2 Frequency synthesizers categories.

There are several frequency synthesizers architectures and each one is suitable for

one of the previously mentioned applications; most of them can be grouped in three

categories [4]:

♣ Direct digital synthesizers.

In this synthesizers a digital to analog converter (DAC) obtains data from a

digital memory to generate a signal with a frequency equal to a reference clock.

If the DAC’s sampling clock signal is divided, the synthesizer can be program-

able. The DAC output is low pass filtered to eliminate the undesired harmonics

generated in the Digital to Analog conversion; this makes very difficult to get

a signal with good spectral purity without using a high order analog filter.

The great disadvantage is the limited operation frequency and the high power

consumption. For a relatively high frequency of operation, a DAC flash archi-

tecture is needed. The flash architecture consumes big amounts of power and

the number of elements increase exponentially as the resolution increases [5].

♣ Direct analog synthesizers.

The analog mixing and frequency division operations are used in this synthesiz-

ers. That is, from a reference analog oscillator (usually LC-tank based) several

mixers and frequency dividers are cascaded to translate the frequency to dif-

ferent values. In contrast with the direct digital synthesizers they can generate

signals with higher spectral purity but the area and power consumption are in-

creased. As the mixers are non linear elements, the amplitude of the harmonics

obtained from the mixing operation is comparable to the fundamental signal [4]

so it is also necessary to design high order filters. The frequency division can

be a power consuming task if it is realized by digital techniques; to solve this

issue the injection locked oscillators are used as frequency dividers [6].

26 1.3. PLL based Frequency Synthesizers

♣ Indirect synthesizers.

The indirect generation of the signal with a Phase Locked Loop (PLL) config-

uration is a technique which combines analog and digital blocks to synthesize

a signal at low cost. Compared to the previous classes, the advantages of this

synthesizers among others are: high integration level, compatible with low cost

integrated circuit fabrication process and low area and power consumptions.

This thesis work is focused in this kind of synthesizers and their fundamentals

are exposed in the following section.

1.3 PLL based Frequency Synthesizers

The indirect frequency synthesizer using the Phase Locked Loop (PLL) configura-

tion [2] is the best solution to generate a signal in an integrated circuit having the

most stringent characteristics. The PLL configuration consist on a Phase Frequency

Detector (PDF), a Charge-Pump (CP), a Low Pass Filter (LPF), a Voltage Controlled

Oscillator (VCO) and a Frequency Divider (FD); all of them arranged in a closed

loop as shown in figure 1.2.

PFD CP LPF

N

VCO

+I cp

-I cp

V control

F out

F ref

Figure 1.2: PLL based frequency synthesizer.

The PFD and CP generate current pulses which represent the phase difference

between the signals coming from the reference signal and from the frequency divider

(θerr = θref − θdiv). The current pulses are low pass filtered and a voltage signal at

the loop filter’s output tunes the VCO. The signal at the VCO’s output is divided by

N to compare it latter to the reference signal and close the loop. In this architecture


the generated signal has an output frequency that is an entire multiple from the

reference frequency. Although the literature has demonstrated that this is the best

way to generate a signal in an integrated circuit some limitations are present. This

limitations will be resumed in next paragraphs.

The VCO and the Frequency Divider are the blocks working at high frequency

so they not only impose the output frequency limit, but also they are the most

power consuming elements in the synthesizer. Every block in the loop adds noise

to the synthesizer which degrades the output signal (a noise study will be presented

in chapter 2, section 2.2). In order to accomplish with the Phase-Noise spectral

mask that the communication protocols impose, the loop filter usually has a cut-off

frequency much lower than the reference frequency. As a rule of thumb it is 10 times

lower than the reference frequency [3] to accomplish with the noise specifications. On

the other hand, if the loop filter has a very low cut-off frequency, the integration of the

circuits with very low time constants (big capacitors for instance) could be difficult

and the settling time would be very large.

Another issue in this system is the election on the reference frequency. Remember

that for this entire PLL synthesizer architecture, the output frequency is an entire

multiple of the reference frequency. There are applications where it is necessary

to change the output frequency with very narrow steps (less than 200kHz for the

communication protocols, as the American GSM [7], [8]). Taking as an example the

American GSM protocol, if in an entire PLL synthesizer a 200kHz reference frequency

is used, it is almost impossible to integrate the loop filter (for the reasons given above).

Also, the settling time will never be less than 300µs which is the required settling

time specification for the GSM protocol [9].

Also, as the output frequency is an entire multiple from the reference frequency;

if a very low reference frequency is used, a very high division modulus is needed

in order to get high frequencies at the synthesizer’s output. As will be explained

in the following chapters this could be good for the output Phase-Noise but the

divider’s complexity is increased. From this discussion it can be concluded that the

28 1.4. Fractional Frequency Synthesizers.

worst disadvantage from entire frequency synthesizers is the constraint which links

the division modulus to the reference frequency election. The best solution to this

issue has been the Fractional Frequency Synthesizers [10].

1.4 Fractional Frequency Synthesizers.

The fractional frequency synthesis [10] is one of the best ways to decouple the con-

straint that links the reference frequency with the step resolution. With this technique

it is possible to generate an output frequency being an entire factor plus a fractional

value from the reference frequency. This allows not only to choose a reference fre-

quency as high as possible to have a good settling time, but also to have enough

spectral purity for the communication protocol the synthesizer is designed for. In-

creasing the reference frequency makes easier to integrate the loop filter in the same

die and the frequency divider can have a lower division modulus factor.

There are different ways to generate an output frequency being a fractional mul-

tiple from the reference frequency. The two most important are:

1. Fractional synthesis using multiple phase switching [11]

2. Fractional synthesis using the PLL configuration [10].

The former uses the VCO’s output signal to obtain several delayed versions with

a delay value less than the VCO’s period. The fractional division factor is obtained

if the signals having different phases are switched to change the total output period.

The resolution depends on the quantity of delayed signals within one VCO’s period.

Besides, the time-varying displacing (due to noise) of the generated signals can yield

and erroneous division. For the communication protocols, such as GSM, the quantity

of channels is about 372 with a 200KHz spacing between them, in a band from

(1.710 − 1.785)GHz. For this protocol it is difficult to generate that quantity of

delayed signals to get a fractional division without uncertainty in the phase.


PFD CP LPF

N,(N+1)

VCO

+I cp

-I cp

Controller

K

F out

F ref

T H T L

Figure 1.3: Fractional PLL based frequency synthesizer.

The fractional synthesis using the PLL configuration is realized by changing ran-

domly the division modulus factor at every reference frequency transition. This ran-

dom switching between division modulus factors is to obtain, “in average”, an entire

plus a fractional division as will be explained next. This task can be done by chang-

ing the modulus factor in a programable divider between N and N + 1 with a digital

controller clocked by the reference frequency (figure 1.3).

To see more clearly how the fractional modulus is obtained, consider the timing

diagram from figure 1.4 where five division cycles are considered in the signal from

the VCO. If, from those five division cycles, the VCO’s output is divided during three

division cycles by N = 2 and during two division cycles by N = 3 the average output

frequency is:

fout =3Nfref + 2(N + 1)fref

5=

(N +

2

5

)fref (1.2)

N N N+1 N+1 N

VCO

DIV 1 2 3 4 5

Figure 1.4: Waveforms where the modulus factor is changed.

Probably, the most simple digital controller (to change the modulus division) is


a digital accumulator of m resolution bits as is shown in figure 1.5. The carry out

from the accumulator is the signal controlling de division modulus with a duty cycle

TH/TL.

Carry out

K Adder (m-bits)

Register (m-bits)

K Carry out

T H

T L

Figure 1.5: Symbol and block diagram of a digital accumulator.

With carry on low value during TL the division modulus is N . With the carry

output on high value during TH the division modulus is N + 1. The average division

modulus is Nav = N + n with N the closest integer value on the programable divider

and n = K2m (m is the word bit size on the accumulator and K is the digital constant

wort at the input of the accumulator). Ideally, by increasing the accumulator’s resolu-

tion (increasing m) the division modulus factor can be changed with highly fractional

values.

If a deeper analysis is made, it can be noticed that the digital accumulator is a

first order digital Σ∆ modulator [12]. The digital Σ∆ modulator is a block which

traduces a constant signal at the input to an oversampled signal (it can be single or

multiple bit). This oversampled signal is a pulse modulated signal whose time average

value yields the constant value at the input. The digital Σ∆ modulator makes a

quantization operation and the quantization error is shaped by a high-pass function.

This high-passed quantization error adds another noise source to the PLL loop in

the Fractional Synthesizer and must be considered at the design time. The theory

on Σ∆ modulators used for oversampled Analog to Digital converters [12] can be

extrapolated to the design of digital Σ∆ modulators used for Fractional Synthesizers.

In the following chapters a deep analysis to the digital Σ∆ modulators used in the

Fractional Synthesizers is realized.


1.4.1 Characteristics of the Fractional Synthesizer.

Although the fractional synthesis can be obtained with a single-bit first order digital

Σ∆ modulator it is not the best solution. In one hand the digital Σ∆ modulators

don’t suffer from mismatch and/or finite gain in the components (the integration

is perfect in contrast to their analog counterparts [12]). On the other hand, the

quantization error at the output of the integrator (accumulator) is a deterministic

signal and the Σ∆ modulator’s output will be a repeating sequence controlling the

division modulus in the Frequency Synthesizer. Figure 3.4 shows the block diagram

of a digital accumulator and the approximated power spectral density of the carry

output when there is a constant input.

Carry out

K

(a)

104

105

106

107

−400

−350

−300

−250

−200

−150

−100

−50

0

Frecuencia (Hz)

PS

D (

dB)

(b)

Figure 1.6: Digital accumulator’s scheme and carry out power spectral density.

The spur tones appearance in the Σ∆ modulator output spectrum (see figure 1.6(b));

means that the controlling sequence will make the output from the divider to be peri-

odic. This periodicity will be reflected as periodic current pulses at the charge-pump

output and the VCO’s output will contain non desirable spur tones, as in figure 1.7

is shown.

As can be seen in figure 1.6(b) the quantization noise for a single-bit first order

digital Σ∆ modulator is almost uniformly distributed along the range (0, Fs), where


PFD CP LPF

N/(N+1)

VCO

+I cp

-I cp

K T H

T L

Frequency (Hz)

F out

F ref

TONES

Figure 1.7: Fractional synthesizer with periodicity in the controller.

Fs is the oversampling rate (and clock frequency) in the digital modulator. In most

Fractional Synthesizers, using Σ∆ modulators, the oversampling rate has the same

frequency than the reference frequency Fs = Fref . When the spectrum of a Fractional

Synthesizer using a Σ∆ modulator is analyzed, it will have spur tones at an offset

frequency very close to the carrier. The spectral purity is affected by this spur tones

and is necessary to avoid them.

One solution to make less significant the spur tones influence in the Fractional

Synthesizer can be to reduce the loop filter cut-off frequency. Unfortunately, this

is contradictory with the advantage on the technique, which allows to use a higher

reference frequency to integrate the loop filter.

As the first order Σ∆ modulator does not accomplish with the spectral purity

and capacity on integration; in the literature there can be found several techniques

to reduce the influence of Σ∆ modulation in the Fractional Synthesizer’s output

phase-noise. During the next chapters the most important of those techniques will be

exposed. Also, the main issues in the fractional synthesizers design will be identified.

Those issues are related with the design and simulation strategies in order to integrate

a fractional frequency synthesizer on the same die. Some alternatives to solve those

problems are proposed in this thesis work.


1.5 Fractional Frequency Synthesizers Limitations

and Content of this Thesis Work.

1.5.1 Fractional Frequency Synthesizers limitations.

From the discussion in the previous sections it is clear that there are many drawbacks

in the Fractional Frequency Synthesizers. In this thesis work it was found that the

most important problems to solve are:

♦ The simulation strategies for the frequency synthesizers.

♥ The spur tones reduction in the Phase-Noise spectrum due to the digital Σ∆

modulator.

♣ The Voltage Controlled Oscillator tuning range.

♠ The programable frequency divider limitations.

Many works present in the literature have solved some of this issues and they will

be mentioned along this thesis work. In spite of it, this drawbacks have been just

partially solved. This thesis work focuses on solving in an efficient way the problems

previously mentioned.

1.5.2 Content of this thesis.

The following chapters will discuss the origin of each limitation and will mention the

most important proposed solutions. Chapter 2 presents a study of the modelling and

simulation of fractional frequency synthesizers and a new way to model the noise in

this systems is proposed.

Chapter 3 explores the spur tones generated by the digital Σ∆ modulation and a

new way to avoid them, without increase the complexity of the systems, is presented.

Chapter 4 presents the design of the VCO and programable frequency divider, which

341.5. Fractional Frequency Synthesizers Limitations and Content of this

Thesis Work.

are crucial elements of a fractional frequency synthesizer. Once the VCO and fre-

quency divider characteristics are known, the chapter 5 presents the design method-

ology of the fractional frequency synthesizer loop. That is the PFD-Charge-Pump

and Loop filter parameters can be designed to ensure stability. Finally, chapter 6

presents the main conclusions of this thesis work and the future work though this

research line.

The thesis work is supported with post-layout simulations results to describe the

design methodology for the integrated circuit. Also, experimental results obtained

from the integrated circuit fabrication prove the theories developed in this research

job.

Chapter 2

Mathematical and Behavioral

Models for Frequency Synthesizers.

2.1 Introduction.

In order to properly design a Fractional Frequency Synthesizer with a Phase Locked

Loop (PLL) configuration, it is necessary to fully understand all the noise and error

sources in the circuits building it. When the design of this Fractional Synthesizers is

realized, usually, it is necessary to run many transistor level simulations. This comes

unpractical when the objective is to optimize the performance of the components one

by one, because the simulation and design time grow significatively. Therefore, it

is very useful to describe behavioral models for this mixed-signal system taking into

account the noise and error sources during the circuit design. The behavioral models

are high level hardware description scripts which are used in the netlist for the fast

simulation of analog and/or digital blocks. To describe this models, a standard code

like VerilogA or VerilogAMS is used. A circuit simulator (such as Spectre, Hspice or

ADMS) is used to get the accurate values for the electrical variables of the network

in a DC, transient or AC simulation.

Matlab-Simulink is also a good tool to model mixed-signal systems but it is not

capable to substitute the models by transistor level blocks. On the other hand,

35

36 2.2. Spectral purity.

VerilogA is a tool that can make last issue possible going down a transistor level

design. In plain words: with VerilogA it is possible to simulate jointly a circuit

modelled as a behavioral model and a circuit with device level models. A simulation

of the frequency synthesizer, only with behavioral models, is also very useful when

the specifications for every block in the synthesizers are obtained and a preliminary

result is needed.

Beyond all this advantages, when the specifications and performance of a cell are

evaluated, it is necessary to include as many non ideal characteristics as possible.

The inclusion of this non ideal characteristics makes the behavioral simulation to

describe more accurately the circuit performance. In this chapter the mathematical

description and behavioral modelling of the frequency synthesizers are explored. A

new methodology to improve the accuracy of behavioral simulation is proposed and

is compared with mathematical models presented in literature [13], [14], [15], [16]. It

is also demonstrated, with behavioral transient simulations, that this new strategy to

simulate the synthesizer (though behavioral models); allows to predict the spectral

purity (phase noise) more accurately than state-of-the-art models.

2.2 Spectral purity.

Ideally, the frequency synthesizer must generate a pure signal; mathematically that

signal can be described as.

x(t) = A cos (ωot + θo) (2.1)

Nevertheless, due to different noise sources in the frequency synthesizer this ideal

behavior is deviated, resulting in amplitude and phase variations. The noisy signal

can be expressed as:

xη(t) = A(t) cos (ωot + θ(t)) (2.2)

Where the terms A(t) and θ(t) are the amplitude and phase noisy modulating

2. Mathematical and Behavioral Models for Frequency Synthesizers. 37

signals. Usually the frequency synthesizer has a high amplitude output and the

amplitude modulation term (A(t)) can be neglected, making the signal to be only

phase modulated (xpm(t) = A cos(ωot + θ(t)). For this phase modulated signal, if the

phase modulating term is θ(t) = Aθ cos(ωmt) and Aθ ≪ 1 [17]:

xpm(t) ≈ A cos(ωot) +AAθ

2[cos((ωo − ωm)t) + cos((ωo + ωm)t)] (2.3)

For an amplitude modulated signal xam(t) = (1 + Am sin ωmt)A cos (ωot); this

equation can be expanded as:

xam(t) ≈ A cos(ωot) +AAm

2[sin((ωo − ωm)t) + sin((ωo + ωm)t)] (2.4)

By comparing equations 2.4 and 2.3 it is demonstrated that mathematically is not

possible to distinguish between the noisy terms generated by amplitude modulation

or phase modulation terms [17]; both of them have the same effect in the spectral

purity and the omission in the amplitude modulation term has no consequence in the

fundamental concept. This helps to mathematically analyze the effect of the noise

in the signal generated by the frequency synthesizer, giving rise to the Phase-Noise

definition.

2.2.1 Phase-Noise.

Consider the phase modulated signal with the phase modulation term as a single tone

(θ(t) = Aθ cos(ωmt)):

xpm(t) = A cos (ωot + Aθ cos(ωmt)) (2.5)

For the case Aθ ≪ 1 the signal can be expressed as:


2[cos((ωo − ωm)t) + cos((ωo + ωm)t)] (2.6)

In the frequency domain this phase modulation term adds two harmonics at a

frequency ωo ± ωm (as shown in figure 2.1b). If the phase modulation term contains


a) b) c)

Frequency (Hz)

P o w

e r (

d B / H

z )

Frequency (Hz)

P o w

e r (

d B / H

z )

Frequency (Hz)

P o w

e r (

d B / H

z )

Figure 2.1: Power spectrum degradation due to phase modulation terms.

more harmonics, the spectrum of a pure sinusoidal signal changes from a Dirac delta

to the one shown in figure 2.1c.

Theoretically, if infinite phase modulation terms are added the power spectral

density of the modulated signal takes the form shown in figure 2.2. In fact, the noise

which generates the phase disturbances can be modelled as an infinite number of

phase components. From the last point of view, it can be said that the skirt shaped

spectrum in figure 2.2 it is a measure of how the phase, and though the instantaneous

frequency, is changed randomly. As this skirt shaped spectrum of a noise sinusoidal

signal can be represented as phase fluctuations, it has received the characteristic name

of Phase-Noise.

Frequency (Hz)

P o w

e r (

d B / H

z )

Frequency (Hz)

P o w

e r (

d B / H

z )

Figure 2.2: Power spectral density of a noisy sinusoidal signal.


2.2.2 Phase-Noise measure.

The Phase-Noise is the phase fluctuation rate (and though the instantaneous fre-

quency fluctuation rate) in the periodic signal generated by a system. The system

can be an Oscillator, a Synchronous Logic Circuit or a Frequency Synthesizer. If in

an ideal situation the phase fluctuations are caused by only a single sinusoidal com-

ponent θ1(t) = Aθ sin(ωo + ωmt) the power spectral density of this pase fluctuation

component is:

Sθ1(ω) =A2

θ

2δ (ω − ωm) (2.7)

This equation was obtained from the analysis in equation 2.6 and figure 2.1. For

the case when a signal is phase modulated by a single tone, the signal power spectral

density can be approached as:


2[cos((ωo − ωm)t) + cos((ωo + ωm)t)]

SX(ω) ≈ A2

2

δ(ω − ωo) +

A2θ

2δ(ω − (ωo − ωm)) +

A2θ

2δ(ω − (ωo + ωm))

SX(ω) ≈ A2

2

δ(ω − ωo) +

1

2Sθ1(ωo − ω) +

1

2Sθ1(ω − ωo)

(2.8)

Where the Dirac’s delta symmetry property is used (δ(ω − ωo) = δ(−(ω − ωo))).

For this ideal case, the power spectral densities of the phase modulating signals and

the fundamental signal can be related and a new term is defined as ϑωm:

ϑωm =SX (ωo + ωm)

SX(ωo)(2.9)

Evaluating equation 2.8 in equation 2.9 the power spectral densities are related

by:

ϑωm = (A2/2)Sθ1(ωm)

A2/2(2.10)


If the relative one sided amplitude (i. e. taking only one side of the spectrum) of

the power spectral density is considered; then:

Lonesidefm =Sθ1(fm)

2(2.11)

The relation between the phase modulation term and the fundamental signal’s

power spectral densities in equation 2.9 can be extrapolated to the continuous skirt

shape and a continuous one sided Phase-Noise figure is defined as:

Lonesidefm =

(SX(fo + ∆fm)

SX(fo)

)(2.12)

Expressed in decibels:

Lonesidefm = 10 log10

(Signal’s Power at ∆fm in a 1Hz bandwidth

Fundamental Signal Power at fo

)(2.13)

The one sided Phase Noise Figure Lonesidefm is the relation between the power

spectral density of the noisy signal in a ∆fm frequency offset from the carrier with the

power of the fundamental component at fo. For convenience it will be referred just as

the Phase-Noise figure instead of one sided Phase-Noise figure. The Frequency domain

to the Phase-Noise domain transformation is the way to measure the spectral purity in

Frequency Synthesizers. A graphical description for the one sided transformation can

be seen in figure 2.3. To make more comfortably the phase-noise descriptions to the

reader, the therm Lonesidefm will be referred only as Lfm. Knowing previously

that the Lfm is the one sided Phase Noise Figure.

Although Lfm is only an approximation for the real Phase-Noise measure; it

was demonstrated in equations 2.9 - 2.11 that the real Phase-Noise, Sθ(f), is related

to the noise figure Lfm as:

Sθ(f) = 2Lfm (2.14)


Frequency (Hz)

P o w

e r

( d B

/ H z )

Frequency Offset From the Carrier (Hz)

L f m

( d B

c / H

z )

Figure 2.3: One sided transformation from Signal’s Power Spectral Density to Phase-Noise Figure.

This is valid just for low amplitude phase modulation terms and for close fre-

quencies offset from the carrier frequency [2]. This limit in the approximation comes

from the suppositions made to express the single tone phase modulation term in

equation 2.3 (section 2.2.1). The one sided transformation from the signal’s power

spectral density to Phase-Noise figure Lfm is not the only way to measure the

spectral purity in a signal coming from a frequency synthesizer. The timing Jitter is

also a measure for the spectral purity in the time domain [18], [19]. In the following

sections it will be demonstrated that the time Jitter and the Phase-Noise are two

ways to demonstrate the same phenomena.

2.2.3 Direct and Reciprocal Mixing.

It was mentioned before that the signal generated by the frequency synthesizer must

be pure to avoid the corrupted information. When the signal is used to translate an

incoming information from the RF spectrum; the skirt on this signal’s power spectral

density can mix some components from an adjacent frequency channel, giving as a

result the direct and reciprocal mixing.

In figure 2.4 both effects are presented. The noisy generated signal (at a frequency

ωLO) will down-convert the signal at frequency ωRF1; the phase noise components on

both signals will be added and a direct mixing is obtained. On the other hand, the

42 2.3. Phase Noise and Jitter in Frequency Synthesizers.

Frequency (rad/s)

P o w

e r ( d B

)

Direct mixing

Reciproc mixing

Figure 2.4: Direct and reciprocal mixing.

skirt shaped spectrum of the generated signal will also down-convert the undesirable

signals at an adjacent RF channel (at a frequency ωRFa) this is known as indirect

mixing. From figure 2.4 it can be seen that the contribution of both mixing actions

will degrade the down-converted signal’s spectrum.

From this section it is worth to emphasize the great importance of spectral purity

in Frequency Synthesizers. The phase noise figure defined through this sections must

accomplish with the Phase-Noise mask that the communication protocol imposes [9].

2.3 Phase Noise and Jitter in Frequency Synthe-

sizers.

The purity of a periodic signal is the characteristic describing how much this signal

deviates from the ideal representation (see section 2.2). The goal of a frequency

synthesizer is to generate a pure periodic signal to avoid the corrupted information.

Nevertheless, the noise and error sources in the frequency synthesizer’s blocks make

the output signal to change randomly the phase (and tough the frequency) so the

noise sources affect the output signal’s spectral purity. This can be measured as

Phase Noise or as Jitter in the output signal. Phase Noise and Jitter are two ways to

describe the same phenomena; the former in the frequency domain and the latter in

the time domain. In this section a more detailed description of both metrics is done.


2.3.1 Time Domain Jitter Noise

Jitter is the timing uncertainty of a transition event in a signal. The uncertainty

comes from the noise in the timed circuits and it can be represented as an error time

function (j(t)) having a normal distribution. Starting from the Jitter free signal; the

error can be added as [13]:

VJitt(t) = v (t + j(t)) (2.15)

A

t

Jitter free.

With Jitter

t 0

t

Figure 2.5: Jitter and its distribution in a signal .

Figure 2.5 shows the waveform of a Jitter free signal (solid line) and the signals

under the Jitter influence (doted lines). The time Jitter makes the location of the

transition time t0 to randomly change and is not possible to predict it exactly. In spite

of it, it can be modelled as a pseudo random process with a time distribution for the

transition uncertainty (look at the graphic for the distribution σ(j(t)) in figure 2.5).

The variance of this random process can be expressed in terms of the physical noise

which generates the Jitter.

To calculate the variance of the error timing signal “σ (j(t))”; the Phase Noise as

defined in section 2.2 can be related to the Jitter. For this it is necessary to distinguish

between Jitter in autonomous circuits (short term Jitter) and Jitter in driven circuits

(long term Jitter); as explained below.


2.3.1.1 Jitter in autonomous circuits.

An autonomous circuit is a cell which generates, by itself, a signal that oscillates. A

good example is a VCO that generates a periodic signal as shown in figure 2.6.

T 1 T 2

Figure 2.6: Autonomous circuit.

The period in the signal from the VCO may change in a random way and in

figure 2.6 T1 6= T2. An important characteristic in autonomous circuits is that the

variation between time periods is not correlated. This means that the time displacing

of the zero cross values in the waveforms are not cumulative. That is, the jitter is not

cumulative and it is known as short term jitter.

For the autonomous circuits, the short term jitter σ (jfm(t)) can be calculated by

taking the phase noise as [13]:

Sφ (fm) ≈ 2Lfm = af 2

o

f 2m

(2.16)

where Sφ (fm) is the Phase-Noise figure and Lfm is the Phase-Noise approximation

from the signal’s power spectral density. The factor a is the Power Spectral Density of

the noise that causes Jitter, fo is the carrier frequency and fm is the frequency offset

from the carrier. If the noise is assumed to be white the last expression is valid only

for frequencies (fm) not far away from the carrier frequency (fo). This expression

can be obtained in several ways which can be explored in literature [2]. The ranges

where this approximation is valid is still an open research field for this mathematical

models.

As the phase noise cannot be measured directly from a Spectrum Analyzer, it is

more useful to relate the Phase Noise to the noise figure Lfm:

Lfm =Sφ (fm)

2=

a

2

f 2o

f 2m

(2.17)


The Jitter time variance can be estimated from the Lfm noise figure as:

Jk =√

kaT (2.18)

Where T is the period of the signal in the autonomous circuit. The k′th term is

the time shift related to the first period of the autonomous signal. Actually this jitter

must be considered as uncorrelated and it can be modelled as a Gaussian random

process. Nevertheless, in order to make a more simple model, it can be described as

a Gaussian random cyclostationary process; such that Jk = J1 and:

J =√

aT (2.19)

2.3.1.2 Jitter in non autonomous circuits.

The non autonomous circuits (also known as driven circuits) are cells which need a

trigger signal to make an operation. A good example are all the digital cells with

static or dynamic logic. This circuits need a signal to trigger the logic values to yield

a logic state. Figure shows 2.7 the schematic and waveforms of NAND gate. If the

A or B signals have a time variance in the switching time, the output signal will be

affected by this time variance.

A

B

O

A

B O

Figure 2.7: Autonomous circuit.

If the signals A or B are periodic, this time variance will be cumulative and the

jitter is known as long term jitter. For the driven circuits which present long term

jitter; the time displacing variance σ (jpm(t)) of every transition event is more directly


related to the power spectral density of the noise that generates it. The jitter variance

is obtained as in [13]:

J =√

2σ (jpm(tc)) (2.20)

where tc is the time of the transition output event and the jitter variance is defined

as the relation between the time average power of the noise generating the jitter and

the signal’s slew rate:

σ (jpm(tc)) ≡σ(ηn)∂(vtc )∂(t)

(2.21)

Using the Parserval’s theorem and the simplest slew rate definition it is possible to

show that [13]:

J =

√T 〈η2

n〉ttVH − VL

(2.22)

The term: 〈η2n〉 =

∫∞

−∞Sn(f)df is the total time average noise power spectral

density which generates the jitter (ideally is the noise integrated overall the spectra).

The term tt is the transition time for the signal and (VH − VL) is the total signal

change. With expressions (2.18) and (2.22) it is possible to model the Jitter variance

in the behavioral models. It is achieved by converting its Phase Noise figure to the

time variance of the signal in the autonomous or driven circuits.

2.3.2 Frequency Domain Phase noise.

In [14] it has been presented a deep analysis to the Fractional-N Synthesizers mixed-

signal behavior. By using some constraints the frequency domain model can be

represented as in figure 2.8.

The main noise sources in the Frequency Synthesizer can be grouped as: the noise

coming from the PFD-Charge-Pump, from the Loop-Filter-VCO and from the digital

Σ∆ modulated division factor. The total output phase noise can be estimated by


cp I Loop filter H(f)

VCO

jf K v

1/T nom N

1

n[K]

Figure 2.8: Synthesizer’s equivalent frequency-domain model.

considering the individual noise sources in the loop:

Soutn (fm) = |Hn(j2πfm)|2 Sinputn (fm) (2.23)

and

Ssynt (fm) =∑

n

Soutn (fm) (2.24)

Where Soutn (fm) represents the n − th contribution to the total synthesizer’s noise

Ssynt (fm). The Sinputn terms are the noise sources which are shaped by their input-

to-output phase noise transfer function Hn (j2πfm). This Phase Noise frequency

representation is more direct to express in the circuit design terms when it is included

within the behavioral models. However, the time domain Jitter representation is

preferred for the compatibility with the VerilogA capabilities. Nevertheless, in this

work a great difference between the simulation and theoretical results was observed

when the phase noise was modelled as time Jitter in the behavioral models.

2.4 Frequency Synthesizer Behavioral model.

2.4.1 Voltage Controlled Oscillator (VCO).

2.4.1.1 VCO’s time domain Jitter model

The advantage of using VerilogA in behavioral models is the easy inclusion of the

Jitter noise by displacing the signal’s transition slightly by a normal distributed time

function as follows [13]:

48 2.4. Frequency Synthesizer Behavioral model.

freq = freq / (1+ dT*freq);

phase = 2*M PI*idtmod(freq,0.0,1.0,-0.5);

@(cross(phase + ‘M PI/2),+1,ttol) or

cross(phase + ‘M PI/2),+1,ttol)) begin

dT=1.414*jitter*$dist normal(seed,0,1);

n= (phase >= ‘M PI/2) && (phase < ‘M PI/2);

end

V(out) < + transition(n ? 1:-1, 0, tt);

This previous model for the VCO is very efficient only for a short range of frequen-

cies due to the considerations taken to estimate the Jitter in equations (2.16,2.18).

2.4.1.2 VCO’s noise source addition model

The VCO can also be behaviorally described by using the relationship for the VCO

output phase deviations and the control voltage:

Φout(t) =

∫2πKvVctrl(t)dt (2.25)

where Vctrl is the input control voltage, Φ is the output phase and Kv is the VCO’s

gain. This equation can be used to describe the VCO as follows:

analog begin

freq = (V(input)-Vmin)*(Fmax-Fmin)/ (Vmax-Vmin) + Fmin;

if (freq > Fmax) freq = Fmax;

if (freq < Fmin) freq = Fmin;

phase = 2*M-PI*idtmod(freq,0.0,1.0,-0.5);

v(out) < + sipha;

end

This ideal behavior is deviated by the noise sources into the VCO and Loop Filter,

changing the phase randomly from cycle to cycle. A single noise source can group

both noise contributions as shown in figure 2.9.


Loop filter H(f)

VCO

jf K v

Figure 2.9: VCO and Loop Filter noise addition.

The total power delivered by the noise source is equal to the variance of the

random signal:

σ2 (η) =

∫∞

0

S (f) df. (2.26)

where S (f) = κ (white noise). The integral has no a closed form solution but it

can be integrated over a frequency band (0, Fup). Therefore, a limit frequency can

be estimated as the one with the most dynamic in the simulation and Fup = Fsample.

If a relatively low frequency white-noise signal is sampled at a frequency Fsample

(respecting the sampling Nyquist condition) the total rms value for the noise source

is:

ηrms =√

S (f) Fsample (2.27)

In this work the sampling frequency is at least 2 times the frequency from the

VCO. For instance if the output signal is fout = 1GHz, then Fsample = 8fout = 8GHz

is a good election.

The noise source including the contributions from the loop filter and the VCO can

be behaviorally described as:

analog begin

@ (initial-step) begin seed = 23;

end

vrms= sqrt(power*Fsample);

randnum= $dist-normal(seed,0,1);

V(out) < + randnum*vrms;

end

2.4.1.3 Models Comparison

A VCO was modelled with the characteristics shown in table 4.4. The Vrms value


Table 2.1: VCO characteristics.

Tuning Range (1.47 − 1.87)GHz

Kvco 247MHzV

Voltage input range (0.25 − 1.87)V

Phase Noise @ 100KHz ≈ −145dBc

of the noise source output can be known from the transfer function of the VCO

and the expected value on the Phase-Noise (equation 2.23). For the case SV CO ≈−145dBC@10KHz with a simulation sampling frequency of 8.216GHz the Vrms ≈5.2 ·10−22. The short term Jitter variance can be obtained from equation (2.18); with

an output frequency of about 1.56GHz the variance jitter is J ≈ 91.3 · 10−18s.

104

105

106

107

−260

−240

−220

−200

−180

−160

−140

−120

−100

−80

−60

Frequency offset from the carrier (Hz)

Pha

se n

oise

L(f

m)

(dB

/Hz)

Theoretical VCO phase noise.

Behavioral model with Jitter term.

Behavioral model with noise source.

Figure 2.10: Simulation results for the VCO behavioral models.

Figure 2.10 shows the VCO’s output phase noise for the individual simulations of

the models and compared with the expected theoretical noise figure obtained from a

mathematical model as in [14]. As the theoretical analysis predict in section 2.2, the


simulation of the behavioral model as the time domain Jitter [13] predicts the phase

noise just for close frequencies offset from the carrier (only up-to @700KHz). The

proposed behavioral model which adds a white-noise source in the control voltage

predicts the phase noise much better for high frequencies offset from the carrier.

2.4.2 Phase-Frequency-Detector and Charge-Pump.

2.4.2.1 Time domain Jitter model

The PFD-CP long term Jitter can be behaviorally described as a time displacing

transition. This is due to the PFD error nature because the logic gates traduce the

voltage noise into Jitter noise, so the dependence on the signal’s slew rate is more

direct as opposite to the short term Jitter in the VCO. The Jitter variance can be

calculated from equation (2.22) where it is worth to note how the slew rate is directly

related to the noise variance, in the behavioral model it is described as [13]:

@(cross(V(ref), +1,ttol)) begin;

if (state > -1) state = state-1;


end

....

I(out) < + transition(Iout*state, td+dt , tt);

Unfortunately, this Jitter representation does not take into account the Charge-

Pump noise from the current sources.

2.4.2.2 The noise addition model

Usually the noise source contribution from the Charge-Pump current sources domi-

nates the jitter in the PFD. Then it is necessary for the PFD-CP behavioral model

to include the analog noise addition to the Charge Pump current by using a noise

generator. The behavioral model for the PFD-CP including this characteristic is:


@(cross(V(ref), +1,ttol)) begin;

if (state > -1) state = state-1;


end

....

randnum=$dist normal(seed,0,1);

I(out) < + transition(Iout*state + irms*randnum, td+dt , tt);

Where the product irms ∗ randnum defines the time average power noise added

by the Charge Pump. In this way the current noise has a normal distribution having

a variance that is calculated from equations (2.26) and (2.27). The noise contribution

from the Charge-Pump current sources can be obtained again from equation (2.23).

2.4.2.3 Models comparison

Figure 2.11 shows a comparison between a simulation with the noise source in the

charge-pump and the simulated only as jitter in the behavioral model. The ideal

Phase-Noise figure again was obtained as the mathematical model in [14].

105

106

107

−200

−180

−160

−140

−120

−100

−80

−60


Pha

se n

oise

L(f

m)(

dB/H

z)

Behavioral model adding CP noise source.Theoretical noise figure.Behavioral model only with PFD Jitter.

Figure 2.11: Phase noise from an integer synthesizer.

The simulation results show that the proposed behavioral model approaches much

better because the source CP transistors noise dominates the jitter term and it should


Table 2.2: Fractional-N frequency synthesizer’s characteristics

Synthesizer 4rd order Tuning (1.47 − 1.87)GHz

Σ∆ modulator MASH 1-1-1 Fref 26MHz

Σ∆ output bits 4 fc ≈ 100KHz

be considered at the simulation time.

2.4.3 The programmable frequency divider and Σ∆ modula-

tor.

The divider’s ideal model counts the VCO’s rising edges and only makes an up-

transition when it has counted N VCO’s cycles. The frequency divider can be pro-

gramable if the division modulus is established as an input parameter. For the Digital

Σ∆ modulator a behavioral gate level model is good to substitute latter by the logic

gate circuits. The phase noise characteristic for the this deterministic blocks can also

be included as in the PFD-CP case but one must decide if the Jitter noise in this

blocks affects significatively the total Phase Noise output. The objective is to get a

trade-off between simulation time and accuracy of the noise prediction.

2.5 Application to a Fractional-N frequency syn-

thesizer.

A Fractional-N frequency synthesizer using the proposed frequency domain based on

verilogA behavioral models has been simulated in Hspice. The characteristics of this

synthesizer are summarized in table 2.2.

The Power Spectral Density has been obtained from a 224 sample sequence us-

ing a windowed (Welch) method and compared to an ideal analytical model. The

phase noise was measured from a fractional synthesized output with a(61 − 77

256

)=

54 2.5. Application to a Fractional-N frequency synthesizer.

109.191

109.194

109.197

109.2

109.203

109.206

−160

−140

−120

−100

−80

−60

−40

Frequency (Hz)

Out

put p

ower

(dB

)

Referencefrequency.

(a) Synthesizer’s output power spectrum estimation.

105

106

107

−160

−150

−140

−130

−120

−110

−100

−90

−80

−70


Pha

se n

oise

L(f

m)(

dB/H

z)

Transient VerilogA simulationTeoretical nosie figure.

(b) Synthesizer’s output phase noise.

Figure 2.12: Simulation results of the proposed behavioral models.

60.699219 division value. With a 26MHz reference frequency, the output frequency

was about 1.5781797GHz. Figure 2.12(a) shows the estimated power spectrum of the

transient simulation where the Σ∆ modulation effect is evident.

The total output phase noise obtained from the transient simulation is shown

in figure (2.12(b)) and is compared to the ideal noise figure. The estimated power

spectral density is used to obtain the Phase-Noise result (Lfm) and the ideal noise

figure was obtained from the mathematical model presented in [14]. As the results

show, with this models the PFD-CP and VCO contributions are accurately included

and the Phase Noise is well predicted. Also, this behavioral simulations allows to

design a block in the Fractional-N Frequency Synthesizer considering the real effect

of the noise sources in the loop.

The use of this frequency domain based models also allows a more direct estimation

of the noise sources compared to a time domain jitter representation, which needs a

previous conversion of the noise to the time domain jitter variance. That is, the

noise sources power can be represented as a function of the circuit parameters which

generate the principal noise sources. With equations (2.23-2.27) the circuit designer is


able to know how much noise will be added by the circuits. The only disadvantage is

the increased simulation time but as they are still behavioral models, the simulation

time is less than transistor level simulations.

2.6 Trade-Offs.

In this chapter an accurate behavioral model for PLL based fractional frequency

synthesizers was proposed. It has been demonstrated that the Jitter representation

predicts the Phase-Noise just for a restricted range in the frequency from the offset

interval. The addition of noise sources representing the main noise contributions in

the synthesizer predicts much better the output Phase Noise. With this noise source

addition it is also possible to describe the noise in the Charge-Pump which is more

difficult to include just as jitter in the PFD.

However, there must be a trade off between the quantity of noise sources added

into the system and the simulation time. The most dominant noise sources are the

noise from the Charge-Pump and the noise from the digital Σ∆ modulator. The noise

from the LC-Tank VCO is not as dominant unless the VCO is realized with in a non

LC-Tank architecture.

56 2.6. Trade-Offs.

Chapter 3

Effective Dithering MASH Σ∆

Modulators for Fractional

Frequency Synthesizers

3.1 Introduction

In the first chapter of this thesis it was mentioned that the Fractional Frequency

Synthesizers, using Σ∆ modulation, are a good solution to integrate a Frequency

Synthesizer; with the fine step resolution and the high spectral purity that the di-

verse communication protocols impose. In this Frequency Synthesizers, the fractional

frequency step resolution is obtained by changing the division modulus factor with

the output sequence from a digital Σ∆ modulator [10].

Although the power consumption of the Frequency Synthesizer from the Voltage

Controlled Oscillator “VCO” and the high frequency blocks in the Frequency Divider

are big problems; attention must be paid to the digital Σ∆ modulator since it increases

the complexity and cost of the circuit. This is because the Σ∆ modulation affects the

Synthesizer’s total Phase-Noise figure. The spur tones, from the quantization error,

affect the Phase-Noise even more. When the Σ∆ modulator has a constant input,

57

58 3.2. Σ∆ Modulators for Fractional Synthesizers

the Phase-Noise degradation can be worst. Therefore, usually complex digital Σ∆

architectures must be selected to avoid the fractional spur tones and to accomplish

the Phase-Noise specifications.

In this chapter a deep insight into the spur tones magnitude reduction techniques

in MASH architectures is presented. The contribution of this work relies in the use

of closed form equations to characterize the digital Σ∆ modulator periodicity, when

a dither signal from a LFSR is added as a Least Significant Bit (LSB). The effects

of adding the dither signal in different paths within the modulator are expressed in

the equations and the results are compared. With this research, it is mathematically

demonstrated that a pseudo-random generator, with a very long repeating sequence,

will not reduce the spur tones magnitude; if it is not added in a path that disables the

periodicity in the digital modulator. On the other hand, the equations are used to

demonstrate that a very simple dither generator (obtained from a small sized LFSR)

can be as effective as more complicated Σ∆ architectures, if added in a path which

disables the periodicity.

3.2 Σ∆ Modulators for Fractional Synthesizers

To avoid the spur tones in the total Phase-Noise figure the Σ∆ modulator must be

of high order and to have enough quantization levels. Contrary to this, for Fractional

Synthesizers, the Σ∆ modulator’s order must be equal or less to the synthesizer order;

otherwise the Phase-Noise figure will be greatly affected [8]. Many architectures have

been proposed to accomplish this restriction. Below, in this section we compare some

of them to show that the MASH architecture has the best trade-off for complexity

and performance. We have classified this architectures in three main groups:

3. Effective Dithering MASH Σ∆ Modulators for Fractional FrequencySynthesizers 59

3.2.1 Hybrid Architectures.

The resolution in a Σ∆ modulator can be increased with hybrid topologies. This

architectures do not increase significatively the hardware. The architecture presented

in [20] is built by a MASH architecture and a concentrator (another digital Σ∆

modulator) as shown in figure 3.1.

k

ACCU. ACCU. ACCU. 25 25 25

Noise Cancellation 3

CONC.

1 Y

Figure 3.1: Hybrid architecture.

The concentrator is used to convert the multi-bit output (from the MASH archi-

tecture) into a single-bit output. In this way, high order modulation is obtained and

the synthesizer order restriction is accomplished. Although the input word length is

large (more than 24-bit), it is well known that a single bit output makes more difficult

to avoid the spur tones in the Σ∆ modulator spectrum. This limits the benefits of

the architecture.

Another hybrid architecture has been presented in [11] where the Multi-Phase

Fractional-Division is proposed. For this technique, the programable divider selects

between 16 signals with different phases to achieve a fractional division. To avoid the

spur tones and to increase the resolution, a long input word (24-bit) is separated. The

20 LSB’s are processed by a high order digital Σ∆ modulator as shown in figure 3.2.

The high order Σ∆ modulator makes the quantization noise to be enough ran-

domized and finally a first order digital Σ∆ modulator produces the output sequence

that controls the multi-phase frequency divider. Unfortunately, to make the output

sequence random enough to avoid spur tones, the high order Σ∆ modulator must be

at least of sixth order and the multi-phase frequency divider needs to be robust to


Fist Order Sigma- Delta

High- Order

Sigma- Delta

k

20

Fractional Multi-Phase Divider

INT FRACT

4 4

F out

F in

Y (sigma delta out)

Figure 3.2: Multi-Phase divider with hybrid Σ∆.

ensure an accurate delay between phases. The Hybrid architectures appear to reduce

the spur tones but at the high cost of increasing the hardware.

3.2.2 Loop architectures.

3.2.2.1 Single-Loop architectures

The single loop architectures can be designed to reduce the quantization noise pushed

to high frequencies. Figure 3.3 shows the block level model of the single loop digital

Σ∆ modulator proposed in [21].

z -1 z -1 z -1 X Y 0.5

1.5

2.0 8-level

Figure 3.3: Single loop digital Σ∆ modulator.

The noise shaping transfer function of this single loop architecture is:

Hn(z) =(1 − z−1)

3

1 − z−1 + 0.5z−2. (3.1)

In figure 3.4 the noise shaping functions of the single-loop and a MASH archi-

tecture are compared. It can be seen that the advantage of this Σ∆ modulator is

the suppressed quantization noise for high frequencies due to the poles into the noise

shaping function of equation 3.1.


106

107

−100

−80

−60

−40

−20

0

Frequency (Hz)

Nor

mal

ized

Pow

er (

dB)

MASH 1−1−1SIngle−Loop

Figure 3.4: Comparison of single-loop and MASH noise shaping functions.

The multi-bit quantizer in this single-loop architecture makes the output to appear

more random and the spur tones are less prominent. Nevertheless, in [21] a pseudo

random signal with a 24-bit Linear Feedback Shift Register (LFSR) is added to disable

the tones. All the advantages are at a cost of an increased complexity to realize the

forward loops and the increased in-band noise (although it will be filtered by the

fractional synthesizer loop). The stability of the digital modulator depends on the

loop coefficients which also limit the input dynamic range.

3.2.2.2 Multi-Loop architectures

Several multi loop digital Σ∆ architectures have been proposed [22], [23]. The goal

in this architectures is to obtain a high order modulator to avoid the spur tones in

the output Power Spectral Density (“PSD”). At the same time the noise shaping

transfer function must not increase the relative low frequency Phase-Noise figure of

the frequency synthesizer. This multi loop architectures use, in general, multipliers

to add coefficients in the loop to avoid instability. In [23] a fourth order digital Σ∆

modulator with 4 loops as shown in figure 3.5 is proposed. Every loop consists of


an accumulator, an adder and 2 multipliers to obtain the scaling coefficients from a

multi-bit quantizer.

ACC ACC ACC ACC

ACC 3 Y

K

z -1

b1 b2 b3 b4

Figure 3.5: Multi-Loop architecture.

The disadvantage is the great complexity to achieve a multi-loop architecture and

the coefficients to avoid instability may limit the input dynamic range. To overcome

this problem another architecture is proposed in [24] to increase the input dynamic

range and to reduce the high frequency shaped noise. For that topology the zeros

in the noise transfer function are moved to a value being a multiple of the minimum

fractional division step; just as the noise transfer function in equation 3.2 for an

specific design in [24]:

Hn(z) = 1 −(

3 − 612

216z−1

)+

(3 − 612

216z−2

)− z−3 (3.2)

This noise transfer function is a modified version of a third order MASH noise

transfer function with an increased complexity. To disable the spur tones on this

architecture a dither signal is added at the quantizer input as is shown in the model

presented in [24] (see figure 3.6); the dither signal is obtained from a 20-bit LFSR,

increasing the complexity even more.

3

z -1 z -1 z -1

m1 m2 FCW

dith

out

Figure 3.6: Multi-Loop architecture.


3.2.2.3 Chebyshev loop

As mentioned for the previous architectures, the reduction of the noise shaped quan-

tization noise is at a cost of an increased noise for low frequencies and there must

be a trade off. The architecture shown in figure 3.7 has a Chebyshev noise transfer

function and has a better compromise [25].

ACC ACC ACC

a b c d

f e

g

K Y

Figure 3.7: Chebyshev architecture.

The noise transfer function of this architecture is:

N(z) =z3 − 3z2 + 3z − 1

(1 − abf)z3 − (3 + abcd + abf)z2 + 3z − 1(3.3)

This transfer function has the best noise shaping as will be shown in the following

subsection. Again, the disadvantages in this architecture, is the complexity and the

one bit quantizer at the output which makes the spur tones to appear.

3.2.3 MASH architectures.

The Multi Stage Noise Shaping (MASH ) architectures [26], [27] have the simplest

configuration because they only use adders and registers to be implemented. The

MASH Σ∆ modulation uses accumulators in a cascade configuration and the quan-

tized output of each stage is processed by a noise cancellation logic as shown in

figure 3.8.

As for digital MASH architectures the noise cancellation logic is perfect, the quan-

tization noise is only the one of the last accumulator (with a shaping order equal to

the modulator’s order). Furthermore, non like most of the architectures, the signal

transfer function does not affect to the input. For a constant input it is not of a


z -1

z -1

z -1

z -1 z -1

X

Y

3-bit

C 1

C 2

C 3

Figure 3.8: MASH architecture.

Table 3.1: Σ∆ Architectures comparison.

Σ∆ Σ∆ Order Synt. Order Dither Spurs

and (fc/fref )

Single-Loop [21] 3 4 (0.005) 224 LFSR −80dB@200KHz

Multi-Loop [22] , [23] 4 5 (0.023) No dither −70dB@300KHz

Error-Feedback [24] 3 4 (0.0153) 210 Off-Chip LFSR No

Hybrid [20] ≥ 4 5 (0.02) No Dither −70dB@10MHz

Hybrid [11] ≥ 6 3 (0.0031) No Dither No

Chebyshev [25] 3 5 (0.0106) No Dither No

MASH [27] 3 4 (0.00135) Off-Chip Dither No

concern but for Frequency Synthesizers used as modulator it is a very valuable char-

acteristic. This architecture is inherently stable and the dynamic range consist of all

the input quantization levels. The only disadvantage is the high probability for this

architecture to generate spur tones because of the low complexity. In this thesis work

this disadvantage is eliminated in a more efficient way.

3.2.4 Comparison between architectures.

Table 3.1 compares the different Σ∆ architectures, when used in a fractional syn-

thesizer, with the normalized loop filter cut-off frequency (fc/fref ), the spur tones


magnitude and the dither characteristic (if used). It is clear that the Hybrid, Multi-

Loop and Chebyshev architectures do not need a dither signal to avoid the spur tones

and the loop filter cut-off frequency can be relatively large. This is at a cost of a

significant increase in the hardware to design the Σ∆ modulator. It can be seen in

the table 3.1 that for some Single and Multi-Loop architectures a dither signal is

added (as a LSB from a LFSR with more than 24-bit), but they present spur tones.

On the other hand, the MASH modulator has a simpler architecture only with adders

and registers but it is necessary to add a dither signal. Because of this drawback,

for fractional synthesizers with MASH modulators, a low frequency loop filter in the

synthesizer is used to reduce the spur tones (see fc/fref in table 3.1).

105

106

107

−120

−100

−80

−60

−40

−20

0

Frequency (Hz)

PS

D (

dB)

MASH 1−1−1Single−LoopMulti−LoopChebyshev

Figure 3.9: Noise shaping comparison of digital Σ∆ modulators.

The noise shaping figures of the architectures reviewed in this chapter are pre-

sented in figure 3.9. It is clear that the best noise shaping from all the architec-

tures is the Σ∆ Chebyshev because it reduces the high frequency shaped noise. The

Multi-Loop and Single-Loop architectures have an improvement in the noise shaping

reduction but again the hardware is increased. The MASH architecture has a similar

noise shaping function (even compared with the Multi-Loop architecture) but the

most important advantage is the significant reduction in the hardware, compared to

66 3.3. Spur Tones Reduction in MASH modulators

the other topologies.

The only disadvantage of the MASH architecture is the spur tones that presents

due to the great simplicity of the architecture. In this work it is proposed to add a

pseudo random sequence for MASH architectures in a much more efficient way.

3.3 Spur Tones Reduction in MASH modulators

In the previous section it was concluded that the MASH modulators are the most

simple digital Σ∆ modulators. They also have very similar noise shaping figures

compared with more complicated architectures. In spite of it they are prone to the

spur tones generation. Many works in literature have reduced the spur tones in

the MASH architecture. Some of them are listed in the next paragraphs to make a

comparison.

3.3.1 Prime modulus quantizer

To reduce the spur tones magnitude, a high resolution digital MASH Σ∆ modulator

can be used (increasing the hardware) where it is necessary to set a sort of initial

conditions as empirically demonstrated by Borkowski in [28], [29]. This was later

mathematically demonstrated by Hosseini [30] with the estimation of the sequence

length of a l-st order MASH architecture. It was also demonstrated that the sequence

length is equal to the quantization level M, if M is a prime number. This design

consideration reduces de spur tones magnitude but the prime modulus quantizer is

more complicated than a power of two quantizer. Another disadvantage is the need to

ensure the zero initial conditions for the quantization errors in the digital modulator.

3.3.2 Output feedback

Liu in [31] proposed a novel topology to randomize the output sequence of a MASH

modulator. The technique consist on taking the output of the digital MASH ar-

chitecture and process it into another digital accumulator; the accumulator output


substitutes the least significant bit of the MASH input. The drawback is the modi-

fication of the input signal in the MASH architecture, which might be negligible for

constant inputs. The technique cannot be used for a non-DC input as the signal

transfer function filters the input signal.

3.3.3 Modified Error Feedback Modulator (MEFM)

Hosseini in [32], [33] created a theory to ensure a maximum sequence length in MASH

architectures with a modified accumulator, having a feedback loop. With this theory

all the semi-empirical works previously presented can be explained. Nevertheless, for

the MEFM MASH modulators to have a maximally length sequence, every accumula-

tor needs an extra M -bit adder. Besides, an output filter to compensate the feedback

paths in the modulator must be instantiated at the MASH output. Under this con-

ditions the MASH architecture has as much hardware as a single-loop architecture

presented in section 3.2.

3.3.4 Shaped additive LFSR dither

Adding a pseudo random signal at the modulator’s input least significant bit (LSB)

is one of the first techniques to reduce the spur tones magnitude; for any digital Σ∆

modulator. The basic idea is to use a very long pseudo random generator to make

the quantization error to appear more randomized. The problem with this way to

reduce the spur tones magnitude is not only the modification to the input signal, but

also the increased quantization noise for very low frequencies in the output spectrum.

This drawback was latter solved by introducing a shaped dithered signal by an analog

Σ∆ modulator with an input DC value [34]. Also in that work, it was proposed to

add the dither signal into the MASH accumulator stages to obtain a shaped dither.

In this thesis the different forms to add a pseudo-random sequence from a LFSR

in MASH topologies are explored. It is demonstrated that the LFSR size can be

reduced and the spur tones reduction and the dither addition is as effective as more

complex techniques but with much less hardware.

68 3.4. Dithering MASH Σ∆ modulators with LFSRs

3.4 Dithering MASH Σ∆ modulators with LFSRs

The research presented in this section treats with the addition of a dither signal

coming from a pseudo-random generator (a linear feedback shift register LFSR) into

MASH architectures. Although the substitution of the least significant bit into the

digital MASH modulators is not an addition; the only way to obtain a close form

expression to estimate their periodicity is by approximating this action as an addition.

Then, the theory proposed by Hosseini [30], [32], is used in this work to demonstrate

an efficient way to add the dither signal from a small sized LFSR and not by a very

large one; as it was done in previous works.

3.4.1 Dither with LFSR in a digital accumulator.

Figure 3.10 shows the block level model of a M -bit digital accumulator; which is the

main block of the digital Σ∆ MASH modulators. The access nodes where the dither

signal can be added is at: accumulator’s input, adder’s output and after the delay. If

the dither signal is added at the input of the accumulator, then the traditional LFSR

input dither is obtained. If the dither signal is added before or after the delay signal

(see figure 3.10) the accumulator’s output Y (z) can be expressed as:

Y (z) ≈ X(z) +1

Mz−1D(z) +

(1 − z−1

)E1(z) (3.4)

where X(z) is the input signal, E1(z) is the quantization error and D(z) is the dither

signal.

z -1

X y[n]

m 1-bit

Points where dither can be added

z -1

m

M-bit LFSR

-e 1 [n]

-e 1 [n]

d[n]

y[n] X

m

M

1/M

Figure 3.10: Digital accumulator model.


By substituting the LSB in this way the dither signal does not affect the input

signal X(z). To estimate the periodicity of the digital accumulator for this case, the

output error sequence can be calculated as:

e1[n] =

(x[n] +

1

Md[n] + e1[n − 1]

)mod M

e1[n − 1] =

(x[n − 1] +

1

Md[n − 1] + e1[n − 2]

)mod M (3.5)

for a constant input x[n] = X the error signal can be written as:

e1[n] =

(nX +

1

M

n∑

k=1

d[k] + e1[0]

)mod M (3.6)

for the quantization error to be periodic e1[n] = e1[n + N ] and:

(NX +

1

M

N∑

k=1

d[k]

)mod M = 0 (3.7)

To estimate the period of the quantization error (N), when the dither signal is

added with a LFSR; we take as a premise that this pseudo-random generator has the

same number of ones and zeroes [35] so:

N∑

k=1

d[k] =N

2=

KM

2. (3.8)

If the dither signal comes from a M -bit LFSR; then if N = KM where K is

an entire number representing the periodic characteristic of the LFSR. Then we can

write:

(NX +

K

2

)mod M = 0 (3.9)

as K/2 can be an entire number for every K power of two then the value (NX +K/2)

is divisible by M for several values of X and the dither signal from the M bit LFSR

does not have any effect on the digital accumulator.


Figure 3.11: Dither addition in a digital accumulator.

Figure 3.11 shows the approximated power spectrum from a Matlab-Simulink sim-

ulation of an 8-bit accumulator with X = 128 for three cases: when the accumulator

is not dithered, when the dither is added as in figure 3.10 with an 8-bit LFSR and

when the dither is added with an ideal digital wide-band white noise source. It is

noticeable how the dither will not randomize the output sequence even when the

dither generator is ideal, which is the case of a very large LFSR. We can conclude

from this analysis that increasing the size of the LFSR will not improve the spur

tones magnitude reduction. Therefore, the equation 3.8 is a good approximation in

this analysis.

3.4.2 Dither in Multi-Stage-Noise-Shaping.

If two or more accumulators are cascaded, the Multi- Stage-Noise-Shaping (MASH )

architecture is obtained. This architecture can be used in fractional synthesizers.

When a dither signal is introduced, no matter the low frequency quantization noise

is filtered by the frequency synthesizer loop, it is desirable to reduce it. This can

be achieved by introducing the dither signal in the internal nodes of the MASH

modulator. Besides, for Fractional Synthesizers it is important to maintain the input


signal unchanged.

z -1

X

y[n]

m+1 1-bit

z -1

m+1 1-bit

z -1

m+1 1-bit

z -1

z -1

3-bit

M-bit LFSR

1/M

-e 1 [n]

-e 2 [n]

-e 3 [n]

y 1 [n]

y 2 [n]

y 3 [n]

M

M

M

d[n]

Figure 3.12: Dithering the MASH 1-1-1.

In a third order MASH modulator the dither can be shaped if the LSB a the input

of the third accumulator is substituted by the pseudo random signal; as it is modelled

in figure 3.12. The 3-bit output signal for this case is:

Y (z) = X(z) +1

M

(1 − z−1

)3D(z)+ (3.10)

(1 − z−1

)3E3(z).

The dither signal D(z) now is shaped by the third order function of the MASH. In

order to estimate the period (N) of the quantization errors in the MASH modulator

of figure 3.12, we can write:

e1[j] = (jX + e1[0]) mod M (3.11)

e2[k] =

[k∑

j=1

(jX + e1[0]) mod M + e2[0]

]mod M (3.12)

e2[k] =

(k(k + 1)

2X + e1[0] + e2[0]

)mod M (3.13)


and similarly to the case of the dithered accumulator, the quantization error in the

dithered third stage of the MASH 1-1-1 is:

e3[n] =

[n∑

k=1

(e2[k] +

1

Md[k] + e3[0]

)]mod M (3.14)

for the quantization error to be periodic, e3[n] = e3[n+N ] and using the equations 3.12

to 3.14:(

N(N + 1)(N + 2)

3 · 2 X +1

M

N∑

k=1

d[k]

)mod M = 0 (3.15)

if the premise for the LFSRs is used as previously, then the last equation can be

written as:(

N(N + 1)(N + 2)

3 · 2 X +1

M

KM

2

)mod M = 0 (3.16)

In this equation, as K/2 can be an entire number for every K power of two, the

value (N(N+1)(N+2)X)3·2

+ K/2) is divisible by M for several values of X. Therefore, for

this dither topology, the dither signal from a very large LFSR does not reduce the

quantization spur tones magnitude.

To prove this, the approximated power spectrum of an 8-bit MASH 1-1-1 modu-

lator from a MATLAB simulation is shown in figure 3.13 again for the cases: when

the dither is not added, when the dither is added as in figure 3.12 with an 8-bit LFSR

and with an ideal band limited white noise source.

From the figure it can be seen that the spur tones magnitude is the same for the

three cases. This proves the theory developed in the last subsection: increasing the

size of the LFSR will not improve the spur tones magnitude reduction.

3.4.3 Effective LFSR dither for the MASH modulator.

It was demonstrated that if the dither signal from a pseudo random generator is added

at the input of the third stage (to reduce the low frequency quantization noise) it will


Figure 3.13: Dithered MASH 1-1-1 output spectrum.

not reduce the spur tones magnitude; no matter if the LFSR sequence length is very

large. In spite of it, if the pseudo-random sequence is added in a different path it can

reduce the spur tones magnitude with a very simple pseudo random generator.

The idea in this analysis is to disable the periodicity of the MASH modulator

output sequence. There are several paths where the dither signal can be added but

the selected path must have a trade-off between the periodicity disabling and low

frequency noise increase. In this research the best path to add a pseudo-random

sequence in a MASH 1-1-1 is shown in figure 3.14. This can be achieved by only

substituting the LSB at the input of the last two stages, by the signal coming from a

M -bit LFSR. This will not add more hardware to the modulator.

The quantization errors for this case are:

e2[k] =

[k(k + 1)

2X +

1

M

k∑

j=1

d[j] + e1[0] + e2[0]

]mod M (3.17)


z -1

X

y[n]

m+1 1-bit

z -1

m+1 1-bit

z -1

m+1 1-bit

z -1

z -1

3-bit

M-bit LFSR

1/M

-e 1 [n]

-e 2 [n]

-e 3 [n]

y 1 [n]

y 2 [n]

y 3 [n]

M

M

M

d[n]

Figure 3.14: Dithering the MASH 1-1-1.

e3[n] =

[n(n + 1)(n + 2)

3 · 2 X +1

M

n∑

k=1

k∑

j=1

d[j]

+n∑

k=1

d[k] + e1[0] + e2[0] + e3[0]

]mod M (3.18)

for the quantization error to be periodic e3[n] = e3[n + N ] and we can write:

[N(N + 1)(N + 2)

3 · 2 X +1

M

N∑

k=1

k∑

j=1

d[j]

+N∑

k=1

d[k]

]mod M = 0 (3.19)

now the double summation cannot be approximated as an entire number which is

divisible by M because for every k value the d[j] values will not be uniformly dis-

tributed. With this way to add the dither signal, the quantization error period N

does not depend on the input value X. When the dither signal is added as it is

proposed, the 3-bit output after the noise cancellation logic can be written as:


Y (z) = X(z) + 1M

D(z)((1 − z−1) + (1 − z−1)2

)

+ (1 − z−1)3E3(z) (3.20)

Figure 3.15: Dithered MASH 1-1-1 output spectrum.

The figure 3.15 shows the approximated output power spectral density of the 8-

bit simulated MASH 1-1-1 modulator for the three cases: when the modulator is not

dithered, when a dither signal from a simple 8-bit LFSR is added as in figure 3.14

and when an ideal white noise source is added as the dither signal in the same fig-

ure. It can be seen that the 8-bit LFSR dither is enough to reduce the spur tones

at high frequencies offset from the carrier frequency, although some low frequency

components increase the noise (but they can be filtered by the frequency synthesizer

as demonstrated in figure 3.16).

If the sequence length of the pseudo-random generator is increased up to an ideal

random signal (see figure 3.15), the dither noise is shaped and the low frequency noise

increases. Nevertheless, the high frequency spur tones magnitude is the same as for

the 8-bit LFSR case.

76 3.5. Experimental results.

103

104

105

106

107

−200

−180

−160

−140

−120

−100

−80

−60

Offset frequency from the carrier (Hz)

Pha

se−N

oise

Lm

(f)

(dB

c/H

z)Total Phase−NoiseSigma−DeltaCharge−PumpVCO Loop−Filter

Sigma−DeltaContributionRegion

Figure 3.16: The Σ∆ modulator contribution to phase-noise.

The advantages to add a dither signal in this way is the noise shaping function for

the dither signal with no additional components but only the substitution of the LSBs

at the indicated nodes. Also, a very simple M -bit LFSR can be used to reduce the

spur tones magnitude for the high frequencies offset from the carrier (which are the

components affecting the total fractional synthesizer phase-noise). Another advantage

among the previous techniques is that the constant modulated signal is not affected

by the dither addition and there is not necessity of a post filter stage.

3.5 Experimental results.

In order to demonstrate the advantages of the proposed dither addition philoso-

phy a third order digital MASH Σ∆ modulator was fabricated in a 0.35µm CMOS

process. The circuit consist of a Multi-Project in an Austiamicrosystems (AMS ) via

Europractice run. The digital Σ∆ modulator was designed with the Standard Cells

from the digital library of the AMS design kit. A standard cell auto-place and route

tool was used to reduce the time-to-test.


The MASH 1-1-1 has an 8 − bit resolution in each accumulator. The micropho-

tograph of the chip is shown in figure 3.17 where the dither generator is as simple as

an 8-bit LFSR [36]. This shift register has a maximally length architecture and the

design considerations are presented in Appendix A. It can be seen in the microphoto-

graph how the dither generator barely increases the system complexity. The digital

Σ∆ has a core area of (315 × 340)µm. The core orientation was placed in such a

way the transmission lines of the clock signal and the outputs of the modulator had

a similar length to reduce the skew.

Figure 3.17: Microphotograph of the digital modulator.

Figure 3.18: PCB designed to test the digital Σ∆ modulator.

The test setup (shown in figure 3.18) was designed to test the circuit for a sample


frequency of 25Mhz with a double layer printed circuit board (PCB). The PCB was

designed to change the digital input of the modulator and to enable and disable the

dither generator to make experimental comparisons. A zero insertion force socket

(KYOCERA part no. 84-536-11) was used to reduce the parasitics effects and the

transmission lines were carefully designed to reduce the skew between the signals in

the PCB. Also the output pins where of gold plating to reduce the parasitic effects on

the PCB. The digital Σ∆ modulator was tested with a 3.3V bias and with a reference

frequency of (25 − 120)Mhz.

(a) Test setup. (b) Time configuration Digital Analyzer output.

Figure 3.19: Experimental setup

The output from this very simple dither generator is applied to the MASH modu-

lator as proposed in section 3.4.3 and the data where obtained with a Logic Analyzer

HP 1663A as in figure 3.19(a). The data where captured with the logic analyzer in

state time configuration but the circuit states can be analyzed in time domain con-

figuration as presented in figure 3.19(b). This data where later stored and used to

obtain the PSD in MATLAB.

Figure 3.20(a) shows a comparison of the measured approximated power spectral

density of the MASH modulator when it is not dithered, when the dither is added

with an 8-bit LFSR and with the MEFM MASH [33] (being the state of the art most

effective spur reduction technique). The graphic is plotted in a linear scale to compare

the high frequency behavior for the three cases. The spur tones magnitude reduction


at high frequencies is the same for the MEFM and the simple M -bit LFSR. As the

noise increase (due to the noise shaping) for low frequencies can be eliminated by the

fractional synthesizer; the 8-bit LFSR proposed dither is as effective as the MEFM

structure but much less complicated.

The autocorrelation sequence is the best form to explore the periodicity of a

discrete sequence and it was calculated for a 213 output sequence for the measured

data and a simulated MASH 1-1-1 MEFM. Figure 3.20(b) shows a detailed view of

the autocorrelation sequences; it can be seen that both of them have very similar

characteristics.

(a) PSD from measurement data. (b) Output autocorrelation sequence.

Figure 3.20: Experimental results

The MASH 1-1-1 MEFM [33] is used to compare the 8-bit LFSR dither addition

as it is the most effective spur tones magnitude reduction up to now. It has been

proven that the simple 8-bit LFSR is enough to reduce the spur tones magnitude if

it is added in the indicated nodes which disable the MASH periodicity.

The only difference between the simple dither addition and the MASH MEFM

structure is the hardware budget. Table 3.2 makes a coarse comparison of the hard-

ware used for both spur tones reduction strategies taking into account only the number

of gates used for each one. The simple 8-bit LFSR dithering increases less than 10%


Table 3.2: Σ∆ hardware comparison.Architecture Number Normalized

of gates HardwareUndithered MASH 1-1-1 420 100%

MEFM MASH 1-1-1 ( [32]) 640 152%M -bit LFSR dither (this work) 460 109%

Table 3.3: Characteristics of the fabricated digital Σ∆ modulator.

Σ∆ Architecture MASH 1-1-1

Sample Frequency ≤ 80MHz

Core area (315 × 340)µm

Dither area percentage from core 2.1%

Dynamic power consumption 3.63mW@26MHz

Spur reduction 30dB

the number of gates. With this little increase in the number of gates, the layout area

could slightly increase due to the routing. With the MEFM strategy the gate number

increases about a 50%, this increase in the number of gates will strongly impact the

chip area and power consumption.

The power consumption of the digital modulator was estimated by enabling and

disabling the clock when the circuit is biased with a 3.3V voltage source. In the

graphic from figure 3.21(a) the power consumption is plotted for different sampling

clock references; the curve presents a linear behavior of power consumption (for digital

circuits the dynamic power consumption has a linear relationship with frequency).

Even designed for 25Mhz of operation, the circuits operates as a digital Σ∆ modulator

up to 80Mhz, beyond this range of frequencies there is still digital signal switching

but there are erroneous data and the noise floor increases. Table 3.3 presents the

characteristics of the fabricated digital Σ∆ modulator.


2 4 6 8 10 12

x 107

0

5

10

15

20

25

30

Frequency (Hz)

Pow

er (

mW

)

(a) Dynamic power consumption . (b) Waveforms from oscilloscope.

Figure 3.21: Experimental results

3.6 Application in a Fractional Frequency Synthe-

sizer.

A fractional synthesizer using this Digital Σ∆ modulator architecture was simulated

to explore the spur tones disabling. The behavioral simulations where done with the

simulation methodology presented in Chapter 2.

Figure 3.22(a) shows the synthesizer’s output phase noise when no dither is added.

The power spectral density was obtained from a 224 sample sequence using a windowed

method and compared to a analytical prediction. Around the region where the Σ∆

modulator dominates the output phase noise it can be seen how the spur tones degrade

the phase noise up to +20dB. When the dither generator is activated the spur tones

are well disabled as shown in figure 3.22(b). In the same figure the output Phase-Noise

for an ideal dithered signal (simulated with an ideal wide band white noise source)

is plotted to demonstrate that the simple 8-bit LFSR is enough to randomize the

fractional synthesizer. This is thanks to the proposed way to add the dither signal.

82 3.7. Remarks

(a) Phase-Noise without dither. (b) Phase-Noise with dither.

Figure 3.22: Simulation results

3.7 Remarks

It has been demonstrated that a simple M -bit LFSR in a M -bit MASH architec-

ture reduces the spur tones magnitude as effectively as more complicated state of the

art MASH spur reduction techniques. The theoretical study on this paper also used

the state of the art theory on maximum sequence length MASH modulators [30], to

demonstrate that increasing the size of a LFSR as much as possible will not improve

the spur tones reduction; if the dither signal is added in a path which totally shapes

the dither signal.

The explored paths, to add the dither signal, make the quantization noise to

increase for low frequency values but this components are filtered by the fractional

synthesizer. Therefore, the simple M -bit LFSR dither signal makes possible to barely

increase the MASH modulators number of gates and though the circuit cost. Another

advantage is that the signal transfer function is not affected by the simple dither

addition and there is not a necessity to filter the signal from the MASH modulator

when the fractional synthesizer is not used with a constant DC output signal.

Chapter 4

Design of the main blocks for the

Fractional Synthesizer.

4.1 Introduction.

As it was mentioned in the previous chapters, the Σ∆ fractional frequency synthesizer

is build by a Phase Locked Loop PLL network having a programable frequency divider

(figure 4.1). The output frequency is an entire value N plus a fraction K/2m.

PFD CP LPF

N..(N+15)

VCO

+I cp

-I cp

Sigma-Delta

N+K

F out

F ref

4 3 3 4 2

Programable Divider

Y

m-bit

4-bit

Figure 4.1: PLL based Σ∆ fractional synthesizer.

83

84 4.1. Introduction.

Both the entire (N) and fractional (K/2m) values are input words for the m-

bit digital Σ∆ modulator who modulates the value K to control the word Y at the

input of the programable divider. The design of the fractional frequency synthesizer

blocks is focused to have a maximal output frequency range in the Voltage Controlled

Oscillator, a low phase-noise figure and low power consumption.

The frequency domain model used in chapter 2 is very helpful to design the frac-

tional synthesizer to avoid instability and prevent in this way the non-lock of the

system. The linearized model of the fractional synthesizer is repeated in figure 4.2

for the convenience of the reader.

VCO

Figure 4.2: Frequency domain model for the fractional frequency synthesizer.

The phase transfer function can be calculated by observing the open loop gain:

A(f) = αTs

2πIcpHlpf (f)

KV CO

jf

1

Ts

1

N(4.1)

The closed loop phase transfer function is then:

φout(f)

φref (f)= G(f) =

NTsA(f)

NTs + A(f)(4.2)

Each one of the terms in the phase transfer function can be identified: α Ts

2πIcp is

the PFD-CP transfer function, Hlpf (f) is the loop filter current to voltage transfer

function, KV CO

jfis the VCO contribution and N is the instantaneous division value.

Ts is the sampling frequency that the PDF uses to estimate the difference between

the reference signal and the divided one. This approximation is valid as long as the

loop filter cut-off frequency is much lower than the reference frequency [14]. To know

4. Design of the main blocks for the Fractional Synthesizer. 85

each one of the parameters used in this model to explore the frequency response of

the phase locked loop it is necessary to establish a design sequence.

The Voltage Controlled Oscillator (VCO) is probably the element with more re-

strictions in the frequency synthesizer because it defines the tuning range and the

KV CO gain being an important parameter for the design. Besides, the VCO along

with the frequency divider are the most power consuming circuits in the frequency

synthesizer. The other parameters such as Charge-Pump current, cut-off frequency

for the low pas filter and reference frequency can be moved a bit more easy to reach a

trade-off in the design. In this chapter the design considerations for the fractional syn-

thesizer blocks are presented starting from the VCO and the programable frequency

divider. Once the parameters on the last mentioned blocks are known it is possible

to complete the fractional synthesizer design with the frequency domain model.

4.2 The Voltage Controlled Oscillator.

A Voltage Controlled Oscillator VCO is a circuit whose output is a periodic time

varying signal having a semi-square or close to sinusoidal shape. The CMOS circuits

bandwidth-limitations and the non-linear behavior for most VCO architectures make

too much common the close-to-sine wave signal.

The VCO is a feedback circuit whose closed loop transfer function makes possible

to amplify its own noise in a controlled form up to a stable oscillation state. The

VCO can be modelled as a two port network H(s) feeded back with G(s) as shown

in figure 4.3.

The closed loop transfer function is given by:

Vout(s)

Vin(s)=

H(s)

1 − G(s)H(s)(4.3)

The circuit oscillates when the denominator of this transfer function is zero and

the open loop gain is enough to maintain the poles in the imaginary axis of the

root-locus plane. The situation can be resumed in the Barkhausen’s criteria.

86 4.2. The Voltage Controlled Oscillator.

H(s)

G(s)

Figure 4.3: VCO feedback block diagram.

|G(jω0)||H(jω0)| = 1 (4.4)

∠(G(jω0)) + ∠(H(jω0)) = 0 (4.5)

There are several techniques to reach the Barkhausen’s criteria in a CMOS circuit.

The feedback of active circuits such as ring oscillators and one cell active oscillators

consume low power but their phase-noise behavior is poor [37]. On the other hand the

LC-tank based VCO’s consume much more power but they oscillate to a much higher

frequency and their phase noise behavior is better [38]. The fractional frequency

synthesizers are frequently used for applications needing a high spectral purity and

this is the main reason a LC-tank based VCO is used for the fractional synthesizer

design in this thesis.

4.2.1 LC-Tank VCO.

Ideally a lossless passive resonator oscillates with a frequency ω0 = 1/√

LC. Never-

theless, the parasitic resistance due to the inductor material and the capacitor makes a

lossless LC-Tank impossible. If the tank looses are compensated by an active network

and if the Barkhausens’s criteria are accomplished, the network will oscillate.

A LC-Tank based VCO consist on a passive resonator network whose energy looses

are compensated by an active network giving a negative resistance. This basic concept

can be modelled as shown in figure 4.4(a) where the LC-tank looses can be modelled

with a resistor Rp.


Active Network Passive Network

H(s) G(s)

(a) Circuit description

H(s)

G(s)

V x I x

(b) Transfer function

Figure 4.4: Compensated LC-tank.

In figure 4.4(a) it is important to notice a limit for the closed loop gain (gmRp),

when the tank looses are compensated. If it is very high, the VCO will behave

in an unstable fashion making the active circuit to saturate and eventually prevent

oscillation. So, loop gain must be greater than 1 to start-up the oscillation but not

to far away from this value in order to ensure stable oscillation. As a rule of thumb

a typical value for the loop gain is about 2 and 3.

4.2.2 Crossed coupled differential pair.

One active circuit having a negative resistance (supplying current) is the crossed cou-

ple differential pair shown in figure 4.5(a). The small signal model for the differential

crossed coupled pair is shown in figure 4.5(b).

V x

M 1 M 2

I b

(a) Crossed coupled transistors

g m1 (V x )

C1 C2

Vx

Ix

g m2 (-V x )

(b) Small signal model

Figure 4.5: Crossed coupled differential pair.


If it is assumed the two cross coupled transistors are identical that is gm1 = gm1 =

gm and so the parasitic capacitances C1 = C2 = C; the current to voltage transfer

function can be calculated as:

Vx(s)

Ix(s)= − 1

gm

(4.6)

If a crossed coupled differential pair is designed to compensate the LC-tank looses

the differential pair transconductance must be gm ≥ Rp and the network oscillates.

The cross coupled LC-tank VCO can be designed with a N-MOS or a PMOS archi-

tecture as in figure 4.6(a) and 4.6(b).

M1 M2

V c L L

C C Ib out p out n

(a) With NMOS pair.

Ib

Vc L L C C

M1 M2

out p out n

(b) With PMOS pair

Figure 4.6: LC-tank based CMOS VCO’s.

4.2.3 Noise in the VCO (NMOS or PMOS?)

As the crossed coupled VCO can be realized as NMOS or PMOS cross coupled pair

it is necessary to establish the design criteria to make a chose between the topologies.

The noise behavior is explored with the help of figures 4.7(a) and 4.7(b).

The thermal contribution of noise is manly due to the MOS transistors and the

resistance in the LC tank. For simplicity the flicker noise in MOS transistors is

neglected in the analysis but it can be significant for very low frequencies offset from

the carrier. In figure 4.7(a) the noise sources are modelled as noise current sources


with a value I2n,m = 4kTγgm for the MOS transistors and I2

n,r = 4kT/Rp for the

LC-tank resistance. The Boltzman constant k and temperature factor T well known

values but the factor γ is a process dependent value.

M 1 M 2

4kTg m1 4kTg m2

R p

4kT/R p

(a) Main noise sources

g m V x

R p

-g m V x

I n 2

V x

C C

(b) Model for noise analysis.

Figure 4.7: Cross coupled pair noise analysis

Supposing the transconductances on the differential pair are similar and as the

noise current sources are uncorrelated they can be modelled as a single noise source

I2n = I2

n,m + I2n,r in the one port network modelling the VCO in figure 4.7(b). With

this model the noise in the VCO can be calculated as:

V 2n,out (ω) =

R2p

(1 + gmRp)2

(4kT

Rp

+ 4kTγgm

)(4.7)

From equation 4.7 it can be seen that in order to reduce the noise in the VCO the

parasitic resistance must be as low as possible and the cross coupled pair transcon-

ductance must be high. Therefore, at a first glance the NMOS topology can be a

good choice. Nevertheless, in equation 4.7 the flicker noise contribution is neglected

and it is much more significant at low frequencies offset from the carrier. To reduce

the flicker noise contribution the PMOS differential pair is preferred [39]. Besides

the PMOS transistors have a better behavior for the transconductance degradation

factor. With this encountered design consideration the election of the cross coupled

VCO depends on the process used for the design and also the frequency tuning range

can be crucial on this task as will be discussed in the next sections.


4.2.4 Monolithic inductors in CMOS technology.

The integration of inductors in a CMOS process is possible by using several design

considerations to reduce as much as possible the parasitics effects like metal resistance,

substrate looses and mutual inductances due to eddy currents in the substrate [40].

The design of integrated inductors is still an active research field and is beyond the

scope of this work. To design a LC-tank based VCO the inductors library available

in the AMS CMOS 0.35µm Europractice process was used for this thesis work.

(a) Metal-4 inductor.

C p

L s R s

C ox1 C ox2

C s1 C s2 R s2 R s1

P 1 P 2

subs

(b) High frequency model.

Figure 4.8: Integrated inductor in 0.35µm process.

Figure 4.8(a) and 4.8(b) show the layout and simplified model of an inductor in

the AMS 0.35µm process used for the design. The complex impedance of the inductor

can be obtained from the S-parameters or the Smith chart given by the manufacturer.

The main parameters for the used inductor are summarized in table 4.1.

Table 4.1: CMOS process inductor model parameters.

Area = (300µm)2 [email protected] = 9.98nH Q @ 2.4 GHz = 3.3 Turns = 7

Width = 15µm Ls@5GHz = 12.7nH Q @ 5 GHz = 2.5 Rs = 49Ω


4.2.5 Increasing the linear tuning range in the VCO.

The Voltage Controlled Oscillator tuning range is rather limited due to the non-

linearity that the varactors present. The varactors can be implemented in a CMOS

process with minimum-length PMOS transistors to get a high Q (see figure 4.9);

the drain and source are tied together to control the substrate-drain/substrate-source

capacitances [41]. In this section the limited tuning range for this varactors is explored

with the analysis of a PMOS architecture but the results can be extrapolated to a

NMOS architecture.

Ib

Vc L L

C C

M1 M2

out p out n

V DD

V ss

M3

Figure 4.9: CMOS VCO with NMOS as varactors.

In figure 4.9 the (|Vgs)| − Vt) value in the crossed coupled pair determines the

output signal’s amplitude and offset DC value. This DC value and the control voltage

Vc also determine the range where the varactors operate. In an ideal scenario, when

the control voltage makes the MOS varactors to operate in the linear range for a deep

inverted channel, the reverse-biased diodes in the source/drain-nwell interface behave

as the varactors. The total capacitance in the MOS varactors can be estimated with

the help of the model in figure 4.10(a). When the transistor is in linear region the

capacitances are:


Cgs = WCovl +1

2WLCox (4.8)

Cgd = WCovl +1

2WLCox (4.9)

Csb = WECj + 2(W + E)Cjsw (4.10)

Cdb = WECj + 2(W + E)Cjsw (4.11)

Cgb = 0 (4.12)

c gs

c sb

c gd

c db

c gch

c cb

g

s d

b (a) MOS capacitances model.

0 0.5 1 1.5 2 2.5 34

4.5

5

5.5

6

6.5

7x 10

−13

Reverse Voltage (V)

Cap

acita

nce

(F)

Capacitance in triode

(b) MOS capacitance for linear region

Figure 4.10: MOS capacitances in transistors used as varactors.

The overlap capacitance per unit length (Covl) and oxide capacitance per unit

area (Cox) are process dependent values but the junction capacitances Cj and Cjsw

are also dependent of the reverse diode voltage Vr.

Cj =Cj0(

1 + Vr

φB

)mb(4.13)

Cjsw =Cjsw0(

1 + Vr

φB

)mb(4.14)


Figure 4.10(b) shows the total MOS capacitance as a function of the reverse-

biased diodes in the surce/drain-bulk junction for the linear range operation of a

MOS transistor with L = 0.35µm and W = 500µm. Even when the channel is in

this deep inversion condition, the total output capacitance is a non-linear function

of the reverse bias voltage (Vr). In this case the charge in the channel makes the

channel-to-bulk capacitance to be nearly zero and the total capacitance is a strong

function of the reverse voltage in the drain/source-bulk diode.

Another case comes as the control voltage Vc is closer to the offset output DC value

in the VCO (Voutp,n). The MOS varactors begin to turn off and the total capacitance is

a weaker function of the reverse voltage Vr. When the MOS varactor has a (Vd = Vs)

and the channel is in weak inversion the capacitances in the model of figure 4.10(a)

can be approximated as:

Cgs = WCovl (4.15)

Cgd = WCovl (4.16)

Csb = WECj + 2(W + E)Cjsw (4.17)

Cdb = WECj + 2(W + E)Cjsw (4.18)

Cgb =WLCoxWLCdep

WLCox + WLCdep

(4.19)

Now the channel-to-bulk capacitance Ccb is a series combination of the gate oxide

capacitance an the channel depletion capacitance WLCdep. This capacitance is also

dependent on the Vgs value at the MOS transistor [42]. In this range of operation

the MOS capacitance has a much weak dependence on the reverse voltage Vr as is

illustrated in figure 4.11. The MOS capacitance has its minimum value and it barely

changes as the reverse voltage Vr does; as the transistor enters in the accumulation

region the capacitance maintains this minimum value because the high frequency

signals in the gate avoid to raise the value up to Cox.

From this previous discussion it can be concluded that depending on the Vgs value

in the cross coupled pair, the MOS varactor enters in the depletion/accumulation


0 0.5 1 1.5 2 2.5 32

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7x 10

−13

Reverse Voltage (V)

Cap

acita

nce

(F)

Capacitance in triodeCapacitance in depletion, acucmulation

Figure 4.11: Comparison of MOS capacitance when in depletion and triode.

range for a wide or short range of the control voltage. For instance figure 4.12 shows

the voltage range where PMOS transistors used as varactor are in the triode region

and the capacitance can change in a more linear characteristic. If the DC offset value

given by the VDSM3 in figure 4.9 is close to Vdd

2(as conventionally used) a PMOS

varactor will be in the triode region for a shorter range than if the DC value is close

to the most negative rail (right side on figure 4.12).

off

Vdd

Vss

V dsM3

V thp

Vdd

Vss

V dsM3

V thp

L i n e

a r

T u n

i n g

R a n

g e

Proposed scheme. Conventional range

depletion

triode

off

triode

depletion

L i n e

a r

T u n

i n g

R a n

g e

Figure 4.12: Comparison of linear ranges for a PMOS varactor.

This simple design consideration is traduced in a more linearized range for the

voltage to frequency transfer function in the VCO. In order to increase an linearize

the tuning range in a PMOS cross coupled VCO it is desirable to design the VCO’s


output DC value as close to the most negative rail as possible. This can be done by

using a current source with a very low Vds value and a high Vgs value in the crossed

coupled pair.

Figure shows a comparison of the transfer curves of a PMOS cross coupled VCO

with minimum length PMOS transistors used as varactors of a transistor level simula-

tion in the 0.35µm CMOS process. It is clear how not only the transfer curve with the

DC output value closer to the most negative rail has a more linear transference but

also the output frequencies are higher. The reason for this effect is that the PMOS

cross coupled pair needs a low W/L characteristic to raise the Vgs value which also

reduces the parasitic capacitance. The drawback in this case is the necessity of a low

Vds value in the current source transistors that turns complicated in some cases.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.81.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3x 10

9

Control Voltage (V)

VC

O O

utpu

t Fre

quen

cy

Clasic VCOVCO with low DC output.

Figure 4.13: VCO tuning range for different output offset DC value.

4.2.6 VCO non-linear analysis.

In the design of the LC-tank VCO a PMOS crossed coupled pair in figure 4.14 has

been chosen because the cross-coupled differential pair and the PMOS varactors can

be isolated with different N-Wells. Also, the output DC value can be designed more

easily to be close to the most negative rail because the NMOS have a much lower


threshold voltage. The low output DC values not only increases the linear tuning

range in the voltage-to-frequency transference but also it has some consequences in

the signal’s distortion.

Ib

Vc L L

C C

M1 M2

out p out n

V DD

V ss

M3

Figure 4.14: VCO with PMOS varactors.

Supposing that the output DC value in figure 4.14 (Voutp,n) is close to the most

negative rail and that the output amplitude is limited; the PMOS crossed coupled

pair is in saturation in the complete output cycle of the VCO. With this condition

the instantaneous Vgs in the cross coupled pair is Voutp,n − Vdd + A cos(ωot) and the

drain current can be expressed as:

ID = 2KpWL

(Voutp,n − Vdd + A cos ωot − Vt)2

(1 + λ (Voutp,n − Vdd + A cos ωot)) (4.20)

This drain current can also be expressed as a Fourier series:

ID(t) = i0 +∞∑

k=1

ik cos nθ (4.21)

The nonlinear term in the right side of the drain current expression 4.20 makes

the Fourier coefficients to change as the DC value (Voutp,n) in the output node varies

and they are shown in table 4.2. The fourier coefficients where estimated for a Kp =


Table 4.2: Id First Fourier coefficients

Voutp,n i0 i1 i2

0.5Vdd 18.5 · 10−3 −6.8 · 10−3 8.5 · 10−3

0.25Vdd 31.6 · 10−3 −22.2 · 10−3 8.5 · 10−3

0.125Vdd 43.4 · 10−3 −29.9 · 10−3 8.5 · 10−3

60µA/V , V t = −0.7V , (W/L) = 200µm/0.35µm. The absolute difference between

the first and second term changes significatively. It is also demonstrated in a time

domain approximation in figure 4.15, how the amplitude of some of the harmonics is

reduced when the output DC value is closer to the most negative rail.

0 0.5 1 1.5 2

x 10−9

−0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

Time (s)

Dra

in c

urre

nt Id

(A

)

Voutp,n=0.5VddVoutp,n=0.25VddVoutp,n=0.125Vdd

Figure 4.15: Drain current as the DC value changes.

The reduction in the amplitude harmonics for the drain current in the cross cou-

pled transistors traduces in an amplitude reduction for the output voltage harmonics.

This makes the output signal from the VCO to have a better behavior for the total

harmonic distortion and the output signal is more pure.


4.2.7 VCO silicon implementation.

Taking into account the design considerations developed in the last two subsections

a PMOS cross coupled VCO was designed in the 0.35µm 4-metal CMOS process. A

RF-MOS transistor model is used to obtain accurate results during the design; this

RF models are valid within the frequency range from (1 − 3)GHz. The equations

derived previously in this section help to design the VCO from a first order approach

but the transistor level simulations are much accurate since the RF models take into

account superior order effects in the devices.

Vc L L

C C

M1 M2

out p out n

V DD

V ss

M3 M4

M5

M6 M7 M8

Mb1 Mb2

Rb1 Rb2 PAD PAD

outn b outp b

Figure 4.16: Schematic view of the VCO.

The schematic view of the VCO is shown in figure 4.16. From table 4.1 the

parasitic resistance of the inductor is Rs ≈ 49Ω so the transconductance of the cross

coupled differential must be gm ≈ 1Rp

≈ 20mA/V . It is necessary to mention that

in order to increase the VCO tuning range, the size of the PMOS should not be

excessive. Besides in the HIT-Kit V-3.70 from Austriamicrosystems the RF PMOS

cross coupled pair transistors cannot be bigger than 150µm. Therefore, with this

restriction it necessary to design the tail current in the VCO in the order of 2mA.

The current source for this VCO is a simple current mirror with a flipped-voltage

cell which gives the necessary Vds4 value to reach the 2mA values in the current

source. Also the Vds3 is designed to be equal to 0.2V to increase the tuning range an

to improve the linearity in the VCO output as it is proposed in the previous sections.


Table 4.3: Size of transistors in the VCOTransistor W/L (µm/µm) Transistor W/L (µm/µm)

M1,M2 150/0.35 M3 2000/2

M4 200/2 M5,M6 500/2

M7,M8 120/0.35 Mb1,Mb2 90/0.35

Rb1,Rb2 125Ω Vdd 3.3V

In order to characterize experimentally the VCO, an output stage was designed to

drive an output pad. The output stage is a common source stage with transistors

Mb1,Mb1 and resistors Rb1, Rb2 which behave better than a source follower for the

range of frequencies needed. An active probe is positioned in this internal pads to

make the on-die measurements. The sizes of the MOS transistors for the VCO are

presented in table 4.3.

4.2.8 Simulation results.

The designed VCO was simulated in the Mentor Graphics Design Flow. The layout

of the VCO is shown in figure 4.17.

Figure 4.17: Layout view of the VCO.

The analog buffers (driving the analog pads) can be seen at the upper part of the

layout. They have a 0.8V/V voltage gain up to the highest VCO frequency operation.


(a) Transient VCO output nodes (b) Transient buffer output nodes

Figure 4.18: Post-Layout simulations of the VCO for Typical Mean, Worst Speed andWorst Power cases.

Figure 4.18(a) shows the VCO output signal of a post-layout simulation with

typical mean (TM ), worst case power (WP) and worst case speed (WS ) cases. Fig-

ure 4.18(b) shows the output from the buffers when loaded by the pads for the previ-

ously mentioned cases. Although not presented in the graphics to avoid a misunder-

standing of the graphs all the worst case corners where simulated and the circuit works

for all of them. The output from the buffers is a level-shifted signal with the same

frequency as the output from the VCO. The voltage to frequency transference curve

for the Typical Mean, Worst Power and Worst Speed cases is shown in figure 4.19(a)

where the KV CO ≈ −65MHz/V for all cases. The output frequency changes for

the corner cases but the KV CO keeps constant which ensures stability in the PLL,

the first stage of the frequency divider must be designed to operate for all the corner

cases when the VCO changes its tuning range. This negative VCO transfer curve

must be compensated in the fractional synthesizer with a negative transfer function

in the loop filter to avoid instability. Also a temperature variation dependence was

simulated to verify the circuit performance of the VCO in a range from (0 − 120)C


(a) Corner cases simulations (b) Corner cases

Figure 4.19: VCO voltage to frequency transference curves.

Table 4.4: VCO characteristicsSize (including I/O pads) (400 × 1015) (µm)2 Vdd 3.3V

Power (without pads) 86mW Power (with pads) 130mW

Tuning Range (typical mean) (1.54 − 1.69)GHz Voltage tuning (0 − 3.3)V

for the four corner cases. Figure 4.19(b) shows only the voltage-to-frequency transfer

curve of the Typical Mean case at 27C but the circuit worked for all cases.

4.2.9 Experimental results.

The VCO was designed with the constraints developed in the last subsection. It was

manufactured in the AMS 0.35µm CMOS process via Europractice with the spirals

supported by the manufacturer, as explained previously. The microphotograph of

the VCO is shown in figure 4.20. An analog buffer was designed to make the VCO

able to drive the internal pads in the chip. This internal pads allow to make on die

measurements of the VCO.

One analog pad was used in the chip to tune the VCO with a constant voltage.

This DC voltage was swept to obtain the voltage-to-transfer characteristic of the VCO.

102 4.3. The Programable Frequency Divider

S p i r a l s

B u f f e r a n d P a d

A c t i v e c i r c u i t

Figure 4.20: Voltage Controlled Oscillator.

The measured tuning range is shown in figure 4.21. Table 4.4 shows the characteristics

of the VCO where it can be seen that the power consumption can be incremented by

the pads in the chip.

0 0.5 1 1.5 2 2.5 31.45

1.5

1.55

1.6

1.65

1.7

1.75x 10

9

Control voltage (V)

Out

put f

requ

ency

(Hz)

MeasuredTypical mean simulation

Figure 4.21: Voltage Controlled Oscillator transfer curve .

4.3 The Programable Frequency Divider

The programable frequency divider is designed with the phase selection technique

[43], [6]. To explain how this technique works the basic idea is presented in figure 4.22


for a dual modulus divider.

Phase Select

Control

F out

F 2q

F 2qn

F 4q

F 4i

F 4qn

F 4in

M

F in

Mux 4-1

F 4 2 2 16

From VCO

To PFD

Figure 4.22: Dual Modulus Divider.

In this case the high frequency signal from the VCO is divided repeatedly by 2

to get 4 signals with a frequency Fvco/4 and phase-shifted 90 (F4i, F4q, F4n, F4qn, see

figure 4.23). This phase shifted signals can be obtained with Flip-Flop based divide

by 2 cells connected as is shown in the figure. One 4 → 1 multiplexer (phase selector)

selects one of the four previously mentioned signals and its output is divided by 16.

A state machine gives the control value for the multiplexer to change between phases

for an entire cycle of the output signal Fout. This state machine can be a simple up-

counter going from 0 − 3 to select one phase at a time. In the case of figure 4.22 the

controller is activated by a NAND gate during one complete cycle of the output signal.

If the activation signal M is in high state (M = 1) the controller will not change the

selection on the multiplexer and the output frequency will be Fout = Fvco/64.

If the activation signal is in low state M = 0 then in the high to low transition of

the output signal (Fout) a count-up in the control machine will change the selection of

the signal. If the phase selection changes to the 90 delayed following signal (f4i → f4q,

for example) the output signal will complete the period 90 later, which is equivalent

to a complete cycle of the signal from the VCO, and the total division modulus will

be 65.

The figure 4.23 shows the concept of phase selection for the programable frequency

divider. Before t0 the multiplexer’s output signals follows the signal F4i but after this

time the multiplexer changes the selection to the phase F4q. This change in phase


F 4i

F 4q

F 4in

F 4qn

F 4

t 0

F vco

Figure 4.23: Phase selection concept for the programable divider.

represents a miscount of an entire period of the VCO signal. With this concept the

programable divider can change the modulus division between N, (N + 1).

4.3.1 The multi-modulus programable divider.

The basic phase selection concept explained in last subsection can be extended to

achieve a multi-modulus programable frequency divider. If during an entire cycle of

the programable divider’s output (Fout), the multiplexer changes 2M times the phase

to the following 90 delayed signal; the total division modulus will be N + 2M .

Phase Select

Control

F out

F 2q

F 2qn

F 4q

F 4i

F 4qn

F 4in

M

F in

Mux 4-1

F 4 2 2 16

From VCO

To PFD

F 8 F 16 F 32 F 64 F 4 4-bit

Figure 4.24: Phase selection for the multi-modulus divider.


f 16b

m 1 f 8b

f 32b f 64b f 4b

f 16b

m 2 f 8b

f 32 f 4b

f 16b

m 4 f 8b

f 4b

m 8 f 8 f 4b

(a) Phase select logic

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

f 4

f 8

f 16

f 32

f out,64

pulse 1

pulse

f 4i f 4q f 4in f 4qn f 4i f 4q f 4in f 4qn f 4i f 4q f 4in f 4qn f 4i f 4q f 4in f 4qn

(b) Waveforms

Figure 4.25: Programable frequency divider logic .

Figure 4.24 explains graphically this concept. If the multiplexer’s output is divided

four times by 2, the signals: F8, F16, F32, F64 are obtained (the signals are labelled as

the frequency division factor regarding to the VCO frequency). This generated signals

can be used together with a M bits digital word to control a logic circuit which can

generate up to (2M −1) pulses along the entire period of the output signal Fout ≡ F64.

For instance if the M control signal is of 4-bits size then the phase selection logic can

generate 15 pulses in an entire period of the output (Fout) and the frequency division

modulus can be programmed to be from N to N + 15 as shown in figure 4.25(b).

The logic circuit used for the pulse generation is shown in figure 4.25(a) where the

complementary signals can be obtained if the divide by 2 circuits are designed in

a differential architecture. The drawback of this phase selection technique is the

possible glitches at the output of the phase selector which can yield a total erroneous

division factor.

4.3.2 The glitch-free design consideration.

The phase selection technique has as a drawback the glitch generation. This is because

the phase selection cannot be realized in a smooth fashion if the following phases have

a different logic values at the switching moment. Besides with the temperature and


process variations the digital circuits cannot be designed to ensure a switching time

to avoid the glitches.

F 4i

F 4q

F 4

t s

(a) Smooth phase-switching

F 4i

F 4q

F 4

t s

(b) Glitch in phase selection

Figure 4.26: Glitch generation.

In order to make a phase-switching in a smooth form the phase selection must be

done when the logic values for both following phases is the same. This situation is

presented in figure 4.26(a) where in time ts the phase-switching is realized when the

signals F4i, F4q have the same logic state. On the other hand if the phase selection

occurs when the signals have different logic values as in figure 4.26(b) a glitch is

generated. This glitch in the output signal can lead to an undesired trigger in a

division cell and therefore an erroneous total division modulus factor in the circuit.

The glitch in the phase selection technique can be avoided if the signals at the

phase selector’s input are arranged in such a way that the phase change is done

smoothly [44]. In this phase-selection glitch free technique not only the phases are

arranged but also the frequency of this signals is lowered and the total division factor

is reduced. The multi-modulus frequency divider in [44] is very similar to the one in

figure 4.24 and their phases are compared in figure 4.27.

In the glitch-free technique (see figure 4.27(a)) the phases just changed positions

to make the phase transitions smoothly; if before time t1 the output signal follows F4i

then the phase can change to the following −90 signal F4qn without a glitch hazard

up to the time t1 + tx. This can be accomplished if for the traditional programable


F 4i

F 4qn

t 1 t 1 +t x

F 4

(a) Glitch-Free technique

F 4i

F 4q

t 1 t 1 +t x

F 4

(b) Conventional phase selection

Figure 4.27: Phase arrangements comparison and their time scheme for smooth tran-sitions.

divider the phase selection is made with a cunt-down instead of a count-up of the

control logic (see figure 4.24). The disadvantage of this technique is the reduction on

the limit frequency of operation for the phase selector (multiplexer) because if the

phase selection is done after t1 + tx there will be an erroneous division factor. This

disadvantage is alleviated by reducing the frequency of operations of the signals a the

multiplexer’s input but the total division modulus range is changed [44]. Therefore,

the reference frequency in the Fractional Frequency Synthesizer should be also lowered

which makes harder the frequency synthesizer loop-filter design.

The phase selection arrangement in figure 4.27(b) is more hazardous to the glitch

generation because it has two times more probability to generate a glitch than the

glitch-free technique (see the crosses over the hazardous times). This is true if the

phase selector (multiplexer) is very fast to change the logic state when both following

signals (F4i, Fqi) have different logic values. So if the phase selector is designed to

be slower to avoid the glitch during the hazardous times the glitches are avoided.

This can be possible because the normal phase arrangement has a greater frequency

limit of operation because if the phase switching is done after t1 + tx there is no a

pulse miscount as in the case of figure 4.27(a). All this restrictions have been taken

into account for the programable divider design in this thesis and the selected phase

arrangement is the shown in figure 4.27(b).


4.3.3 The high frequency division cells

The programable frequency divider is presented again in figure 4.28 for convenience

of the reader. From this figure it can be seen that the signal from the VCO passes

through a first divide by 2 cell. This circuit is the one operating at the highest

frequency of operation and it was designed as fully differential architecture based on

a master-slave flip-flop.

Phase Select

Control

F out

F 2q

F 2qn

F 4q

F 4i

F 4qn

F 4in

M

F in

Mux 4-1

F 4 2 2 16

From VCO

To PFD

F 8 F 16 F 32 F 64 F 4 4-bit

Figure 4.28: Multi-modulus programable divider.

M1 M2

M3 M4

M5

M1P M2P

M3P M4P

M5P in n in p

out p

out n

Figure 4.29: High Frequency divide by 2 cell schematic.

The schematic view of the high frequency divide by 2 cell is shown in figure 4.29.

As this cell has positive feedback, it is very difficult to use a closed form expression

for the design but a qualitative analysis can yield some design considerations for

this cell. The transistors M5,M5P are the ones giving the necessary strength for the

pull-down/up in the flip-flops and their transconductance value must be high. The

transistors M1,M1P and M3,M3P give the necessary feedback for the circuit to work

as a high frequency latch and the transistors must be designed to have little intrinsic


Table 4.5: Size of transistors in the High Frequency divide by 2 cell

Transistor W/L (µm/µm) Transistor W/L (µm/µm)

M1, M1P, M2, M2P 10/0.35 M3,M3P,M4,M4P 15/0.35

M5,M5P 60/0.35 Vdd 3.3V

capacitance in order to reduce the load. As the transistors M1,M1P ,M2,M2P give

the positive feedback to the latch cells they are a little bit smaller than transistors

M3,M3P ,M4,M4P . The W/L values of the transistors are shown in table.

The layout cell is shown in figure 4.30 where a symmetric structure is used to

reduce the mismatch between the transistors and the process variations. The cross

coupled pairs have also a feedback and the routing was done only with metal 1 and

poly to reduce the mismatch in the cells.

Figure 4.30: High Frequency divide by 2 cell layout view.

Figure 4.31 shows the typical mean (TM), worst case power (WP) and worst

speed (WS) post layout simulations of the divide by 2 cell with the VCO included in

the layout. The worst ones an zeroes simulations and temperature variations where

also run but they are not shown here to avoid a confusion in the waveforms. The

simulation results ensure a proper divide by 2 operation of the signal from the VCO

for all the corner cases and the temperature variations.


(a) VCO output waveforms (b) Divide by to output waveforms

Figure 4.31: Post-Layout simulations of the Divide by 2 circuit for Typical Mean,Worst Speed and Worst Power cases.

4.3.4 The medium frequency divide by 2 cells

The medium frequency divide by 2 cell is similar to the high frequency divide by 2

cell and is shown in figure 4.32(a).

M1 M2

M3 M4

M5

M1P M2P

M3P M4P

M5P in n in p

F4 i

F4 q F4 in F4 qn

(a) MF divide by 2 cell

inp

inn

outp

outn

(b) Signal Booster.

Figure 4.32: Schematic view for the MF divide by to cell and the signal boos circuits.

The proposed medium frequency divide by two circuit also takes the advan-

tage from the master-slave latch architecture to obtain the 4, 90 delayed signals

(F4i, F4q, F4in, F4qn) as can be seen in the schematic view. The design is also very

similar but in this case the master slave flip-flop can be optimized to the medium


Table 4.6: Size of transistors in the High Frequency divide by 2 cell

Transistor W/L (µm/µm) Transistor W/L (µm/µm)

M1, M1P, M2, M2P 20/0.35 M3,M3P,M4,M4P 15/0.35

M5,M5P 30/0.35 PMOS(inv,boost) 3.6/0.35

NMOS(inv,boost) 2.1/0.35 PMOS(buff-chain) 3.6/0.35,10.4/0.35

NMOS(buff-chain) 2.1/0.35,5.4/0.35 Vdd 3.3V

frequencies of operation. In this case the transistors in the crossed coupled pairs are

a little bit wider than the transistors M3,M3P,M4,M4P. The transistors M5,M5P are

narrower than in the high frequency case.

As the signals from the MF divide by 2 cell have very smooth transitions, a

signal boosting circuit is used to obtain the 4 signals F4i, F4q, F4in, F4qn. After the

boosting stage, the signals have the necessary strength to drive the phase-selector in

the multi-modulus divider. The transistor sizes are shown in table 4.6.

Figure 4.33: Medium Frequency divide by 2 cell layout view.

Figure 4.33 shows the layout view of the MF divide by 2 cell with the boost

circuits. Figure 4.34 shows the post layout simulation results of the MF divide by 2

cell for the typical mean case. Also, in figure 4.34(b) the worst case speed post layout

simulation along with the VCO output signal is shown to illustrate the divide by 4

operation.


(a) Typical mean (b) Worst case speed

Figure 4.34: Post-Layout simulations of the Divide by 4 circuit.

4.3.5 Design for the process variation robustness.

The multi-modulus frequency divider was designed with the considerations developed

in the last subsections. With the glitch free design consideration the phase-selector

and the logic circuit, to control the phases, can be designed with more relaxed spec-

ifications. Therefore, the logic circuits were designed with static-logic digital gates.

Nevertheless, the process variations can increase or reduce the delay between the

gates and some glitches could appear.

Phase-Select Logic Circuit

/2 /2 /2 /2

D Q

Q

D Q

Q

D Q

Q

D Q

Q

Counter F4,F4b F8,F8b F16,F16b F32,F32b F64,F64b

Glitch Filter

Phase Select

F4i F4q F4in F4qn

Fout

Synchronization Network

Figure 4.35: Process variations unsensitive Phase-Select logic.


Figure 4.36: Layout of the programable divider.

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Vol

tage

(V

)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

Vol

tage

(V

)

Frequency : 25.561 MEGHz

Measurement Window

Measurement Window

Frequency : 1.6314 GHz

V(OUTN)V(OUTP)

V(S64BP)

75.0N 80.0N 85.0N 90.0N 95.0N 100.0N 105.0N 110.0N 115.0N

Time (s)

(a) Divide by 64

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Vol

tage

(V

)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Freq

uenc

y (G

Hz)

-0.20.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.23.4

Vol

tage

(V

)1.49157

1.64049

0.02075

0.00706

V(OUTN)

Frequency.2(V(OUTN))Frequency.2(V(S64BP))

V(S64BP)

120.0N 140.0N 160.0N 180.0N 200.0N 220.0N 240.0N 260.0N 280.0N 300.0N

Time (s)

C1: 234.90566N

(b) Divide by 79

Figure 4.37: Post-Layout simulations of the programable divider.

In order to make this digital circuit unsensitive to the fabrication process vari-

ations; the signals subsequently divided where passed through a latch chain as is

shown in figure 4.35. With the synchronization network, the divided signals F4 −F64

switch at the same time and the phase-select logic will change between pases with no

errors. The errors that the phase-select logic circuit were described previously in this

chapter.

Also, as a simple multiplexor is used as the phase selector; the process variations

can make the glitches to appear. In order to avoid them, the glitch filter shown in

figure 4.35 is used. This glitch filters consists on a inverter chain which threshold


level can be controlled to avoid the glitch generation.

The layout circuit of the multi-modulus frequency divider with division modulus

N = 64 − 79 is shown in figure 4.36. The layout includes: the phase selection logic,

the glitch filter, the synchronization network, the up-counter and multiplexer.

The transient simulations for the multi-modulus programable divider where real-

ized to ensure the circuit operation, for all worst cases. Also the programable divider

was simulated with the temperature variations to warrantee the good circuit perfor-

mance in any temperature range.

The transient simulations for the typical mean case are shown in figure 4.37.

The leftmost plot shows the signal from the VCO at 1.63GHz and the signal at the

programable divider’s output at 25.5MHz, that is a N = 64. The rightmost plot

shows the signal from the VCO at 1.64GHz and the output from the programable

divider is 20.7MHz, this represents a N = 79.

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Vol

tage

(V

)

0.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.2

Vol

tage

(V

)

-0.20.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.23.4

Vol

tage

(V

)



Measurement Window

V(OUTP)_1

V(S64)_1

V(P)_1

15.0N 20.0N 25.0N 30.0N 35.0N 40.0N 45.0N 50.0N 55.0N 60.0N 65.0N

Time (s)

(a) Divide by 64

-4.0-3.5-3.0-2.5-2.0-1.5

-1.0-0.50.00.51.0

1.52.02.53.03.5

Vol

tage

(V

)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Vol

tage

(V

)

-0.20.00.20.40.60.81.01.21.41.61.82.02.22.42.62.83.03.23.4

Vol

tage

(V

)


Measurement Window


Measurement Window

V(OUTP)_3

V(S64)_3

V(P)_3

45.0N 50.0N 55.0N 60.0N 65.0N 70.0N 75.0N 80.0N 85.0N 90.0N

Time (s)45.0N

(b) Divide by 79

Figure 4.38: Post-Layout simulations of the programable divider.

The transient simulations for the worst case speed and power are shown in fig-

ures 4.38(a), 4.38(b) respectively. For both cases the division modulus is N = 79;

in both plots the number of pulses generated by the phase-select-logic are shown to

demonstrate that the switching between phases is done smoothly.


4.3.6 Experimental Results of the Programable-Divider

The programable frequency divider was fabricated with the AMS 0.35µm CMOS

process via Europractice. The microphotograph of the multi-modulus programable

divider is shown in figure 4.39.

VCO

Programable Divider

HF and MF DIV /2

Figure 4.39: Microphotograph of the programable divider and the VCO.

Figure 4.40: Setup for the measurements.

The circuit on this figure includes the VCO, the high frequency divide by 2 cell,

the medium frequency divide by 2 circuit and the phase-select logic (used to select


the division modulus). The chip was prepared to change the control voltage at the

VCO input in order to tune the VCO. Also a 4-bit digital word is programmed as

the chip input to change the modulus from N = 64 − 79. A setup circuit in figure

was designed to characterize the Programable Frequency Divider. With this setup

the division modulus can be changed from N = (64 − 79).

(a) Divide by 64 (b) Divide by 79

Figure 4.41: Experimental results of the programable divider.

The experimental results are shown in the figure 4.41 from the capture of an

Agilent Oscilloscope. Also, in the plots, the output signal from the half frequency

circuit is shown. The plot in figure 4.41(a) shows the experimental results when the

VCO is tuned at 0V and the 4-bit digital input is in 0 (the multi modulus frequency

divider is at N = 64). In this conditions the phase-select logic us deactivated and

the division is surely N = 64. From this discussion the VCO output frequency

can be known if the programable divider’s output frequency is multiplied by 64.

In figure 4.41(a) it can be seen that the divide by 64 circuit output frequency is

f64 = 25.6MHz. Therefore, the VCO output frequency is 1.64GHz.

If the tuning voltage of the VCO is maintained at 0V , and so the VCO output

frequency is at 1.64GHz, the modulus division can be changed and the divider output

frequency will change. In figure 4.41(b) it is shown the output waveform from the

programable divider when N = 79. It can be seen that the frequency at the divider’s

output is now f79 = 20.7MHz which is congruent with the division modulus of

N = 79, for a VCO output frequency = 1.64GHz.


(a) Divide by 64 @ 3.3V (b) Divide by 79 @ 3.3V

Figure 4.42: Experimental results of the programable divider.

Table 4.7: Programable divider characteristicsSize (including I/O pads) (611 × 490) (µm)2 Vdd 3.3V

Prog. Div. power 130mW VCO power 86mW

Pads power 107mW Overall power 323mW

Programable range N = 64 − 79 Glitches NO

The programable divider was tested when the VCO was tuned at 3.3V . Fig-

ure 4.42(a) shows the case when N = 64 and the output frequency in this case is

f64 = 23.4MHz. The VCO output frequency is 64 ∗ 23.4MHz = 1.49GHz. When

the division modulus is programmed at N = 79, the expected output frequency is

f79 = 1.49GHz/79. Form the figure 4.42(b) the measured frequency is 18.9MHz it

match wells with the estimated frequency. Table 4.7 resumes the characteristics of

the programable divider. The power consumption is even more than the VCO and

both are the most power consuming circuits. The power consumption of the pads is

also significant but they are beyond of the scope of this thesis work.


Chapter 5

The frequency synthesizer loop

design.

5.1 Introduction.

The last chapter presented the methodologies to design the Voltage Controlled Os-

cillator (VCO) and the Frequency Divider. This circuits are crucial in the frequency

synthesizer design because their parameters cannot be easily designed, as discussed

before. It is more easy to re-design the parameters in the Phase-to-Frequency Detec-

tor (PFD), the Charge-Pump (CP) and the Low Pass Loop Filter (LPF ). Whit this

design parameters the frequency synthesizer can be designed to reach the phase-noise

specifications, the settling time and range of programmable frequencies; for instance.

In this chapter the design of the entire loop in the fractional frequency synthesizer

is presented. The design process starts with the mathematical model presented in

chapter 2. This mathematical model has a frequency domain part and a time domain

counterpart.

The frequency domain model [14], uses the input-to-output frequency transfer

function in the loop, to calculate the phase and gain in the synthesizer. With this

calculus a stability criteria can be applied to ensure the “lock‘” of the synthesizer.

This frequency domain model was programmed in MATLAB as a design tool.

119

120 5.2. Frequency domain design.

The time domain based model is the one used to make the behavioral models

proposed in this thesis work. The advantages of the behavioral models have been

presented in chapter 2.

After the mathematical models have been used to obtain the frequency synthesizer

parameters, each cell can be individually designed. Then, every transistor level cell

can be incorporated to the behavioral model to test its performance. Therefore, the

design process is a task between the transistor level design and behavioral model

simulation. Once all the frequency synthesizers cells are designed, a post-layout

simulation for the whole system must be done taking into account the worst cases to

ensure the integrated circuit function.

5.2 Frequency domain design.

The fractional frequency synthesizer model is shown in figure 5.1 again for convenience

of the reader.

cp I Loop filter H(f)

VCO

jf K v

1/T nom N

1

n[K]

S pfdcp (f) S lfvco (f)

Figure 5.1: Synthesizer’s equivalent frequency-domain model.

The open loop transfer function is:

A(f) = αTs

2πIcpHlpf (f)

KV CO

jf

1

Ts

1

N(5.1)

where Icp is the charge-pump current, Tsample is the period of the reference signal,

H(f) is the low pass filter transfer function, KV CO is the VCO gain and Nnom is the

nominal division value in the programable divider. As in fractional synthesizers the

5. The frequency synthesizer loop design. 121

division modulus is pseudo-randomly changed, Nnom is the closest entire value (for

instance in N = 67.12; Nnom = 67). In fact, the fractional division barely affects

the synthesizer transfer function and this is a good approximation for the frequency

domain behavior. The most significative effect of the Σ∆ modulation in the fractional

synthesizer is in the phase-noise figure (a deeper analysis was done in chapters 2 and

3). The closed loop transfer function is then:

G(f) =NTsA(f)

NTs + A(f)(5.2)

With this mathematical model, the frequency behavior of the fractional synthe-

sizer can be explored and the stability can be warranted. In equations 5.1 and 5.2

it is clear that the frequency domain behavior of the frequency synthesizer can be

manipulated with several parameters.

From the discussions in chapter 4, the VCO and frequency divider have design pa-

rameters which cannot be easily changed. Therefore, the PFD-CP current pulses and

the loop filter frequency behavior can be moved to design the frequency synthesizer.

5.2.1 The Loop Filter Transfer function

The loop filter has a current to voltage transfer function H(f). This must be a low

pass filter to convert the current pulses, from the charge pump, to a voltage value

which controls the VCO frequency. In the synthesizer’s closed loop transfer function

(equation 5.2) the number of poles determines the synthesizer’s order and the number

of integrators determines the type of synthesizer. For instance, if the low pass loop

filter is of 2nd order with an integrator included, the synthesizer is a type II of 3rd

order. This is because the VCO performs as an additional integrator [3].

The most important problem with the loop filter is the integration of the capacitors

in a CMOS process. As for frequency synthesizers, the cut-off frequency is very

low (usually it is ≤ Fref/10), the small time constants lead to very high values of

resistance and/or capacitance. This problem is beyond the scope of this thesis and

many solutions can be found in the literature [44].


The low pass filter used for the fractional synthesizer is shown in figure 5.2.

+

-

I cp

V ctrl

C 1

C 2

R 2 R 3

C 3

V ref V ref

Figure 5.2: Low-Pass filter for the frequency synthesizer.

The transimpedance for the loop filter, when the operational transconductance

amplifier is ideal, is:

Vctrl

Icp

= H(s) = − sR2 (C1 + C2) + 1

(s2R2C1C2 + sC1)

1

(1 + sR3C3)(5.3)

In this transfer function the pole-zero locations are:

ωz = − 1

R2(C1 + C2)

ωp1 = 0

ωp2 = − 1

R2C2

ωp3 = − 1

R3C3

(5.4)

With this loop filter, the frequency synthesizer can be described as a type II 4-th

order frequency synthesizer. The pole-zero locations can be selected together with

the other synthesizer parameters like Icp and Fref to reach stability and specifications.


5.2.2 The Stability Criteria

With the loop filter transimpedance H(f), the closed loop frequency synthesizer trans-

fer function G(s) can be expressed as:

G(s) =NnomTsampleA(s)

1 − A(s)(5.5)

where:

A(s) = αTsample

2πIcp

sR2 (C1 + C2) + 1

(s2R2C1C2 + sC1) (1 + sR3C3)

KV CO

s

1

Tsample

1

Nnom

(5.6)

equation 5.6 was obtained substituting equation 5.3 into 5.1. The classic control

stability criteria can be applied to this frequency domain model in the frequency

synthesizer. For the frequency synthesizer to be stable, the transfer function G(f)

must have a negative feedback. That is: the open loop transfer function A(f) must

accomplish:

|A(f)| @ ωc = 1

∠A(f) @ ωc < π (5.7)

Where the cut-off frequency ωc is defined as the frequency where the open loop

gain is A(f) = 0dB, and therefore the closed loop gain G(f) = −3dB. This is the

classic open-loop stability criteria in feedback systems [3]. Notice that the open loop

transfer function must be positive to accomplish with the negative feedback in the

loop. For instance, in equation 5.6 if the KV CO would be positive, then the Charge-

Pump current must be injected with negative polarity to maintain stability.

5.2.3 Design of Parameters

In chapter 4 the KV CO and Nnom parameters where designed. For the frequency di-

vider, the division range is N = (64..79) and for the VCO KV CO ≈ −60MHz/V .

With this fixed parameters, the loop filter and charge pump parameters where de-

signed with the equations 5.6 and 5.5 in MATLAB. The objective was to obtain a


relatively high cut-off frequency in the synthesizer transfer function to make more

evident the spur tones degradation. In this way the effect of the proposed technique

in chapter 3, for dithering the MASH Σ∆ modulator, can be demonstrated. The

parameters for the frequency synthesizer are shown in table 5.1.

Table 5.1: Frequency synthesizer loop parameters.

Parameter Value Parameter Value

Tuning Range (1.54 − 1.69)GHz fc 25KHz

Kvco −60MHzV

fz 90.4KHz

Nnom 64 − 79 ωp2 0.994MHz

Icp 10µA ωp3 3.54MHz

The frequency relations between the zero and first pole is ≈ 10 as a rule of thumb

for many frequency synthesizer architectures [3]. This frequency design parameters

allow the stability for the loop. As the VCO gain is very low, it can allow a high

Charge-Pump current value. In spite of that, a very low value for Icp is used to make

the synthesizer much more stable.

102

103

104

105

106

107

108

−150

−100

−50

0

50

100

150

Frequency (Hz)

Mag

nitu

de (d

B),P

hase

(deg

)

MagnitudePhase

(a) Open loop A(f).

102

103

104

105

106

107

108

−150

−100

−50

0

50

Frequency (Hz)

Mag

nitu

de (d

B),P

hase

(deg

)

MagnitudePhase

(b) Closed loop G(f).

Figure 5.3: Bode analysis for the Fractional Synthesizer.


Figure 5.3 show the bode curves for the open loop and the closed loop transfer

functions, for the complete frequency synthesizer, with the parameters in table 5.1.

From this bode analysis the frequency synthesizer stability, and the system lock are

ensured.

5.3 The Loop Filter Circuit Implementation.

The operational transconductance amplifier has a limited gain and bandwidth prod-

uct. Therefore, it is necessary to obtain the minimum gain and the 0dB crossover

frequency in the OTA. Figure 5.4 shows the most simple model for the loop filter that

takes into account the non ideal effects.

I cp V ctrl

C 1

C 2

R 2 R 3

C 3

V +

V ref

V -

g m R o C p

Figure 5.4: Non ideal Low-Pass filter for the frequency synthesizer.

The low pass transfer function, for the model in figure 5.4 is:

(R3sC3 + 1)Ro

(s2r2C1C2 + sC1 + gmsR2C1 + gmsR2C2 + gm

)(1 + sR3

2)s (RosC3 + R3s2C3RoRp + R3sC3 + RosRp + 1 − gmRoR3sC3 − gmRo) (sr2C2 + 1)C1

(5.8)

This non ideal transfer function was used to estimate the necessary gain and

bandwidth for the OTA which are A0 ≥ 40dB and BW ≥ 300MHz. Figure 5.5

shows the effect of the non ideal effects in the amplitude and phase characteristics in

the low pass filter. For the low pass filter cutoff frequency, the phase and amplitude

values are very close to the ideal.

126 5.3. The Loop Filter Circuit Implementation.

102

103

104

105

106

107

108

0

20

40

60

80

100

120

140

160

180

Frequency (Hz)

Mag

nitu

de (

dB),

Pha

se (

deg)

Amplitude with non ideal effectsPhase with non ideal effectsAmplitude with ideal OTAPhase with ideal OTA

Figure 5.5: Non ideal Low-Pass filter for the frequency synthesizer.

The single-ended architecture was preferred because the control voltage in the

VCO is of single polarity. Although a fully differential architecture can reduce the

common mode noise (due to the switching in digital circuits); the low pass charac-

teristic will eliminate this components. Also, a ring guard is used for the analog and

digital circuits to avoid the switching noise in the substrate. Figure 5.6 shows the

transistor level schematic of the OTA used for the low pass filter.

300/3 300/3

50/7 50/7

105/3

70/7

50/10 150/10

70/7 200/3

5/10

3/24

160/0.35

14/7

M1 M2

M3

M4 M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

V ip V in

V ctrl

5/10

Figure 5.6: Operational Transconductance Amplifier.

Transistors M4,M5 have a larger channel to increase the output resistance rds.

This is to achieve a 40dB gain without increasing significatively the input differential

pair sizes and tail current. The current source was designed as an unsensitive process-

temperature topology, presented in [45]. Because of the good performance, this same


current source was used for the charge pump as explained in the following sections.

Figure 5.7: OTA Layout.

Figure 5.8: Capacitor and resistor layout.

The layout for the OTA, the capacitors and resistors used are shown in figure 5.7

and figure 5.8 respectively. The capacitors are built by poly1-poly2 plates with a

guard ring to reduce the coupling noise, also a N-Well is buried under the capacitor

to reduce the parasitic effects in the passive element. The resistors are built with a

poly2 line on top of a N-Well in the substrate, a finger topology is used to reduce the

area and process mismatch.

The pos-layout OTA open-loop frequency response is shown in figure 5.9 for the

typical mean (TM), worst case speed (WS) and worst case power (WP) respectively.

128 5.3. The Loop Filter Circuit Implementation.

(a) Gain. (b) Phase.

Figure 5.9: OTA Frequency response.

The OTA characteristics and the passive element values, in the low pass filter, are

presented in table 5.2. For the OTA, a unit gain bandwidth of 360MHz is a good

election given a low pass filter cut-off frequency of 25KHz.

With the OTA designed and the passive elements in table 5.2 the low pass filter

layout was designed. The frequency response from a pos-layout simulation result is

shown in figure 5.10.

The DC gain for the loop filter is very high with a phase 90, which indicates the

pole at f = 0. The transfer function in equation 5.3 does not consider the parasitic

poles from the OTA. They are evident in the frequency response of the pos-layout

simulation in figure 5.10. They degrade the phase response only for high frequency

values and the stability is warranted. From the pos-layout simulation, it can be seen

a good trade-off between gain and phase in the loop filter, for the typical mean and

worst cases.


Table 5.2: Loop filter parameters.

OTA Value Passives Value

DC gain 50dB C1 160pF

Unit gain frequency (no load) 360MHz C2 16pF

Phase Margin 47deg R2 10KΩ

Voltage Offset +2.78mV C3 45pF

Vdd 3.3V R3 1KΩ

5.4 The Phase-to-Frequency-Detector.

In Fractional Frequency Synthesizers there is a strong relation between the program-

able frequency divider (including to the Digital Σ∆ modulator) and the Phase-to-

Frequency-Detector (PFD). This relation is strong because the error signal at the

PFD output depends significatively on the distribution of the transition time of the

signal coming from the programable divider.

The PFD has several non-linear characteristics and one of the most significative

is the “death zone” in the phase error detection [40]. This death zone in the PFD

characteristic can be eliminated using a delay in the reset pulse of the Flip-Flops

building the PFD. Up to now, there is no a closed form expression for the magnitude

of the delay in the reset signal. The design of the delay in the reset signal is usually

done as a rule of thumb. For instance in [40] it is mentioned that the delay magnitude

should be long enough to eliminate de death zone but it does not have to be very

long in order to reduce the noise contribution of the charge pump to the frequency

synthesizer. The charge pump noise is significant only when a very low current

magnitude used.

It is worth to mention that for Fractional Frequency Synthesizers the phase error

is never zero and it changes in a pseudo random fashion, which gives the average

fractional division factor. In this research it is demonstrated how the maximum

130 5.4. The Phase-to-Frequency-Detector.

(a) Gain. (b) Phase.

Figure 5.10: Low-Pass-Filter Frequency response.

delay in the reset signal, to avoid the PFD polarity to erroneously change, should

be calculated considering the setup time in the PFD. Also, the effect of the Σ∆

modulation is included and it was found that it does not affect the election of the

delay in the reset signal. From this error analysis an adequate value for the delay in

the reset signal can be chosen.

5.4.1 The effect of the PFD delay in the reset signal.

The PFD in figure 5.11, used in a Fractional Synthesizer, compares the phase of a

reference signal (ref) with the phase coming from the programable frequency divider

(div) and generates a signal representing the difference between their phases. This

signal consist on the difference of the two output pulses on the PFD (up− dn) and it

is transferred to the loop filter though the Charge-Pump.

If in figure 5.11, the (up, dn) signals are in low state and the reference signal “ref”

has a high-to-low transition before the one coming from the programable divider

“div”, the signal up will be activated and dn keeps in low state. In an ideal scenario,

once the up signal is high, when the div signal has a high-to-low transition the up


D Q

D Q

delay dn

up ref

div

ref

div

up

dn R

Figure 5.11: The PFD and its waveforms.

signal deactivates and the dn signal keeps in low state. In fact the PDF needs a

certain amount of time ∆R to deactivate the up signal. Therefore, the signals up and

dn are in high state for a time ∆R (see figure 5.11). This delay time ∆R is a function

of the load in the digital cells and it can be manipulated with a buffer string as shown

in figure 5.11.

As both output signals up, dn are activated at the same ∆R time; it is supposed

that no charge will be injected to the loop filter because the charge-pump currents

will be cancelled. This is only an ideal behavior because the mismatch in the charge

pump will affect the total charge injection. This undesired effect can be alleviated

with several charge injection noise reduction techniques [40], detailed in the next

section.

5.4.2 Probabilistic analysis for the PFD.

In [46] there where presented the frequency limitations of a conventional PFD. Taking

that work as a base, in this section it has been established a design consideration

for the PFD delay in Fractional Frequency Synthesizers. Consider the signals in

figure 5.12; we can define the ratio of the frequencies of the reference signal and the

divided signal as [46]:

α =fdiv

fref

(5.9)

If α < 1, at most 1 div high-to-low transition will occur in the time [t, t + Tref ]


ref

div

transition no

transition

t t+T ref

Figure 5.12: Waveforms for fref ≥ fdiv.

(one ref cycle). If it is supposed a uniform distribution of the div transition in the

interval [t, t + Tref ] then the probability of occurrence P (1) and no occurrence P (0)

will be respectively:

P (1) = α (5.10)

P (0) = (1 − α) (5.11)

With the last two equations it can be argued that if during the interval [t, t+Tref ]

there is no a down transition of the div signal; then the up output in the PFD will

not be deactivated and the average PFD output will be (up − dn) = 1. Otherwise, if

in such a time interval there is a down transition of the div signal, the average PFD

will be (up − dn) = 0.5. So, the total average output value for the PFD is:

(up − dn) = P (0) +1

2P (1) = 1 − 0.5α (5.12)

If the signals (ref, div) in the PFD have the same frequency, then the average

value will be 0.5 as long as the signals are out of phase. This analysis was taken

without the ∆R effect. The frequency limitation of the PFD, due to the delay in the

reset signal, was also explored in [46] giving as a result a value for the average PFD

output as:


(up − dn) = P (0) · 1 ·(

1 − ∆R

Tdiv

)− P (0) · 0 · ∆R

Tdiv

+P (1) · 0.5 ·(

1 − ∆R

Tdiv

)− P (1) · 0.5 · ∆R

Tdiv

=

1 − 1

2α − ∆R

Tdiv

(5.13)

With this result, the maximum frequency for the PFD not to change erroneously

the polarity is fmax = 1/(2∆R). In this section a more accurate approximation is

done by considering the effect of the setup time in the PFD. Besides, the effect of

Σ∆ modulation in Fractional Frequency Synthesizers is also taken into account for

the PFD .

5.4.3 Accurate estimation of the PFD Frequency Limit.

Considering the waveforms in figure 5.12; if α = 1 and the phase of the signals is in

the range [Tref , Tref − ∆R] the output signals will not to respond as it is expected.

This is due to the delay in the reset signal because if the down-transitions of the

signals occur during this period of time, the PFD has not been reset to start the

phase-detection again [46]. This is not completely true because the wrong operation

happens before. In figure 5.13 it is shown the layout of the PFD designed with a

CMOS AMS 0.35µm process.

Figure 5.13: Layout of the PFD.


Figure 5.14 shows the post-layout transient simulation of the PFD in figure 5.13.

In this case Tref = Tdiv = 50ns; the delay for the reset signal is ∆R ≈ 2.34ns and

from the figure it is clear that the up signal does not activate even when the phase is

out of the range [Tref , Tref − ∆R].

Figure 5.14: Waveforms for a bad PFD detection.

This is because the setup time of the gates working as flip-flops has not been taken

into account. In stead of it, if the phase difference is out of the range [Tref , Tref−∆R−Tsetup], the gates working as Flip-Flops will have the setup time necessary to make

the next signal transition in a correct fashion as is shown in figure 5.15. This simple

modification to the limit frequency might not be crucial for a low frequency analysis

but for high frequencies the delay value ∆R can be similar to the setup time and the

limit frequency for the PFD is considerably reduced. This analysis is complemented

with the inclusion of the Σ∆ modulation of the signal from the frequency divider as

explained in the next subsection.


Figure 5.15: Waveforms for a correct PFD detection.

5.4.4 The effect of the Σ∆ modulation.

In [46] it is considered a uniform distribution function, for the down transition of the

div signal, in the time interval [t, t + Tref ] of the reference signal. This is only a first

order approximation. This supposition cannot be realized when the PFD is used in

a Fractional Frequency Synthesizer because during [t, t + Tref ] the down-transition of

the div signal is controlled by the digital Σ∆ modulation; that makes the fractional

synthesizer never to be in lock. If a multi-modulus frequency divider is used, the

division factor will be randomly changing with a distribution seeming to normal as


ref

div

t 0 t 0 +T ref

Figure 5.16: Distribution function of the div transition for fractional synthesis.


With this assumption, once in “lock” for the Fractional Synthesizer, the distribu-

tion for the dn signal can be modelled by the normal function:

f(t) =e−

t−(t0+Tref /2)

2σ2

√2πσ2

(5.14)

with t0 the initial time for the ref period. Then the cumulative probability of occur-

rence of a div transition in a ref period is:

P ′(1) = P [t0, t0 + Tref ] =

∫ t0+Tref

t0

αe−

(t−t0)2

2σ2

√2πσ2

dt (5.15)

making a variable change :

P ′(1) = P [t0, t0 + Tref ] =

∫ Tref√

2σ

0

α√π

e−u2

du =

α

2erf

(Tref√

2σ

)(5.16)

Similarly, the cumulative no transition probability is:

P ′(0) = P [t0,∞) =

∫∞

t0

(1 − α)e−

(t−t0)2

2σ2

√2πσ2

dt =

(1 − α)

2erfc(0) =

(1 − α)

2(5.17)

Therefore, without taking into account the delay in the reset signal, the PFD

output has an average value:

(u − d) = P ′(1) + P ′(0) = P [t0, t0 + Tref ] + P [t0,∞] =

α

2erf

(Tref√

2σ

)+

1

2(1 − α) (5.18)


5.4.5 High frequency analysis.

In the last analysis the effect of the delay signal was not included. From the discussion

at the beginning of this section, the phases must be in the range [Tref , Tref − ∆R −Tsetup] to avoid the PFD to change the polarity erroneously. For ease in the calculation

it is assumed that the reset signal has a magnitude similar to the setup time (Tsetup ≈∆R). Also, if only one period of the reference signal is taken, then the probability

of transition of div signal is calculated in a time interval (−∞, t0 − 2∆R]. From a

similar analysis as in section 5.10, the probability for the up signal to activate in a

correct form and not in a correct form is given respectively by:

(1 − 2∆R

Tdiv

)(5.19)

(2∆R

Tdiv

)(5.20)

Therefore the probability of transition of the div signal in the interval (−∞, t0 −2∆R] (and so, the up signal is activated correctly) is:

P (−∞, t0 − 2∆R] =

∫ t0−2∆R

−∞

(1 − 2∆R

Tdiv

)e−

(t−t0)2

2σ2

√2πσ2

dt

=

(1 − 2∆R

Tdiv

)1

2erfc

(∣∣∣∣2∆R√

2σ

∣∣∣∣

)(5.21)

The probability of no transition of the div signal in the interval (−∞, t0 − 2∆R]

(and up will not activate in a correct fashion) can be calculated as:

P (−∞, t0 − 2∆R] =

∫ t0−2∆R

−∞

(2∆R

Tdiv

)e−

(t−t0)2

2σ2

√2πσ2

dt

=

(2∆R

Tdiv

)1

2erfc

(∣∣∣∣2∆R√

2σ

∣∣∣∣

)(5.22)


For this conditions the average PDF value (u − d) is:

(u − d) = P ′(0)P (−∞, t0 − 2∆R]

−P ′(0)P (−∞, t0 − 2∆R]

+P ′(1)P [−∞, t0 − 2∆R]

−P ′(1)P [−∞, t0 − 2∆R] (5.23)

which results as:

(u − d) =1

2erfc

(∣∣∣∣2∆R√

2σ

∣∣∣∣

)

(1 − 4∆R

Tdiv

)(1

2− α

2+

α

2erf

(Tref√

2σ

))(5.24)

Equation 5.24 takes into account the non uniform distribution of the transient

signals when a Fractional Frequency Synthesizer is near lock. The second term in

equation 5.24 has a sign change for the term(1 − 4∆R

Tdiv

)and it can be said that

the variance in the transition times (σ) does not affect the minimum delay value for

which the PFD makes a wrong phase comparison. For the particular case α = 1

(fref = fdiv), when the variance of the div transitions is σ = Tref/2 and normalizing

Tref = 1 we have:

(u − d) =1

2erfc

(∣∣∣∣4∆R√

2

∣∣∣∣

)(1 − 4∆R)

(1

2erf

(2√2

))(5.25)

Figure 5.17 shows the plot of (u − d2) as a function of ∆R for different σ values

when the setup time in the PFD is similar to the delay time (Tsetup ≈ ∆R). The limit

of operation for the PDF is when the average output value (u − d)2 is at minimum,

avoiding in this way, the polarity of the PFD’s output to erroneously change (that is


d(u−d)2

d(∆R)= 0). It can be seen in figure 5.17 that the maximum value for the ∆R delay

must be ∆R = 0.25Tref for this conditions. If the setup time wold not be included

then ∆R = 0.5Tref as in [46].

0 0.2 0.4 0.6 0.8 1

10−8

10−6

10−4

10−2

100

Out

put P

FD

ave

rage

(u−

d)2

Normalized reset delay (dR/Tref)

sigma = Tref/2

sigma = Tref/4

sigma = Tref/8

Figure 5.17: Normalized value of (u − d)2

for differen σ values.

In equation 5.24 the term which includes the change in the sign is(1 − 4∆R

Tdiv

)and

the variance σ does not affect the maximum reset delay that can be selected. Also in

figure 5.17 the average output is plotted for different σ values and it can be seen how

as the variance is reduced, the average value error is reduced as well.

The order of the Σ∆ modulation is the one making the variance of this model

to change. With a low order digital modulation the variance of the model σ will be

much higher. If the sigma delta modulation makes the σ variance to decrease, the

error will be much lower as shown in figure 5.17.

5.5 The Charge-Pump.

The phase difference between the ref, div signals is transferred to the loop filter via

the Charge-Pump. The charge pump injects current into a summing node as is shown

in figure 5.18.

140 5.5. The Charge-Pump.

PFD

ref

div

up

dn

I cp

I cp

up

dn x

+I cp

-I cp

Figure 5.18: Ideal Charge-Pump.

The signals (up, dn) represent the phase difference between (ref, div) and they

activate the current sources connected at node x. If the signal up is in high state,

the current injected in the node x will be +Icp; if dn is in high state the current

injected is −Icp. Ideally, if both signals are activated the total injected current is

zero. This current is feeded to the loop filter in order to control the VCO frequency

in the fractional synthesizer. The performance of the charge pump is far away from

the one shown in figure 5.18 due to several non-idealities:

• The switching noise.

As the current sources are activated with CMOS switches, the charge injection

from the CMOS switches introduces noise to the summing node x. It is nec-

essary to design complementary CMOS switches and to use clock-feed-trough

reduction techniques to minimize the noise in the loop filter. The solution to

the charge injection noise is a clock network which generates non-overlap signals

and will be explained bellow.

• The current sources start-up noise.

When the current sources are disabled, they need a certain amount of time to

totally turn-off. When they are turned-on again, it is also necessary a time

period, for the current source to settle-down completely. Also, the start-up of

the current source may inject a big amount of charge, which traduces in big

noise contributions to the low pass filter.


• Mismatch in the current sources.

The current sources in the charge-pump will have a process mismatch. This

traduces in a non-zero current when both current sources are activated. In

order to reduce the mismatches a good layout must be designed. In this thesis

the common centroid philosophy is used to reduce them.

The schematic and layout view of charge pump used in the frequency synthesizer

is shown in figure 5.19. It was designed with the temperature unsensitive current

source presented in [45].

105/3

50/10 150/10

70/7 200/3

5/10

3/24

160/0.35

14/7

Mp5

Mn6

Mp2

Mn2

Mp1

Mn1

Mn4

Mn3

Mp3

Mns1

Mps1

Mps2 V ctrl

5/10

120/12

70/7

120/12

105/3

3/0.35

3/0.35

3/0.35

3/0.35

V up V

un

V dp V dn V dpd

V dnd

V upd

V u nd

Mn5

Mp4

V ref

Figure 5.19: Charge-Pump schematic and layout views.

Transistors Mn, p1 − Mn6 compose the current source which, according to the

parameters designed in the last section, Icp = 10µA. Transistors Mns1,Mps1,Mps2

built a start-up circuit to turn-un the current source. This is necessary as the current

source has two operating points and the circuit might be inactive at start-up [45].

The rightmost branch is the current source which feeds Icp to the loop filter at

node Vctrl. The left branch is a dummy current source that is active when the right

142 5.5. The Charge-Pump.

(a) (b)

Figure 5.20: Non-overlapped signals for the switching control.

branch will not inject current. For instance, when the signals Vup, Vun are activate, the

+Icp current source is on. Then, if the +Icp is going to turn-off; the signals Vupd, Vund

activate the dummy current source in first place. Latter, the Vup, Vun signals turn the

Icp current off. In this way the current source is always on; and the charge injected

when the main current source turns off is avoided. The same occurs with the −Icp

current source and the signals Vdp, Vdn, Vdpd, Vdnd. The non overlapped signals for the

current sources switching are shown in figure 5.20 and the network to obtain this

signals is shown in figure 5.21.

up

dn

vupd

vund

vup

vun

vdpd

vdnd

vdp

vdn

HT

LT

HT

LT

HT

LT

HT

LT

Figure 5.21: Network to obtain the control switching signals.


The clock network is built with feeded-back inverters to obtain the fully differential

signals, also some inverters with a high threshold (HT) and a low threshold (LT) are

used to obtain the non-overlapped signals. The CMOS switches are controlled by

fully differential signals Vup, Vun. The switches sizes are designed to compensate the

complementary charge transfer. As the charge injection depends on the operation

region of the switches; it is highly desired to maintain the DC bias fixed. This

is achieved by the active low-pass filter implementation, fixing the Vctrl = Vref =

Vdd/2. Therefore, the dummy branch is also fixed to Vref = Vdd/2 to maintain equal

conditions. Figure 5.22 presents the pos-layout simulation of the PFD and Charge-

Pump.

(a) Reference signal leading divided signal. (b) Divided signal leading reference signal.

Figure 5.22: PFD-CP pos-layout simulation.

Figure 5.22(a) presents the case when the reference signal leads the divided signal.

If the signals Vup, Vdp are inactive, at the down transition of ref the charge-pump

injects current to the loop filter. When the reverse occurs, in the down transition of

div the charge-pump injects current with the negative direction (see figure 5.22(b)).

Figure 5.23 shows the post-layout simulation results when the PFD-Charge-Pump

144 5.6. The Fractional Frequency Synthesizer circuit.

(a) Reference signal leading divided signal. (b) Divided signal leading reference signal.

Figure 5.23: PFD-CP-LPF pos-layout simulation.

and the loop filer function together. When the ref signal leads the div signal, the

charge pumps injects current to the loop filter and the control voltage diminish (re-

member the negative sign for the loop filter’s transimpedance). The opposite occurs

when the div signal leads the ref signal, see figure 5.23(b).

5.6 The Fractional Frequency Synthesizer circuit.

The Fractional Frequency Synthesizer was implemented with the design considera-

tions developed in this chapter for the PDF, Charge-Pump and loop filter; the VCO

and frequency divider in chapter 4; and with the proposed digital Σ∆ modulator

architecture for spur tones reduction in chapter 3. The circuit was designed with

the Mentor Graphics IC Flow 2006.2. The integrated circuit was fabricated with the

Austria Micro-Systems (AMS) 0.35µm CMOS C35B4C3 process with participation

in the mini@sic program.

The layout of the Fractional Frequency Synthesizer is shown in figure 5.24 where


Figure 5.24: Layout view of the chip designed to test the Fractional Synthesizer.

the principal blocks are:

• The entire frequency synthesizer with analog buffers and pads to make on die

measurements. This section was also prepared to test the circuit at low fre-

quencies to make indirect measurements (area CHIPA in figure 5.24).

• The VCO and Programable Frequency divider to characterize the multi-phase

switching scheme. The circuit was prepared to make only low frequency tests

in a Printed Circuit Board (PCB), (area CHIPB in figure 5.24).

• The VCO with analog buffers and pads to obtain the voltage to frequency

transfer curve (area CHIPC in figure 5.24).

The circuit was simulated with Eldo in the Mentor IC Flow with all the parasitics

included after the layout extraction. Due to the big amount of parasitic elements the

simulation task is very time consuming. Figure 5.25 shows the pos-layout simulation

result of the fractional frequency synthesizer which compares the frequency from the

reference signal with the frequency from the divided signal. It can be seen that the

146 5.6. The Fractional Frequency Synthesizer circuit.

Figure 5.25: Pos-Layout transient simulation of the Fractional Frequency synthesizer.

divided signal is changing with a pseudo-random fashion. Nevertheless in average

fref ≈ fdiv. This is the main characteristic in fractional synthesizers because the

closed loop configuration never locks. Instead, the average value of the signal at the

dividers output must be fdiv ≈ fref .

In order to ensure the lock of the fractional frequency synthesizer a pos-layout

simulation was run with a bigger frequency step and is shown in figure 5.26(a). Also,

a simulation was run with the polarity of the PFD changed to illustrate how the

fractional synthesizer will not lock for that case.

The pos-layout worst cases simulation where not realized as it is a very time

consuming task. It can take about one month to obtain a transient simulation when

all the parasitics effects are present. In spite of that, each critic cell was characterized

with the corner cases individually to ensure the good design.


1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

Vol

tage

(V

)

V(VCTRL)

0.4U 0.6U 0.8U 1.0U 1.2U 1.4U 1.6U 1.8U 2.0U 2.2U 2.4U 2.6U 2.8U

Time (s)

(a) Vctrl when in lock.

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

Vol

tage

(V

)

V(VCTRL)

0.0U 5.0U 10.0U 15.0U 20.0U 25.0U 30.0U 35.0U 40.0U 45.0U 50.0U

Time (s)0.0U

(b) Vctrl when not in lock.

Figure 5.26: Pos-layout simulation for a big frequency step.

5.6.1 The Phase-Noise Approximation.

The phase noise was approximated with the frequency domain models presented in

chapter 2; where the simulation methodologies where detailed. With the design of the

main cells in this chapter, the frequency synthesizer phase-noise can be approached.

Table 5.3: Fractional Frequency Synthesizer parameters.


Closed-Loop cut-off Freq. 25kHz Fref 21.6MHZ

Synthesizer order 4th Σ∆ order 3th

Σ∆ architecture Efficient Dithered MASH Fractional Resolution 1/256

Charge-Pump noise ≈ 5x10−21 A2

HzLoop-Filter noise 1.85x10−16 V 2

Hz

VCO noise ≈ 2.1x10−18 V 2

HzVoltage 3.3V

The phase noise figure was simulated with the parameters in table 5.3. This

parameters where obtained from the noise analysis of each cell, obtaining in this

way the input referred noise for the charge-pump, loop filter and VCO. The noise

parameters are given as white noise spectral densities. Figure 5.27 shows the fractional

148 5.7. Experimental Results

frequency synthesizer total phase-noise figure. The noise contributions of each cell

are detailed.

104

105

106

107

−130

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

Offset frequency from the carrier (Hz)

Pha

se−N

oise

(dB

c/H

z)

Total Phase−NoiseSigma−DeltaCharge−PumpVCO Loop−Filter

Figure 5.27: Simulated Phase-Noise.

5.7 Experimental Results

The circuit containing the fractional frequency synthesizer was fabricated in a mini@sic

run whit the Europractice IC service. The microphotograph is shown in figure 5.28.

Figure 5.28: Microphotograph of the chip.


The circuit was prepared to tests its performance in low frequency by measuring

the signal from the programable divider. Also, the chip was prepared to measure

the high frequency power spectrum (from the Fractional Synthesizer) in on-die mea-

surements. Figure 5.29 shows the schematic and the physical distribution of the test

setup is shown in figure 5.30.

PFD CP LPF

P. DIV.

SIGMA DELTA

F ref F out

V DDD1

V SSD1

V DDA1

V SSA1

K 0 K 1

K 6 K 7

C 3 C 2 Controlp

S64p

(DIGITAL CONSTANT INPUT)

(DITHER CONTROL)

(ENTIRE DIVISION) (ANALOG VDD)

(DIGITAL VDD)

Digital circuit Analog Circuit

V ref

Figure 5.29: Test setup schematic.

Figure 5.30: Measurement setup.

The reference signal Fref is obtained from an external pulse generator; this signal

is feeded to the reference port via the PCB board. An 8-bit digital word (K0 . . . K7)

is programmed in the circuit board to change the fractional value in the digital Σ∆

modulator. The low frequency signal S64p is measured from the programable divider


output. This signal must have, in average, the same frequency than the reference

signal when the fractional synthesizer is in lock.

Figure 5.31: Measurement result when the fractional synthesizer is “locked”.

The signals from the reference frequency ref and from the programable divider div

are shown in figure 5.31 when the fractional synthesizer is in lock for fref = 21MHz.

PFD-CP PFD-CP

Sigma-Delta

Figure 5.32: Signal spectrum when the fractional synthesizer is at 1.45369GHz.

To test the fractional synthesizer in high frequency, analog buffers where used to

drive an on-die pad. An active probe model 35A from Picoprobe was used to test the

circuit. The test setup in figure 5.30 was used to obtain the high frequency measure,

and the power spectrum obtained from the Advantest R3256A Spectrum Analyzer is


a ) W i t h o u t d i t h e r e d S i g m a - D e l t a b ) W i t h d i t h e r e d S i g m a - D e l t a

C a r r i e r C a r r i e r

Figure 5.33: Signal spectrum when the fractional synthesizer is at 1.45369GHz.


When a reference frequency of 21.6MHz, the circuit was locked to a fractional

value of K = 67.3007821 which is a fout ≈ 1.45369GHz. In the output spectrum

of figure 5.32 the main noise contributions are detailed. It is worth to note that

the signal in the output spectrum is attenuated 10dbm by the active probe. The

real signal power is in the range of −3dBm. As the Advantest R3256A spectrum

analyzer has not the sufficient band-width resolution to differentiate between the

spur tones and the other noise sources, the circuit was tested with an Agilent 4352B

VCO-PLL analyzer. This VCO-PLL analyzer has a noise sensitivity up to 150dBc

but unfortunately the frequency span is of only 10MHz. This span is not enough to

observe the total Σ∆ modulation effect in the Phase-Noise figure.

The signal spectrum obtained with the Agilent 4352B, with the spam shifted, is

shown in figure 5.33. Figure 5.33a shows the spectrum when the dither signal is not

added and figure 5.33b shows when the dither signal is added as proposed in chapter

3. The spur tones reduction is clear from the spectrum, even when the active probe

attenuated the signal.

The phase-noise figure obtained from the VCO-PLL analyzer is shown in fig-

ure 5.34. This phase noise figure could not be properly obtained due to the limited


Sigma-Delta contribution

PFD-CP

Figure 5.34: Phase-Noise figure.

frequency span in the VCO-PLL analyzer. In spite of that, the phase noise figure ob-

tained in the experimental results matches well with the estimated phase noise figure

in figure 5.34. An unexpected effect is obtained because the spur tones affect in the

region where the charge-pump noise is dominant. The physical explanation in this

effect is the to the noise coupling in the substrate due to the digital circuits. When

the dither addition is activated, as proposed in chapter 3, the fractional synthesizer

was characterized and the phase-noise is shown in figure 5.35.

The dither addition reduces the spur tones dramatically. Once again it is em-

phasized that the dither addition barely increases the circuit complexity. The phase

noise figure with the dither addition is −112dB at 10MHz offset from the carrier

frequency. A resume of the fractional frequency synthesizer designed in this thesis is

shown in table 5.1.

The fractional frequency synthesizer designed in this thesis was compared with

state of the art works which tried to reduce the spur tones in this mixed signal circuits.

Table 5.5 shows the main characteristics of the frequency synthesizers. A figure of


Figure 5.35: Phase-Noise figure.

merit, for this case, might not be enough to fully characterize the architecture because

there are many parameters which can be manipulated to obtain a good number.

Instead of that in table 5.5 the Σ∆ order, the synthesizer order and normalized

loop filter cutoff frequency are detailed. The fractional synthesizer in this work has a

very simple digital Σ∆ architecture for spur tones reduction with a low order fractional

synthesizer architecture with a relatively high cut-off frequency.


Table 5.4: Fractional Frequency Synthesizer parameters.


Area (700 × 900)µm Fref 21.6MHZ

Tuning Range (1.4 − 1.57)GHz Closed loop cut-off fc 25KHz

Synthesizer order 4th Fractional Resolution 1/256

Σ∆ architecture Efficient Dithered MASH Σ∆ order 3rd

Spur tones no Vdd 3.3V

Phase-Noise −110dBc @ 10MHz Power consumption 380mW

Settling time (full range) 200µs

Table 5.5: Σ∆ Architectures comparison.

Σ∆ Σ∆ Order Synt. Order Dither Spurs

and (ωc/ωref )

Single-Loop [21] 3 4 (0.005) 224 LFSR −80dB@200KHz

Multi-Loop [22] , [23] 4 5 (0.023) No dither −70dB@300KHz

Error-Feedback [24] 3 4 (0.0153) 210 Off-Chip LFSR No

Hybrid [20] ≥ 4 5 (0.02) No Dither −70dB@10MHz

Hybrid [11] ≥ 6 3 (0.0031) No Dither No

Chebyshev [25] 3 5 (0.0106) No Dither No

MASH [27] 3 4 (0.00135) Off-Chip Dither No

MASH This work 3 4 (0.00115) Eff. M-bit No

Chapter 6

Conclusions.

This thesis has focused on the main drawbacks of the state-of-the-art fractional fre-

quency synthesizers in integrated circuits. The main contributions of this work can

be divided in three parts.

6.1 The simulation strategies.

As the fractional synthesizer is a mixed signal circuit, it contains many sub-circuits

and therefore thousands of transistors. During the design task, it is not practical to

include all the circuits, when a single cell is designed. It is more convenient to use the

transistor level model of the circuit being designed and macro-models for the rest of

the circuits. In order to design a fractional frequency synthesizer it is also necessary

to understand all the noise and error sources in the circuit.

Matlab-Simulink is a good tool to model the integrated circuits with several noise

sources but it is not capable to substitute this models for transistor level cells. On

the other hand, VerilogA is a tool that can handle behavioral models going down a

transistor level design. The behavioral models are hardware description scripts which

represent the network function of the circuits and they are suitable to model the

frequency synthesizer blocks. In spite of all the advantages in the behavioral models,

the most recent scripts presented in the literature have several disadvantages. To

155

156 6.1. The simulation strategies.

include the most important noise sources in the behavioral models, many instructions

and parameters must be added. The behavioral models must have a trade-off between

accuracy and simulation time.

In chapter 2 it was mentioned that Phase-Noise and Jitter are two ways to char-

acterize the spectral purity in frequency synthesizers; the former in the frequency

domain and the latter in the time domain. In the state-of the art behavioral models,

the noise contribution is commonly added as time Jitter in the signal. A mathemati-

cal analysis was realized to find the closed form expressions to relate the Phase-Noise

and Jitter in behavioral models. With this expressions, it is possible to model the

noise contribution in the circuits building the fractional synthesizer as additive noise

sources. Each additive noise source has a mean square value obtained from the fre-

quency domain model of the circuits.

This new way to model the Phase-Noise in fractional synthesizers, contrary to

the time domain Jitter, is more direct from the circuit designer’s point of view. The

principal instructions for the new behavioral models were presented and they where

compared with the models that add the noise in the circuits as Jitter. This new

philosophy to model the phase noise was applied in every cell in the fractional syn-

thesizer.

In the Voltage Controlled Oscillator it was demonstrated, with behavioral simula-

tion results, that the new way to model the Phase-Noise is more accurate than state

of the art models. This is because the time jitter instructions use a mathematical

approximation that works only for close values of frequency offset from the carrier,

in the Phase-Noise figure. It was also demonstrated that the noise contribution from

the loop filter can be included in the VCO model, without loose of accuracy.

It was also demonstrated that the noise in the PFD-Charge-Pump circuit is mainly

due to the noise sources in the Charge-Pump and the time Jitter in the digital circuits

is not significative. Once again, the frequency domain noise additive sources model

is more accurate.

The Jitter noise from the Programable Divider and the digital Σ∆ modulation is

6. Conclusions. 157

not as significant as other noise sources in the system. Therefore, we conclude that

the noise sources in the VCO-Loop-Filter, and the Current Sources in the Charge-

Pump are the most significative in the fractional synthesizer. They can be added

with the frequency domain based behavioral models presented in this thesis. With

the proposed models there can be found a trade-off between accuracy and simulation

time.

6.2 Effective dithering the MASH Σ∆ modulators.

The fractional frequency synthesizer in strict sense is not a phase-locked-loop. It

changes the division factor in a pseudo-random way and the total average division

factor is an entire value plus a fractional factor. The digital circuit that changes the

division modulus in this way is a digital Σ∆ modulator. The fractional synthesizer

is, therefore, a digital-to-frequency converter.

The disadvantage in the digital Σ∆ modulator is the periodic quantization error.

This periodicity is reflected as spur tones in the phase noise figure in the fractional

frequency synthesizer. To reduce the spur tones, the digital Σ∆ modulator should

be of high order. Nevertheless, for a fractional synthesizer the Σ∆ modulator order

must not be greater than the synthesizer order; otherwise the phase noise is greatly

affected. Therefore the order of the Σ∆ is limited by the fractional synthesizer, which

is commonly less than 4-th order.

In chapter 3 the state of the art architectures for digital Σ∆ modulators in frac-

tional synthesizers was revised. It can be concluded that the MASH architecture has

the best trade-off between noise-shaping and complexity. The only disadvantage is

the spur tones appearance.

In this thesis work it is proposed to reduce the spur tones magnitude by using

Linear Feedback Shift Registers (LFSR). Although the LFSR are already used in the

literature to reduce spur tones, in this thesis the different paths to add the dither

signal where explored. It was demonstrated that adding the dither signal in the

158 6.3. The fractional synthesizer loop.

internal nodes of the MASH architecture is a good way to shape the additive dither.

One of the main contributions of this work is the mathematical demonstration

to show that, increasing the LFSR size will note reduce the spur tones if it is not

properly added. With the proposed way to add the dither signal a simple 8-bit LFSR

is enough to randomize the output sequence of an 8-bit MASH 1-1-1 architecture. The

performance of the dither addition was compared with the state-of-the-art techniques

to reduce spur tones. It was demonstrated experimentally that the proposed technique

is as effective as the Modified Error Feedback Architecture, but with much less cost

in the circuit complexity.

6.3 The fractional synthesizer loop.

The design of the frequency synthesizer depends on the characteristics of the main

analog blocks in the loop. For instance, the KV CO gain is a critical value to obtain

the rest of the parameters which define the frequency domain behavior for the frac-

tional synthesizer. In chapter 4 the tuning range for LC-tank VCOs is explored by

analyzing the bias ranges for which the varactor is more linear. The linear tuning

range is improved by biasing the VCO in such a way that the DC level is close to

the most negative (or) positive rail. Under this conditions, the varactor capacitance

is therefore more linear, and so the tuning range. The bias conditions which allow a

linear tuning range also reduce the harmonic distortion of the output signal. This was

demonstrated with a fourier analysis of the currents in the VCO. We can conclude

that the characteristics in the VCO can be improved by properly biasing the crossed

coupled differential pair.

The Phase-to-Frequency detector uses a delay in the signal path to avoid the death

zone in the phase-detection characteristic. This delay was usually designed as a rule

of thumb; in this thesis a mathematical model was developed to obtain a closed form

expression to determine the delay magnitude. This expressions helped to conclude

that the Σ∆ modulation does not affect the absolute delay value but the setup time

6. Conclusions. 159

in the PFD gates does. The result from this research is a modification in the limit

frequency for the PFD in fractional frequency synthesizers.

Finally some techniques to avoid digital glitches in the multi-modulus programable

divider were proposed. One good solution for this problem is to low the frequency

at which the digital programable functions are realized. This changes the division

modulus factor and all the parameters must be designed according this low frequency

range. Instead, in this work the glitches are avoiding by using a synchronization

network in the phase/-select logic. The proposed techniques to design a fractional

frequency synthesizer where proved by the experimental results of the fractional syn-

thesizer manufactured in the AMS 0.35µm.

6.4 Future work.

As the frequency synthesizer are necessary in many communication applications it is

necessary to make more power efficient circuits. The VCO and high frequency blocks

in the programable divider are high consumption cells and a great amount of power

can be saved if this cells reduce consumption. The noise from the charge-pumps is

the most significative error source in this systems. This noise must be reduces as low

as possible. An active research line is raising in which all-digital implementations

avoid the use of charge-pump. Nevertheless, the PLL based fractional synthesizers

have an enormous application field. It goes from mobile communication systems to

clock distribution networks in digital processors.

160 6.4. Future work.

Appendix A

Pseudo Random Generators

In the proposed technique to avoid spur tones in the Phase-Noise figure for Σ∆

Fractional frequency synthesizers, a 1-bit digital pseudo-random signal is added in a

MASH 1-1-1 architecture in such a way the spur tones are avoided barely increasing

the digital Σ∆ modulator complexity. This digital pseudo-random signal is called a

“dither signal”. Because of its simplicity the most commonly used dither generator

is the Linear Feedback Shift Register. In this appendix the theoretical considerations

used for the design of the 8-bit LFSR in the proposed dither technique are presented.

A.1 Linear Feedback Shift Register (LFSR).

A LFSR is a digital circuit processing the logic 1-0 values in the form of figure A.1.

x 0 x 1 x 2 x 3 x 4 x 5

c 0 c 1 c 2 c 3 c n

Figure A.1: Linear feedback shift register concept.

In periodic intervals (given by a clock signal), the xi → i > 1 is transferred to

161

162 A.2. Maximally length LFSR.

xi−1 and the x1 data is lost. Thus, the new xn content is given by:

xn =n∑

i

xici (A.1)

Each one of the coefficients ci must be previously now and a different combination

of them gives a differen sequence length. The addition is done as a digital module-2

⊕ operation (an XOR function). The longest period for the generated sequence of a

n stage LFSR is (2n − 1) and when the generated sequence reaches this period it can

be said it is a maximally length LFSR.

The LFSR can be implemented with simple Flip-Flops and XOR or XNOR gates,

the XOR gates quantity defines the values of the ci coefficients. Figure A.2 shows

the realization of a LFSR with 2 coefficients and a maximum sequence length of

(22 − 1) = 3.

D Q

Q

D Q

Q

c 0 c 1

x 1 x 2

c 1

c 2 x 1 x 2

clk

c 2

c 0

x 0

Figure A.2: 2-bits LFSR.

There are several ways to obtain the coefficients ci for the circuit to have a maxi-

mally length period. The analysis presented in this appendix is based on the Galoid

Fields theory and for a more deep analysis the references can be consulted.

A.2 Maximally length LFSR.

The modulo-2 addition operation (represented by ⊕) is used to represent the basic op-

eration in LFSRs. For binary signals the modulo-2 addition is equivalent to the XOR

operation. A pseudo-random sequence can be obtained with the LFSR in figure A.3.

Every element of the sequence is given by:

A. Pseudo Random Generators 163

D D D x k x k-1 x k-2

x k-n-1 x k-n

h 1 h 2 h n-1

h n h 0

Figure A.3: LFSR operations.

xk = h1xk−1 ⊕ · · · ⊗ hnxk−n (A.2)

if we add ⊕ xn on both sides of this equation and given xn ⊕ xn = 0:

xk ⊕ xk = xk ⊕ h1xk−1 ⊕ · · · ⊗ hnxk−n = 0 (A.3)

This expression is the same as the convolution of xk ∗ hk and for this particular

case xk ∗ hk = 0 for all h0 = 1. To make operations is better to use the modulo-2 D

transformation. That is it, for a bk sequence:

B(D) = · · · ⊕ h−1D−1 ⊕ h0D

0 ⊕ h1D1 ⊕ h2D

2 ⊕ · · · (A.4)

In this way the convolution of two sequences can be expressed as:

ck = gk ∗ bk (A.5)

C(D) = G(D)B(D) (A.6)

A LFSR sequence can be represented as a series H(D) with a characteristic poly-

nomial h.

H(D) = h0D0 ⊕ h1D

1 ⊕ h2D2 ⊕ · · · ⊕ hnD

n (A.7)

h = [h0, h1, h2, . . . , hn] (A.8)

For a n-bit LFSR to have a maximally length sequence, its characteristic polyno-

mial H(D) must accomplish the following restrictions:

164 A.3. Circuit implementation.

1. H(D) must not be factorized in (1 ⊕ D)m terms.

2. The last restriction must be for m < (2n − 1).

For instance: a 2-bit LFSR must have a characteristic polynomial:

h0 ⊕ h1D ⊕ h2D2 −→ h0 = h1 = h2 = 1 (A.9)

This is because the characteristic polynomial cannot be factorized for m < (2n −1) = 3. For the 8-bit LFSR case the characteristic polynomial must be:

H(D) = 1 ⊕ D2 ⊕ D3 ⊕ D4 ⊕ D8 −→ h0 = h2 = h3 = h4 = h8 = 1 (A.10)

Although there are more characteristic polynomials for a maximally length LFSR

by changing the sign oplus with ⊖ the circuit implementation is much easier by the

⊕ operation with XOR functions. This is because for digital signals the addition is

equivalent to the XOR function on the other hand the substraction is realized with

more complex digital circuits.

A.3 Circuit implementation.

To characterize the sequence length in the Linear Feedback Shift Registers the discrete

autocorrelation function is used. For a finite sequence the autocorrelation function is

defined as:

rxx(l) =1

N

N∑

n=0

x(n)x(n − l) (A.11)

Where n is the sequence index and l ≥ 0 is the lag index of the autocorrelation

sequence. Because of the finite sequence size it is recommended to estimate the

autocorrelation for at least M lags to properly show the periodicity of the sequence.

In every case of study for this research M ≫ N .

A. Pseudo Random Generators 165

D Q

Q

D Q

Q

D Q

Q

D Q

Q

c 1

c 2 c 3

c 0

(a) 4-bit Linear Feedback Shift Register.

0 100 200 300 400 500 600−0.2

0

0.2

0.4

0.6

0.8

Lag

No

rmal

ized

au

toco

rrel

atio

n

(b) Autocorrelation sequence.

Figure A.4: Autocorrelation for 4 bit LFSR

D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

D Q

Q

clk

(a) 8-bit Linear Feedback Shift Register.

0 200 400 600 800 1000 1200−0.2

0

0.2

0.4

0.6

0.8

Lag

No

rmal

ized

au

toco

rrel

atio

n

(b) Autocorrelation sequence.

Figure A.5: Autocorrelation Sequences

For the 4-bit LFSR, the circuit implementation is shown in figure A.4(a). The

autocorrelation function was estimated in Matlab and it is shown in figure A.4(b).

This LFSR implementation generates a 1-bit sequence with a 15 samples periodicity

because it is implemented with the characteristic polynomial h0 = h1 = h4 = 1.

For the 8-bit LFSR the architecture with coefficients as in figure A.5(a) has the

characteristic polynomial h0 = h2 = h3 = h4 = h8 = 1. The autocorrelation sequence

for the first 1024 lags was obtained in Matlab and it is shown in figure A.5(b). With

this architecture the LFSR has a periodicity of 256 clock cycles. In the proposed

technique to avoid spur tones in the Phase-Noise figure this 8-bit LFSR was enough

166 A.3. Circuit implementation.

to randomize the output sequence of a digital MASH 1-1-1 Σ∆ modulators. The

simple dither addition is the result of the research in the fundamentals to add a

dither signal in digital Σ∆ modulators.

Appendix B

Resumen en extenso

B.1 Introduccion.

En muchas aplicaciones, es necesario generar una senal en el interior de un circuito

integrado. La senal generada debe tener un buen desempeno en cuanto al uso eficiente

de los recursos usados para generarla y en cuanto a la ausencia de errores y fuentes de

ruido. El bloque que genera esta senal es conocido como sintetizador de frecuencia.

Este trabajo de investigacion resuelve algunos de los problemas en el diseno de sinte-

tizadores de frecuencia N-fraccional que no habıan sido resueltos de manera adecuada

hasta su publicacion.

B.2 Capıtulo 1.

Una de las maneras mas eficientes para generar una senal es mediante la sıntesis

indirecta de frecuencia. En este metodo, un lazo de amarre de fase (PLL) genera una

senal con una frecuencia que es un multiplo entero de la frecuencia de referencia. La

gran desventaja es la conexion entre la frecuencia de referencia y el paso con el que

se puede cambiar la frecuencia de salida. Esta limitante implica una gran dificultad

para integrar al sintetizador en silicio.

Una solucion para el problema antes citado es la sıntesis de frecuencia fraccional.

167

168 B.3. Capıtulo 2.

En esta tecnica, el divisor de frecuencias es programable y en varios ciclos de la fre-

cuencia de referencia el modulo de division es cambiado. Si esta variacion del modulo

de division es de manera aleatoria, en promedio, se obtiene una division entera mas

una fraccion (N +n). El modulo se puede cambiar con una senal digital que proviene

de un acumulador, el acumulador digital es un modulador Σ∆ de primer orden. Este

controlador digital provoca una gran desventaja porque la caracteristica periodica de

la senal del acumulador degrada el ruido de fase del sintetizador fraccional.

La motivacion principal de este trabajo de investigacion es la reduccion de la

degradacion del ruido de fase debida a la periodicidad del modulador Σ∆. Sin em-

bargo, durante el desarrollo de la investigacion se encontraron nuevas estrategias de

diseno y simulacion que dieron un avance en el estado del arte del diseno de sinteti-

zadores fraccionales. Estas aportaciones se mencionan a lo largo de la tesis: el capıtulo

2 muestra los nuevos modelos comportamentales para la simulacion de este circuito de

senal mixta. En el capıtulo 3 se desarrolla una nueva filosofıa para desabilitar la peri-

odicidad en el modulador Σ∆; esta metodologia es demostrada con elementos teoricos

que recien han sido desarrollados en el estado del arte. El capıtulo 4 trata nuevas

consideraciones de diseno para el oscilador controlado por voltaje y para el divisor

programable. Ambos circuitos son los que presentan mas retos para el disenador de

circuitos integrados. Finalmente el capıtulo 5 muestra el diseno del sintizador com-

pleto y los resultados experimentales que sustentan las hipotesis planteadas en este

trabajo de investigacion.

B.3 Capıtulo 2.

Cuando se disena un circuito complejo, como es el sintetizador fraccional, la gran

cantidad de elementos y la gran diferencia de las constantes de tiempo en el sistema

presentan un reto para la simulacion. Simular al circuito completo con todos los

elementos parasitos es una tarea que consume una gran cantidad de tiempo. Por

ello, en el proceso de diseno es necesario describir el comportamiento de los elementos

B. Resumen en extenso 169

para garantizar su buen desempeno. Una simulacion en Matlab puede ayudar, pero

en este ambiente no se pueden sustituir los modelos matematicos por modelos a nivel

dispositivo. La filosofıa de simulacion con Verilog-A, Verilg-AMS si permite dicha

tarea que es de gran utilidad en el diseno del circuito.

En este capıtulo, ademas de resumir las bases teoricas que describen al ruido de

fase, se proponen nuevos modelos comportamentales. Estos modelos utilizan una

descripcion del circuito con base en su comportamiento linealizado en el dominio de

la frecuencia. Esta filosofıa fue aplicada a los bloques que generan a las fuentes de

ruido mas significativas en el sintetizador fraccional.

Se presentan los resultados a nivel simulacion comportalental que son comparados

con un modelo matematico. Como conclusion es posible decir que los modelos prop-

uestos predicen de una mejor manera a los bloques que componen al sintetizador sin

aumentar demasiado el tiempo de simulacion.

B.4 Capıtulo 3.

En este capıtulo se describe de manera detallada como es el funcionamiento de la

sıntesis de frecuencia fraccional. Con una comparacion cualitativa de todos los mod-

uladores Σ∆ digitales, usados para la sintesis fraccional, se pudo concluir que la arqui-

tectura MASH es la que tiene un mejor compromiso entre complejidad y moldeado de

ruido. La desventaja es que los moduladores MASH son propensos a la generacion de

tonos espurios. Debido a su baja complejidad, la arquitectura MASH ha sido usada y

recientemente muchos trabajos han intentado reducir los tonos espurios sin aumentar

su complejidad. En este capıtulo se resumen los mas importantes. El objetivo es

deshabilitar la periodicidad sin aumentar de manera significativa la complejidad.

Una solucion general al problema es anadir una secuencia aleatoria (comunmente

llamada dither) para deshabilitar la periodicidad. Para esto, es necesario disenar

un generador de secuencias muy grande. En este trabajo de tesis se demuestra

matematicamente, y con simulaciones, que no importa si el perido de la secuencia

170 B.5. Capıtulo 4.

es muy grande; si no se anade de manera adecuada a la arquitectura MASH no existe

efecto alguno. Este estudio cuantitativo y cualitativo es usado para proponer una

manera mas eficiente para anadir la secuencia pseudoaleatoria.

La solucion consiste en anadir una secuencia pseudoaleatoria en el bit menos

significativo de las dos ultimas etapas del modulador MASH. De esta manera la pe-

riodicidad es deshabilitada con el uso de un registro lineal de corrimiendo de M -bits

para una arquitectura MASH de M -bits de resolucion. Un analisis matematico de-

muestra la efectividad de la propuesta. Para demostrar esta hipotesis se fabrico un

modulador MASH 1-1-1 en un proceso CMOS de 0.35µm. Los resultados experi-

mentales comprueban que la propuesta de esta tesis deshabilita la periodicidad sin

aumentar los recusos utilizados. El trabajo es comparado con las distintas soluciones

que recientemente se han publicado en el estado del arte.

B.5 Capıtulo 4.

El diseno del sintetizador fraccional esta restringido de manera importante por los

parametros del oscilador controlado por voltage (VCO) con una arquitectura tanque

LC y por el divisor programable.

En el caso del VCO la gran limitante consiste en el rango de entonado que, ademas

de ser limitado, es no lineal. Para reducir esta desventaja en esta tesis se propuso una

nueva consideracion de diseno. El uso de varactores PMOS o NMOS es muy comun

en los VCO, el varactor debe trabajar en la region lineal para poder controlar la

capacitancia intrınseca. Si el varactor sale de esta region de operacion la capacitancia

intrınseca deja de ser una funcion fuerte del voltaje de control. Por ello, se propuso

disenar al VCO con el nivel de DC de salida, lo mas cercano al riel mas positivo,

o negativo (dependiendo de la arquitectura). Con esta consideracion, los varactores

estan en la region lineal para un rango mas amplio del voltaje de control. Otras

ventajas son el aumento de la frecuencia de operacion y la reduccion en la distorsion

armonica total (ambas ventajas demostradas en este capıtulo).

B. Resumen en extenso 171

El divisor programable tambien presenta un reto para el disenador de circuitos:

desde el diseno de las primeras etapas que operan en alta frecuencia, hasta el circuito

digital que programa a la division total. En el caso de las primeras etapas el diseno

fue elaborado con celdas analogicas que necesitan un buen patron geometrico para

reducir la probabilidad de falla. En el caso de la logica que programa al factor de

division en este trabajo se propone una logica sincronizada. Esta manera de disenar

al divisor programable reduce significativamente la probabilidad de una falla por las

variaciones del proceso de fabricacion.

Las consideraciones de diseno presentadas en este capıtulo fueron demostradas

experimentalmente con un circuito intrgrado en el mismo proceso CMOS de 0.35µm

B.6 Capıtulo 5

En este capıtulo se presenta el diseno de todo el lazo de retroalimentacion en el

sintetizador fraccional. Una ves que se conocen los parametros del VCO y del divisor

programable; el PFD, la bomba de carga y el filtro de lazo pueden disenarse con mayor

grado de libertad. El diseno es un procedimiento que involucra a las simulaciones

compartamentales propuestas en el capıtulo 2 y al diseno de cada una de las celdas

del sintetizador como se propuso desde el capıtulo 3.

Un modelo en el dominio de la frecuencia permite establecer los parametros de

todo el sintetizador para asegurar la estabilidad. Un filtro de lazo activo es preferible

para reducir, en lo posible, el tamano de los elementos pasivos. Al mismo tiempo

esto permite fijar un potencial a la salida de la bomba de carga para reducir el ruido

por inyeccion de carga. La bomba de carga es disenada con una fuente de corriente

insensible a la temperatura y a las variaciones del proceso de fabricacion. Una red

de relojes con fases no traslapada es usada para reducir el ruido en la bomba de

carga por inyeccion de carga. En este trabajo de tesis tambien es propuesta una

consideracion de diseno para el retardo en el detector de fase frecuencia, usando un

modelo probabilıstico.

172 B.6. Capıtulo 5

El sintetizador de frecuencias fue disenado en el mismo proceso CMOS de 0.35µm.

En este capıtulo se muestran los resultados experimentales que validan las hıpotesis

de esta investigacion. Como trabajo futuro es necesario explorar si, en los nuevos

procesod de fabricacion de circuitos integrados, una implementacion en senal mixta

sigue siendo viable para los sintetizadores de frecuencia. Es necesario comparar su

desempeno con las implementaciones completamente digitales.

Bibliography

[1] M. H. Perrott, T. L. Tewksbury, and C. S. Sodini, “A 27-mW CMOS Fractional-

N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,”

IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2048–2060, dec 1997.

[2] B. Razavi, Analog RF Design. USA: Kluwer Academic Publishers, 1998.

[3] C. S. Vaucher, Architectures for RF Frequency Synthesizers. Boston, Dordretch,

London: Kluwer Academic Publishers, 2002.

[4] V. Reinhardt, K. Gould, K. McNab, and M. Bustamante, “A Short Survey of

Frequency Synthesizer Techniques,” in Proceedings of the 40th Annual Frequency

Control Symposium, 1986, pp. 355–365.

[5] P. G. A. Jespers, Integrated Converters D to A and A to D ARCHITECTURES,

ANALYSIS AND SIMULATION. Great Claredon Street, Oxford: Oxford Uni-

versity Press, 2001, ch. 8.

[6] H. R. Rategh and T. H. Lee, MULTI-GHz FREQUENCY SYNTHESIS & DI-

VISION. Boston, Dordretch, London: Kluwer Academic Publishers, 2001.

[7] J. Janssens and M. Steayert, CMOS Cellular Receiver Front-Ends. Boston,

Dordretch, London: Kluwer Academic Publishers, 2002.

[8] B. D. Muer and M. Steyaert, CMOS Fractional-N Synthesizers. Boston, Dor-

dretch, London: Kluwer Academic Publishers, 2003.

173

174 BIBLIOGRAPHY

[9] C. S. Vaucher, Architectures for RF Frequency Synthesizers. Boston, Dordretch,

London: Kluwer Academic Publishers, 2002, ch. 2.

[10] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma Modula-

tion in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, vol. 28,

no. 5, pp. 553–559, may 1993.

[11] T. Riley and J. Kostamovaara, “A Hybrid Σ − ∆ Fractional-N Frequency Syn-

thesizer,” IEEE Trans. Circuits Syst. II, vol. 50, no. 4, pp. 176–180, apr 2003.

[12] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters.

IEEE, Inc. New York: IEEE Press, 1997.

[13] M. Takahashi, K. Ogawa, and K. S. Kundert, “VCO Jitter Simulation and Its

Comparison With Measurement,” in Proc. IEEE ASP-DAC’99. Asia and South

Pacific Design Automation Conference, Hong Kong, Jan. 1999, pp. 85–88.

[14] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A Modeling Approach for Σ∆

Fractional-N Frequency Synthesizer Allowing Strightforward Noise Analysis,”

IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028–1038, aug 2002.

[15] M. H. Perrott, “Techniques for High Data Rate Modulation and Low Power

Operation of Fractional-N Frequency Synthesizers,” Ph.D. dissertation, Mas-

sachusetts Institute of Technology, Department of Electrical Engineering and

Computer Science, Sept. 1997.

[16] A. Fakhfakh, N. Milet-Lewis, Y. Deval, and H. Levi, “Study and behavioural

simulation of phase noise and jitter in oscillators,” in Proceedings of the 2001

IEEE International Symposium on Circuits and Systems, ISCAS 2001, vol. 5,

no. 2, may 2001, pp. 323–326.

[17] H. Taub and D. Schilling, Principles of Communication Systems. New York:

McGraw Hill, 1971, ch. 3,4.

BIBLIOGRAPHY 175

[18] J. A. McNeill, “Jitter in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 32,

no. 6, pp. 870–879, jun 1997.

[19] M. Takahashi, K. Ogawa, and K. S. Kundert, “VCO jitter simulation and its

comparison with measurement,” in Proceedings of the of the ASP-DAC apos;99.

Asia and South Pacific, vol. 1, Jan. 1999, pp. 85–88.

[20] T. P. Kenny, T. A. D. Riley, N. M. Filiol, and M. A. Copeland, “Design and

Realization of a Digital Σ∆ Modulator for Fractional-n Frequency Synthetisis,”

IEEE Trans. Veh. Technol., vol. 48, no. 2, pp. 510–521, mar 1999.

[21] W. Rhee, B.-S. Song, and A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency

Synthesizer with a 3-b Third-Order Σ∆ Modulator,” IEEE J. Solid-State Cir-

cuits, vol. 35, no. 10, pp. 1453–1460, Oct. 2000.

[22] I. C. Hwang et al., “A Σ∆ Fractional-N Synthesizer with a Fully-Integrated Loop

Filter for a GSM/GPSR Direct-Conversion Transceiver,” in Proceedings of the

Symposium On VLSI Circuits Digest of Technical Papers, 2004, pp. 42–45.

[23] H. il Lee et al., “A Σ∆ Fractional-N Frequency Synthesizer Using a Wide-Band

Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Appli-

cations,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1164–1169, jul 2004.

[24] A. M. Fahim and M. I. Elmasry, “A Wideband Sigma-Delta Phase-Locked-Loop

Modulator for Wireless Applications,” IEEE Trans. Circuits Syst. II, vol. 50,

no. 2, pp. 53–62, feb 2003.

[25] S.-Y. Lee, C.-H. Cheng, M.-F. Huang, and S.-C. Lee, “A 1-V 2.4GHz Low-Power

Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controler,” in

Proceedings of the Symposium On VLSI Circuits Digest of Technical Papers,

2005, pp. 2811–2814.

[26] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters.

IEEE, Inc. New York: IEEE Press, 1997, ch. 3.

176 BIBLIOGRAPHY


dretch, London: Kluwer Academic Publishers, 2003, ch. 6.

[28] M. J. Borkowski and J. Kostamovaara, “Spurious Tone Free Digital Delta-Sigma

Modulator Design for DC Input,” in Proceedings of the IEEE International Sym-

posium on Circuits and Systems (ISCAS’05), May 2005, pp. 5601–5604.

[29] ——, “On Randomization of Digital Delta-Sigma Modulators with DC inputs,”

in Proceedings of the IEEE 2006 International Symposium on Circuits and Sys-

tems (ISCAS’06), May 2006, pp. 3770–3773.

[30] K. Hosseini and M. P. Kennedy, “Mathematical Analysis of a Prime Modulus

Quantizer MASH Digital Delta-Sigma Modulator,” IEEE Trans. Circuits Syst.

II, vol. 54, no. 12, pp. 1105–1109, dec 2007.

[31] J. Liu, H. Liao, R. Huang, and X. Zhang, “Sigma-Delta Modulator with Feedback

Dithering for RF Fractional-N Frequency Synthesizer,” in Proceedings of the 2005

IEEE Conference on Electron Devices and Solid-State Circuits, Dec. 2005, pp.

137–139.

[32] K. Hosseini and M. P. Kennedy, “Maximum Sequence Lenght MASH Digital

Delta-Sigma Modulators,” IEEE Trans. Circuits Syst. I, vol. 54, no. 12, pp.

2628–2638, dec 2007.

[33] ——, “Architectures for Maximum Sequence Lenght Digital Delta-Sigma Modu-

lators,” IEEE Trans. Circuits Syst. II, vol. 55, no. 12, pp. 1104–1108, nov 2008.

[34] V. R. Gonzalez-Diaz and G. Espinosa, “Integrated Dithering Technique in Digital

Σ∆ Modulators for Fractional-N Frequency Synthesizers,” in Proceedings of the

2006 IEEE International Conference on Electronic Design, 2006, pp. 173–177.

[35] E. A. Lee and D. G. Messerschmitt, Digital Communication. Boston, Dordretch,

London: Kluwer Academic Publishers, 1994, ch. 12.

BIBLIOGRAPHY 177

[36] J. Wawrzynek. (2002, May) Linear feedback shift regis-

ters (lfsrs). EECS150 - Digital Design. [Online]. Available:

http://inst.eecs.berkeley.edu/ cs150/sp02/lectures/lec27-misc2-6up.pdf

[37] J. G. Maneatis and M. A. Horowitz, “Precise Delay Generation Using Coupled

Oscillators.” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273–1282, dec

1993.

[38] J. Craninckx and M. S. J. Steyaert, “A 1.8-GHz Low-Phase-Noise CMOS VCO

Using Optimized Hollow Spiral Inductors.” IEEE J. Solid-State Circuits, vol. 32,

no. 5, pp. 736–1997, may 1997.

[39] B. Razavi, Design of Analog CMOS Integrated Circuits. USA: McGraw Hill,

2001.


dretch, London: Kluwer Academic Publishers, 2003, ch. 4.

[41] K. Shu, E. Sanches-Sinencio, J. SIlva-Martınez, and S. H. K. Embabi, “a

2.4-GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-

Switching Prescaler and Loop Capacitance Multiplier,” IEEE J. Solid-State Cir-

cuits, vol. 38, no. 6, pp. 866–874, June 2003.

[42] M. Shur, Semiconductor Devices. USA: Prentice Hall, 1990, ch. 4.

[43] B. D. Muer and M. Steyaert, “A CMOS Monolithic ∆Σ-Controlled Fractional-N

Frequency Synthesizer for DSC-1800 ,” IEEE J. Solid-State Circuits, vol. 37,

no. 7, pp. 835–844, jul 2002.

[44] K. Shu, E. Sanchez-Sinencio, J. Silva-Martınez, and S. H. K. Embabi, “A

2.4GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-

Switching Prescaler and Loop Capacitance Multiplier,” IEEE J. Solid-State Cir-

cuits, vol. 38, no. 6, pp. 866–873, jun 2003.

178 BIBLIOGRAPHY

[45] “Latin American Consortium for Integrated Services,” 2006. [Online]. Available:

http://www.lacis.org/index.asp

[46] M. Souyer and R. G. Meyer, “Frequency Limitations of a Conventional Phase-

Frequency Detector,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1019–1022,

aug 1990.

Documents

“Design and Simulation Strategies for Fractional-N