Design and Harmonic Analysis of Multi Level Step Up Inverter1

8/13/2019 Design and Harmonic Analysis of Multi Level Step Up Inverter1

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Design and Harmonic analysis of Multi Level

step up inverterVeeranki. Sabari Pradeep

Koneru Lakshmaiah University, Department of Electrical and Electronics Engineering, Guntur, India

[email protected]

Abstract In this paper a multilevel inverter whoseoutput voltage can be boosted to desired voltage is

proposed. The output level depends on the value of the

modulation factor used. The modulation factor is varied

using digital modulation technique. This proposed

technique uses capacitor switching as the key concept.

This, like a normal inverter has the virtue of harmonic

reduction and also reduces the number of switches

required for operation compared to a traditional

converter

Index termsboosting, multilevel inverter, switch modeoperation. Digital modulation

I. INTRODUCTIONThe proposed inverter has two technologies blended in

it. First of it is the Multi-Level Inverter (MLI)

technology. The FOUR switch VSI is generally called

as two level inverter due to the fact that it has only two

of instantaneous phase voltages and

. In other

words phase voltages can take one of the two voltage

levels. Multi-level inverter provides an alternative to

these voltage levels. For example in a three level

inverter the output voltage levels are instantaneously

0, ,

. The complicated issue in this topology is the

switching sequence. This problem can be addressed by

use of modulating techniques.

There are usually inverter topologies which use diodes

and capacitors for obtaining the required number of

level of voltages. But due to the use of large number

of elements its size and weight increases and

complexity in design of switching circuitry. Digital

methods of modulation are the most suitable

techniques to address the problem of switching.

Another topology which provides the additional

advantage of getting the required voltage by increasing

number of simple H-bridges connected in cascade with

the Cascaded Multilevel Inverter (CMLI). The

cascaded MLI uses many H-Bridges each with a

separate source. This yields us higher voltage values,

but increases the circuit size. The output obtained is

alternating, but always less than are equal to voltage

applied. The variable input voltage required by the

inverter is supplied by a STEPUP model SMPS to

counter the use of multiple sources and multiple H-

Bridges. This paper deals with the Hybrid Multi-Level

STEP UP Inverter.

II. SWITCHED CAPACITOR STEP UPCONVERTER (SCSUC)A switched capacitor step up inverter uses capacitor

switching to boost output voltage to the required value.

This is done by charging the capacitors in parallel and

discharging them in series. The circuit of the switched

capacitor step up converter is shown in the figure-1.

When switches 1and are closed the capacitors ischarged to a voltage of for time1.

= (1)During this time switches 3 and 4 are open whenthese switches are closed the output voltage is across the load for time. = (2)

Figure 1 Step UP Converter

Here we observe as the number of capacitors increases

the output voltage also increases. This circuit can be

modified to obtain a unipolar multilevel step up

converter, which has different output levels. The

output wave form obtained is similar to that of a

cascaded inverter, but unipolar as shown in figure 3

the output of normal step up converter is shown in

figure 2.


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Figure 2 output of SUSC

Figure 3 output of modified SUSC

III. CIRCUIT DESCRIPTION ANDWORKING OF MULTILEVEL STEP

UP INVERTER

A. Circuit descriptionThe circuit shown in Fig 4 & Fig 5 is the

setup multilevel inverter which has two sections

1. Switched mode section.2. HBridge sectionSwitched mode section:

This section contains solid state devices that act as

switches. They take the role of charging the capacitors

and discharging the voltage to the next section. This

section focuses on the charging of capacitors in

parallel and discharging them in series. For a four level

inverter there are totally 9 switches, two capacitors and

a voltage source as shown in the Fig. 5 As the number

of output voltage levels increase the number of

elements also increases for a particular input.

HBridge section:

The H-Bridge inverter section is used to make the

unipolar output obtained in the first section to bipolar.

It has four switches and is similar to that of a typical

H-Bridge. The number of switches used in this section

does not depend on the number of levels of output

voltage. Hence there is only one H-Bridge for any

number of output voltage levels

B. WorkingThe switching sequence of the proposed inverter is

shown in Fig. 6 for the switch mode section. The

procedure cited below explains the inverter working in

positive half cycle when and are closed. Firstlevel of 0v is obtained by maintaining a delay of 1inswitching and. After1, Sa and Sd are closed.During, switches1,3,4, and 6 are closed tocharge each capacitor to a voltage () equal to supplyvoltage and7, 9are closed to supply the voltage of1to H-Bridge inverter. During this interval of timewe get a voltage equal to supply voltage at the output.

The interval between and 3is the period in whichswitches7,,4, 6 and8 are closed so that thecapacitor now becomes in series with source and so

the total voltage input to the H-Bridge inverter is .From 3to the switches7,,3, and8are closedto supply an input of 3. From to 6 the voltagelevels start stepping down and finally reach to a

voltage of 0v at6. The same procedure is repeated, innegative sequence but with switches and closed. Thus we obtain a multilevel boosted

alternating output voltage as shown in Fig. 7

1 = = supply voltage, = (3)

= (4)

= 2 (5)3 = 2 (6)

Figure 4 Multilevel step up inverter


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C. Mode of conduction of the proposed converterThe circuit topology of the proposed converter is

shown in Figure 4. This converter consists of dc input

voltage, power switch S, coupled inductors and, one clamp diode 1and, clamp capacitor 1,two blocking capacitors & 3, two blocking diodesand 3, output diode and, output capacitor .The coupling inductor is modeled as magnetizing

inductor and leakage inductor . To simplify thecircuit analysis the following conditions are assumed.

1. Capacitors , 3 and are large enoughthat , 3and are considered constantin one switching period.

2. The power MOSFETS and diodes areconsidered as ideal, where as the parasitic

effect of the power switched is considered.

3. The coupling coefficient of the coupledinductor k is equal to +and turns ratio of

the coupled inductor is equal to.

Continuous conduction mode (CCM) operation

During this time interval ( 1) S is turned on andthe diodes 1, and 3 are turned off, and isturned on. The motor current path is show in the fig 5.

The primary side current of the coupling inductor is increased linearly, the magnetizing inductor stores its energy from the dc voltage . Due toleakage inductor

, the secondary side current of the

coupling inductor is decreased linearly. The voltageacross the secondary side winding of the coupled

inductor and blocking voltages and 3 areconnected in series to charge the output capacitor and to provide the energy to the load R. when the

current has become zero, dc source begins tocharge capacitors and 3via the coupled inductor.When is equal to at = 1 this operatingends.

Figure 5 continuous conduction mode (mode1)

Mode 2:

During this time interval, S is still turned on. Diodes

1and are turned off, and and 3are turned on.The current-flow path is shown in Fig.6. The

magnetizing inductor stores energy from dc source

. Some of the energy from DC source transfersto the secondary side of the coupled inductor to chargethe capacitors and 3. Voltages and 3 areapproximately equal to . Output capacitor provides the energy to load R. This operating mode

ends when switch S is turned off at = .

Figure 6 conduction process of mode 2 in

ccm

Mode 3

During this time interval, S is turned off. Diodes 1 and are turned off, and and 3are turned on. Thecurrent-flow path is shown in Fig. 7. The energies ofleakage inductor and magnetizing inductor arereleased to the parasitic capacitor of switch S. Thecapacitors and 3are still charged by the DC source via the coupled inductor. The output capacitor provides energy to load R. When the capacitor voltage

is equal to at = 3, diode3conductsand this operating mode ends.

Figure 7 conduction process of mode 3 in ccm.


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Mode 4:

During this time interval, S is turned off. Diodes 1,, and 3are turned on and is turned off. Thecurrent-flow path is shown in Fig.8. The energies of

leakage inductor and magnetizing inductor arereleased to the clamp capacitor 1. Some of the energystored in starts to release to capacitors and 3in parallel via the coupled inductor until secondary

current is equals to zero. Meanwhile, current isdecreased quickly. Thus, diodes and 3 are cut offat = 4, and this operating mode ends.

Figure 8 conduction process in mode 4 of ccm.

Mode 5:

During this time interval, S is turned off. Diodes 1and are turned on, and and 3 are turned off.The current-flow path is shown in Fig.9. The energies

of leakage inductor and magnetizing inductor are released to the clamp capacitor

1. The primary

and secondary windings of the coupled inductor, DC

sources , and capacitors and 3are in series totransfer their energies to the output capacitor andload R. This operating mode ends when capacitor 1starts to discharge at = 5.

Figure 9 conduction process in mode 5 of ccm.

Mode 6:

During this time interval, S is still turned off. Diodes

1and are turned on, and and 3are turnedoff. The current-flow path is shown in Fig.10. The

primary-side and secondary-side windings of the

coupled inductor, DC sources , and capacitors 1,, and 3 transfer their energies to the outputcapacitor and load R. This mode ends at = 6when S is turned on at the beginning of the next

switching period.

Figure 10 conduction process in mode 6 of

ccm.

IV. STUDY STATE ANALYSIS OFPROPOSED INVERTER

At modes 4 and 5, the energy of the leakage

inductor is released to the clamped capacitor1. According to previous work, the duty cycle ofthe released energy can be expressed as

1 = =(1)

+1 (7)

Where is the switching period, 1is the dutyratio of the switch, and 1is the time of modes 4and 5. by applying the voltage second balance

rule on , the voltage across the capacitor 1can be represented by

1 = 1 (1+)+(1)

(8)Since durations of modes 1, 3, and 5 are

significantly short only modes 2, 4, and 6 are

considered in CCM operation for the steady state

analysis. In the time period of mode 3, the

following equations can be written.

1 = + = (9)


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= 1 = (10)Thus the voltage across the capacitors and 3canbe written as

= 3 = = (11)During the duration of mode 5 and 6 the followingequations can be formulated

5 = 6 = 1 3 (12)Thus the voltage across the magnetizing inductor is

given by equation

15 = 16 = + + + (13)Using the voltage second balance equation on we get the following

1

1

= 0

Solving the above found equations we get

= 1+1

1(1)(1)

(14)

The schematic of the voltage gain versus the duty ratio

under various coupling coefficients of the coupled

inductor is shown in Fig. 6 It is seen that the voltage

gain is not very sensitive to the coupling coefficient.

When k is equal to 1, the ideal voltage gain is written

as

= 1+1 (15)If the proposed converter is operated in boundary

condition mode, the voltage gain of CCM operation is

equal to the voltage gain of DCM operation. From

(15), the boundary normalized magnetizing inductor

time constant can be derived as = (1)(1+)(1+) (16)

Figure 11 Simulink model of the proposed

inverter

Figure 12 Gate pules to the switches of the

proposed inverter


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Figure 13 output voltage of the inverter with

R load

Figure 14 output of the inverter with RL load

V. SIMULATION USING MATLABFor an input of 230 V, if the switching sequence

described above is followed for the proposed circuit

then we obtain a voltage of 690V alternating at the

output as shown in the Fig. 7 at no load. For a resistive

load of R=100 and inductive load of R=100 , L=

0.001 H, the output waveforms are shown in Fig. 8,

Fig. 9 & Fig. 10 respectively

Figure 9 voltage output of R-L load

Figure 10 current output of the RL load

VI. HARMONIC STUDY OF MULTILEVELSTEP UP INVERTER WITH RL LOAD.

As the output wave for is symmetric it has no evenharmonics. Total harmonic distortion (THD), odd

harmonics components, percentage of fundamental

component are the components of interest. FFT

analysis of the proposed inverter voltage wave is

shown in figure 11.

Figure 11 FFT analysis of output voltage

with R-L load


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The above analysis gives information about the

harmonics present in the output. It is observed that the

output fundamental has a peak voltage of 628.1V. The

third, fifth and seventh harmonic components are

9.05%, 5.16% and 9.54% respectively.

VII. CONCLUSIONMultilevel inverters are known for their virtues. Sothe concept of multilevel inverters blended with switch

mode converter technology yields a good outcome that

can replace the cascaded converter. It has the added

advantage of reduction in number of switches used

compared to other inverters when the number of levels

are increased as described in Table1. It however has

the drawback of designing complexity for gating and

capacitor design, but if deployed it can yield much

better results than other inverters.

TABLE 1

Comparison of number of switches used in CMLI

and MLSUI

S.NO Level

Switches

required

for

cascaded

MLI

Switches

required

for Step

Up MLI

1 4 12 13

2 5 16 16

3 6 20 19

4 7 24 22

5 8 28 25

6 9 32 287 10 36 31

8 11 40 34

9 12 44 37

Figure 12 graphical analysis of switches requirement

for CMLI vs. MLSUI.

VIII. REFERENCES[1] L .Tolbert and T. Habetler, ``Novel multilevel inverter

carrier-based PWM method, in IEEE Trans. IndustryApplications, 35(5), 10981107 (1999).

[2] G. Walker and G. Ledwich, Bandwidth considerations

for multilevel converters, IEEE Trans. Power Electronics

14(1), 7481 (1999).

[3] Y. Liang and C. Nwankpa, A new type of STATCOM

based on cascading voltage-source inverters with phase-shifted unipolar SPWM, IEEE Trans. IndustryApplications 35(5), 11181123 (1999).

[4] N.Schibli, T.Nguyen, and A.Rufer, A three-phase multilevel converter for high-power induction motors IEEETrans. Power Electronics 13(5), 978986 (1998).

[5] J. Lai and F. Peng, Multi level convertersA new breedof power converters, IEEE Trans. Industry Applications 32(3), 509517 (1997).

[6] S. Halaacute; sz, A. Hassan, and B. Huu,Optimalcontrol of three level PWM inverters, IEEE Trans.

Industrial Electronics 44(1), 96106 (1997). 268 J.Espinoza

[7] R. Menzies, P. Steiner, and J. Steinke, Five-level GTOinverters for large induction motor drives, in IEEE Trans.

Industry Applications 30(4), 938944 (1994).

[8] R. P. Severns and G. Bloom, Modern DC-to-DCSwitchmode Power Converter Circuits, Van Nostrand

Reinhold Company, New York, 1985.

IX.

BIBILOGRAPHY

V. Sabari Pradeep pursued his

Bachelor of Technology degree

from Koneru Lakshmaiah

University in Electrical and

Electronics Engineering. His

research interests include power

electronic converter design, 3 D

Space vector modulation, Artificial

Intelligence, etc.

0

20

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raphical analysis ofswitch requirement

Switches required for cascaded MLI

Switches required for Step Up MLI

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Design and Harmonic Analysis of Multi Level Step Up Inverter1