IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 2, MAY 1996 265

Design and Fabrication of a CMOS Signal Conversion Integrated Circuit

for Remote Control Hobbvists J

Larry T. Wurtz

Abstract-The availability of low-cost VLSI (very large scale integration) design software and fabrication services for design, simulation, and layout of integrated circuits has become readily accessible to universities for classroom instruction. The design and fabrication of a CMOS integrated circuit is described, which converts an eight-bit digital signal to a pulse-width modulated (PWM) signal and vice versa for radio control hobbyist trans- ceivers and motor servos. This example design serves to describe a subset of VLSI design tools from the University of California, Berkeley, the University of Washington, and Microelectronics Center of North Carolina and MOSIS fabrication services avail- able for classroom instruction.

I. INTRODUCTION LSI (very large scale integration) design software and ac- V cess to fabrication services has become readily available

to universities for classroom instruction at very low cost. The greatest investment in establishing and maintaining a VLSI de- sign capability is associated with workstation-level computer facilities on which most VLSI design, simulation, and layout software executes. Workstation-level computer facilities, such as Sun and IBM, have, however, become commonplace in engineering programs and consequently, can provide shared support for VLSI design with little extra real costs.

This paper illustrates the availability and potential of low- cost VLSI design software and fabrication services for class- room instruction by describing the design of a custom inte- grated circuit. The function of the custom IC is to convert an eight-bit digital signal to a pulse-width modulated (PWM) signal and vice versa for radio control (WC) hobbyist trans- ceivers and motor servos. The function to be implemented in integrated form is simple and straightforward, yet complex enough to support a thorough VLSI design experience at the senior undergraduate level. Previously reported VLSI design experiences can be found in [ l l , [21, and [31.

The VLSI design software described in this paper is a very small subset of available VLSI design tools and, consequently, should by no means be considered complete. The point is to show that a handful of inexpensive software tools is really all that is needed to provide a good VLSI design experience.

Most VLSI design software is currently supported on a wide variety of workstation platforms. At The University of

Manuscript received November 3, 1992; revised April 10, 1993. The author is with the University of Alabama, Department of Electrical

Publisher Item Identifier S 001 8-9359(96)04254-9. Engineering, Tuscaloosa, AL 35487-0286 USA.

Alabama, a network of IBM RS6000 Model 320 and 520 workstations have provided an excellent platform for our VLSI design environment. Specifically, the following software tools were used to create the custom IC and can be obtained from the addresses given. The circuit simulators NETLIST, PRESIM, and RNL are available from the NW Laboratory for Integrated Systems, Department of Computer Science, University of Washington, Seattle, WA [4]. The layout editor MAGIC, EXT2SIM and EXT2SPICE file conversion utilities, CIF2PS package for generating laser print output, and CIFP utility for generating plots were obtained from the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA[5]. The Circuit Analyzer with Macromodeling software package, CAZM, was provided by the Microelectronics Center of North Carolina, Research Tri- angle Park, NC [6]. Information on MOSIS fabrication and NSF funding to cover the fabrication costs can be obtained from The MOSIS Service, USC Information Sciences Institute, Marina del Rey, CA [7].

The paper begins with an overview of RJC hobbyist trans- ceivers and motor servo components followed by a functional description of the digital-to-PWM signal conversion IC. The VLSI software tools used for design, simulation, and layout are described. The architecture of the digital-to-PWM IC is discussed. The paper concludes with a description of the fabri- cation process using The MOSIS Service and final comments.

11. RADIO CONTROL SYSTEMS FOR HOBBYISTS

Radio control (WC) of model aircraft and vehicles for hobbyist was started in the 1930’s. The majority of R/C systems are used for controlling the flight of model airplanes. Other applications include R/C cars and motorboats. Model airplanes, for example, vary in size from one pound in weight with a one-foot wing span to over 50 pounds with 15-foot wing spans.

A typical transceiver system with motor servos is shown in Fig. 1. The operator controls the model from a transmitter using control sticks. A miniature receiver is built into the model which receives signals from the transmitter. The action of the control sticks is sent through the transmitter and receiver to motor servos located in the model, which translate stick movement into the desired mechanical movement.

Because R/C systems are widely available at a low cost, they are often used for many applications which require mechanical

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266 IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 2, MAY 1996

Fig. 2. PWM signal sent to each servo.

Mode 0 - PWM to Digltal 1 - Dlgltal t o PWM

lMHz C l k PWM Slgnal

CONVERTER 4 I Eight-bit Digital Signal

Fig. 1. A typical WC transceiver system with servos. Fig. 3. R/C signal conversion IC block diagram

movement and remote control. Fig. 1 shows large, high thrust servos for heavy duty mechanical applications and regular size servos for smaller tasks. The motor servos provide precision, fast, high torque, low power mechanical movement which have many practical applications.

The receiver controls servo movement by a CMOS compat- ible PWM signal. Fig. 2 shows the signal seen by each servo. The PWM signal period is 20 msecs with the active-high pulse width varying from 1 to 2 msecs for full servo movement. The servo is powered by a 5 V source. With past projects, many applications have been found for remote control without servo movement and for mechanical movement without re- mote control. An Intel 8748H single-chip microcomputer with timing software has been used to generate the PWM signal for servos and demodulate the PWM signal from the receiver into a digital signal. The example IC will provide a simple alternative to using a microcomputer for signal conversion. The custom IC will, for example, generate a PWM signal of 20 msec period with active-high pulse width varying linearly from 1 msec to 2 msecs as the input eight-bit digital signal varies from zero to FF hexidecimal.

Fig. 3 shows a functional diagram of the IC. In mode 1, the IC will convert an eight-bit digital input to a PWM signal for servo control. In mode 0, a PWM signal from the WC receiver will be demodulated to an eight-bit digital output for digital system applications. To simplify the design, a 1 MHz clock signal was applied externally to the custom IC, rather than fabricate the clock source on chip. Single component, crystal- controlled, TTL compatible clock sources can be purchased for a couple of dollars. This design example is an electronic hobbyist’s “dream” chip and provides a thorough, easy-to-test VLSI design experience.

111. VLSI DESIGN SOFTWARE

Fig. 4 shows the relationship between the VLSI design tools used to create the custom IC. NETLIST is a network description language for VLSI circuits. Circuits and systems to be simulated are described as networks of sized transistors by a macro-based language. Resistors, capacitors, transistor

threshold voltages, propagation delays, etc. may be represented by the description language. Circuit descriptions are placed in .NET extension files. The NETLIST software package converts .NET files to .SIM files. PRESIM is a NETLIST pre- processor for the RNL VLSI circuit simulator which converts .SIM files to binary files for RNL. RNL is an interactive timing and logic simulator for VLSI circuits [4]. Although initially designed for NMOS circuits, RNL may be used to simulate CMOS circuits. With each RNL simulation step of duration specified by the user, RNL reports specified output values as either TTL high, low, or undefined. An undefined node value implies that the voltage level at a node is between the TTL high and low voltage thresholds. Inputs may be modified interactively with each simulation step. An RNL simulation is usually performed before any layout work begins to verify circuit functionality and to size transistors for satisfactory output drive.

MAGIC is an interactive editor for VLSI layout [5]. In particular, MAGIC supports NMOS and CMOS process tech- nologies. MAGIC has a simple command set and provides design rule checking (DRC) concurrently during layout. The simplicity of the MAGIC command set and interactive DRC allows students to quickly master circuit layout.

The next step is to layout the circuit with MAGIC. To minimize fabrication costs, a 2-pm N-well CMOS process was selected. The MOSIS Service provides a very low cost 2- pm A-well CMOS fabrication option called Tinychip [7]. With Tinychip, the designer is allowed a die size of 2250 by 2220 pm which includes 40 prelocated input, output, and tristate pads. The designer may relocate pad types to minimize signal path lengths, as long as bonding locations remain unchanged. Fig. 5 shows the Tinychip pad assignments and empty area in which the custom circuit is to be placed. Information about bonding pads may be downloaded from the MOSIS automated mail system. The automated mail syntax and address may be obtained from the MOSIS address given above.

Referring to Fig. 4, two routes may be selected to simulate the circuit layout. MAGIC generates an extracted file with .EXT extension consisting of active and passive component

WURTZ: DESIGN AND FABRICATION OF CMOS SIGNAL CONVERSION

MOSIS Fabrica

.EXT File

W W Fig. 4. Relationship between VLSI design software.

VDD Input, Output, Tri-state Pads GND

0 2220 urn

Fig. 5. Tinychip input, output, and tristate pad layout

areas. The EXT2SIM conversion package may be used to convert the .EXT file format to .SIM file format for RNL simulation. The EXT2SPICE file conversion package con- verts the extracted file to a SPICE file format [5]. The completed circuit layout consisted of 1066 enhancement- mode N-channel MOSFET’s and 1 134 enhancement-mode P-channel MOSFET’s. Traditional SPICE simulators have difficulty converging with this number of transistors. CAZM, a table-based, SPICE-like simulator, however, provides results with SPICE accuracy on very large circuits [6]. CAZM is able

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to quickly and accurately simulate large MOSFET circuits by taking advantage of the fact that a large number of MOSFET’s are of equal size and, consequently, have identical charge and current characteristics. These MOSFET’ s are represented in CAZM with charge and current tables, rather than with tra- ditional mathematical models. Accordingly, CAZM provides fast and accurate results.

It is very important to always simulate the circuit layout from input to output bonding pads to determine the effect of capacitances and resistances associated with the physical layout. Because RNL is a logic-level simulator, its output timings are not as accurate as those obtained from CAZM. However, RNL quickly verifies that all connections have been properly made in the layout.

MAGIC creates a file with .CIF extension, California In- termediate Format, which serves three purposes in our VLSI design environment. The .CIF file is electronically transferred to MOSIS for fabrication. Plotted output of circuit layouts are facilitated by conversion of the .CIF file to plotter format with the CIFP file conversion utility [5]. Although CIFP will support a wide variety of plotter formats, HPGL plotter formats are generated for our HP table-top plotter. A utility program called HPSHADE was written to modify HPGL files for shade and crosshatch enhanced plots. HPSHADE may be obtained from The University of Alabama. High quality laser prints of circuit layouts are possible with the CIF2PS file conversion utility [SI. CIF2PS converts .CIF files to postscript files for laser print. Fig. 5, for example, is a CIF2PS laser print output.

Iv. DESIGN OF THE R/c SIGNAL CONVERSION IC

Fig. 6 shows the FUC signal conversion circuit schematic. Again, two operational modes are provided. Mode 1 converts an eight-bit digital input signal to a PWM output signal for servo control and mode 0 performs the reverse function for

26X IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 2, MAY 1996

%i!%!P~ Fig. 6. R/C signal conversion IC schematic.

D A T A I N

TEST

SCANIN

C L K

IC A>B PAD

RESET I

1 Fig. 7. Two-phase static flip-flop with scan-path testing.

1 I I

' I "T2 I I

RESET : T

CLK I - I

I I I I

TEST I - RESET TEST CLK

I CINi COUTi :

Fig. 8. Counter bit cell

remote control of digital applications. The IC is placed in mode 0 or 1 by setting the mode pad at GND or VDD, respectively.

Again, to simplify the design, the clock source was not integrated on chip, but rather applied externally. The lowest

frequency, single-component clock source which is commer- cially available provides a 1 MHz clock signal. The divide- by-eight subcircuit shown in Fig. 6 drops the extemal clock frequency to 125 kHz for a 4 psec clock step. With inter-

269 WURTZ: DESIGN AND FABRICATION OF CMOS SIGNAL CONVERSION

Fig. 9. Two -phase static flip-flop layout.

Fig. 10. Full-adder constructed with standard gates.

nal clock step? of 4 psecs, timing works out very nicely, in that, 250 clock steps provides a 1 msec delay. 5000 clock steps provides the complete 20 msec PWM signal period. The 13-bit synchronous binary counter with outputs BO through B12 is sufficient for a count to 5000, or 20 msec delay.

In mode 1 , 250 decimal, or 1 msec, is added to the input eight-bit digital signal by the adder subcircuit labeled Adder1 . The adder output on signal lines SO through S8 provides timing for the active-high PWM output signal; in that, while the binary counter output, BO through B8, is not greater than the adder output, SO through S8, the comparator output, A > B, pulls the output PWM signal level high. After the counter output increments above the adder output, the PWM signal level drops low. When 20 msecs has elapsed, the counter output is equal to 5000 decimal, or 1388 hexidecimal, and a pulse is created by gates 1 4 to reset the binary counter. The process repeats to provide 50 motor servo updates each second.

In mode 0, while the incoming PWM signal is active-high, the binary counter is allowed to count in 4 psec clock steps. As the PWM signal becomes active-low, the binary counter output is latched at register Reg1 and the binary counter is reset. One msec is subtracted from the latched counter value by adding -250 decimal with adder Added. When the PWM

signal level rises to start a new 20 msec period, the adder output in range 0 to 250 decimal is latched by register Reg2 and is routed to the eight-bit digital output. Accordingly, the digital output is updated every 20 msecs.

The divide-by-eight and 13-bit binary counters are based on the two-phase static flip-flop shown in Fig. 7. This structure was selected because of its low transistor count and uncom- plicated clock strategy [SI. Although information is held as charge on nodes 1 and 2 during clock transitions, the flip-flop is basically a static structure. Accordingly, students need not be concerned with the complexities of charge redistribution and timing associated with dynamic structures which are normally involved in minimal transistor designs. The static flip-flop has been modified to allow selection of a test data input called Scanin by raising the test signal. Series connection of the flip-flops, where the Scanin signal input is connected to the previous flip-flop’s Q output, supports scan-path testing. Scan-path testing has become an important ASIC test method throughout industry [9].

The counters are synchronous designs which are built by cascading the basic counter bit cell shown in Fig. 8. This cell is created by adding transmission gates T1 and T2 to the two- phase static flip-flop of Fig. 7 for proper selection of the data input signal, datain [ 101. Layout of the counter bit cell of Fig. 8 is shown in Fig. 9. Additionally, the registers shown in Fig.

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Fig. I I . Complex CMOS full-adder gate.

6 are formed by connecting the two-phase static flip-flops of Fig. 7 in parallel. Scan-path testing is facilitated by connecting output Q of each flip-flop to the Scanin input of the next flip- flop. As with the counter layouts, the register layouts are very regular in structure.

The regularity of basic structures has been emphasized throughout the custom IC so that the layout of larger VLSI structures is a simple task of arraying basic cells. The result is a very regular, well organized layout that promotes testability, reliability, quick design, and area efficiency.

The adders of Fig. 6 are created by a simple connection of full-adders in ripple-carry fashion [lo], [ l l ] . This ad- dition scheme is certainly not as quick as carry-lookahead arrangements; but, adder performance is not a critical issue with this design. The layout area limitation associated with the Tinychip fabrication option, however, is a concern. A number of VLSI texts show the full-adder circuit constructed from a set of standard CMOS gates, as shown in Fig. 10 110]-[14]. To reduce the transistor count for reduced layout area, the full-adder was implemented as a complex CMOS gate shown in Fig. 11. The full-adder layout is shown in Fig. 12.

The comparator cell of Fig. 6 was formed from the basic cell shown in Fig. 13. A and B bit inputs, to be compared, control the cell function by turning the appropriate transmission gates on and off. This design is a classic pass-transistor structure where NMOS transistors have been replaced with transmission gates to improve the noise margin [8]. Series connection of the basic cell forms the complete comparator shown in Fig. 14.

The pass-transistor structure offers a tremendous savings in layout area compared to the alternative design consisting of exclusive-or gates. The comparator cell layout is shown in Fig. 15.

To complete the scan-path connections, the scanin, Si, and scanout, So, signals of each component are connected serially as shown in Fig. 6. The first Si and last So signals are connected to input and output pads, respectively. All test control signals are connected to the test input pad. Testing by scan-path is perfomed by selecting test mode, shifting in bit patterns via the scanin pad and system clock. The IC is clocked in nontest mode. Modified bit patterns are shifted out of the IC via the scanout pad by clocking the IC in test mode. Accordingly, the procedure enhances controllability and observability of the IC internal structures.

The scan-path test procedure, although very thorough, re- quires additional equipment to generate input test bit patterns and process output test bit patterns. To simplify testing and promote the educational experience, the large number of pads provided with Tinychip allowed many of the internal buses and signals to be routed directly off chip. Direct accessibility of internal signals allowed inspection of internal chip function with a logic analyzer and oscilloscope.

v. FABRICATION OF THE R/c SIGNAL CONVERSION IC

The custom IC was fabricated by The MOSIS Service, which is a prototyping service offering fast-turnaround of standard cell and full-custom VLSI circuits. The MOSIS methodology allows the merging of many different projects

WURTZ: DESIGN AND FABRICATION OF CMOS SIGNAL CONVERSION 27 1

Fig. 12. Full-adder layout.

from various organizations onto a single wafer. Consequently, instead of paying the costs of mask making, fabrication, and packaging for a complete fabrication run, MOSIS users pay only a fraction of the cost. Although practically all industry standard process technologies are supported, the 2 pm CMOS process has the lowest cost per die area.

The Tinychip fabrication option was chosen for the example IC, because of its low cost of roughly $450 for a set of four prototype chips. As mentioned earlier, this process is 2 pm N - well CMOS with a standard 40-pad frame. A standard frame implies that bonding pad locations are defined to facilitate an automated bonding and packaging process.

The custom IC was fabricated by submitting its MAGIC .CIF file to the MOSIS automated electronic mail system. Both information and submission of IC’s are handled by electronic mail messages conforming to standard template formats. The automated system parses messages for keywords and needed information to satisfy the request [7].

Submitting a .CIF file for fabrication involves a sequence of messages. To start a fabrication task, the first message requests a project identification number and selects the process technology and bonding pad arrangement. After a project identification number has been assigned, the .CIF file is submitted in a mail message to MOSIS for a design rule check (DRC). The DRC insures that the IC layout conforms to the most up-to-date technology constraints. If the DRC is

successful, the designer may request fabrication. Otherwise, a corrected .CIF file must be resubmitted. During fabrication, the designer may request information by using the status message template.

Complete interaction with the MOSIS mail system from project identification request through DRC to placing the design in the fabrication queue required 1.5 days. Prototype IC’s were received within one month. Fig. 16 shows a labeled microphotogragh of the custom IC. Although the IC was designed for operation with an external clock frequency of 1 MHz, testing showed the IC to be completely operational at 20 MHz.

VI. CONCLUSION

For classroom instruction, many VLSI design software packages are available for only the costs associated with shipping and handling of magnetic tapes and documenta- tion. All of the referenced software, for example, was ob- tained for less than $500. Most VLSI design software is supported on a wide variety of workstations, which are be- coming as common in universities as IBM PC’s. The MOSIS Service with NSF funding provides an excellent fabrication outlet. Consequently, it has become affordable to offer a good VLSI design experience for at least the CMOS process technology.

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c1-c1 c2-c2 c3 - c3 c 4 - c 4 c5 COMPARATOR COMPARATOR CUMPARATOR COMPARATOR COMPARATOR

C E L L C E L L C E L L C E L L C E L L Dl-.Dl D2-D2 D3 ~ D3 D4-04 D 5--

Fig. 13. Comparator cell circuit schematic.

BO A 0 B1 A1 B2 A 2 B3 A 3

- D9 D8-D8 D7-DD7 D6 - D6 D 5 - COMPARATOR

C E L L A>B- C 9 C8-C8

Fig. 14. Comparator subsystem

COMPARATOR COMPARATOR COMPARATOR C E L L C E L L C E L L

c7-c7 C6-C6 c5

B VDD

Fig. 15. Comparator cell layout.

The complexity of the R/C signal conversion IC is suffi- cient to fill the layout area provided by the low-cost Tiny- chip option. At The University of Alabama, design, simu- lation, and layout of functions with similar complexity are appropriate for a senior-level undergraduate VLSI design course.

In addition, many companies that offer extensive com- mercial VLSI design packages are very happy to support universities. Normally associated with elaborate VLSI design software, such as Mentor Graphics or Compass, is a monthly maintenance fee of a couple hundred dollars. The low main- tenance fee associated with industry standard VLSI design

WURTZ DESIGN AND FABRlCATION OF CMOS SIGNAL CONVERSION

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Fig. 16. Microphotograph of the WC signal conversion IC.

software, however, is certainly worth the investment to provide an advanced VLSI design experience.

REFERENCES

E. Sicad, A. Rubio, and K. Kinashita, “A VLSI design system for teaching introduction to microelectronics,” IEEE Trans. on Educ., vol. 35, no. 4, pp. 311-320, Nov. 1992. W. Wolf, “Synthesis tools help teach systems concepts in VLSI design,” IEEE Trans. Educ., vol. 35, no. 1, pp. 11-17, Feb. 1992. R. Williams, “An undergraduate VLSI CMOS circuit design laboratory,” IEEE Trans. Educ., vol. 34, no. 1, pp. 47-51, Feb. 1991. VLSI Design Tools Reference Manual, Re1 3.2, NW Laboratory for Integrated Systems, University of Washington, Sept. 1988. 1986 VLSI Tools: Still More Tools by the Original Artists, Computer Science Division, University of California, Dec. 1985. D. J. Erdman and D. J. Rose et al., CAZM: Circuit Analyzer with Macromodeling. ver. 4.1. MCNC Center for Microelectronics and Duke University, June 1990. MOSIS User Manual, Re1 3.1, Univ. of Southern California, 1988 N. Weste and K. Eshraghian, Principles of CMOS VLS1 Design, A Systems Perspective. M. E. Levitt, “ASIC testing upgraded,” ZEEE Spectrum, pp. 26-29, May 1992.

Reading, MA: Addison-Wesley, 1988.

[lo] M. M. Mano, Computer System Architecture, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1982.

[l I] F. J. Hill and G. R. Peterson, Computer Aided Logical Design With Emphasis on VLSI, 4th ed.

[I21 L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.

[13] D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits, 2nd ed.

[I41 R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI Design Techniques for Analog and Digital Circuits.

New York: Wiley, 1993.

New York: McGraw-Hill, 1988.

New York: McGraw-Hill, 1990.

Larry T. Wurtz received the M.S. and Ph.D. degrees in electrical engineering in 1985 and 1988, respectively, from Auburn University, Auburn, AL. He received the B.S. in computer science in 1982 from Troy State University, Troy, AL.

He is presently an Assistant Professor of Electrical Engineering at The University of Alabama, Tuscaloosa, AL. His research interests are in the areas of analog and digital discrete and integrated circuit and system design, computer system architecture and design, microprocessor and microcontroller- based computer system design and layout, fault-tolerant system design and analysis, RF digital and analog system design, power electronics, high-speed data acquisition, and neural networks.