Design & Verification Challenges for 3G/3.5G/4G Wireless Baseband

Design & Verification Challenges for 3G/3.5G/4G Wireless Baseband MPSoCs

Michael Speth

Herbert Dawid

Frank Gersemsky

Infineon Technologies AG

Duisburg, Germany

Page 2Copyright © Infineon Technologies 2008. All rights reserved. 03.07.2008

Outline

challenges of 3G / 4G modem design

data throughput

latency

configurability

wireless standards: a nightmare for system verification

keys to success:

architecture

methodology

team-setup


State of the Art Cellphone Platform

A Heterogeneous Application Specific Multi-Processor SoC

Focus: Digital Baseband


Example: Infineon MP-EH Platform

Customer Demands:

1. Functionality

2. Platform BOM

3. Power Consumption


Why Dedicated Wireless MPSoCs?

Thought Experiment: Modern digital cellular baseband

¬ 20 GOPs peak signal processing demand (active)

¬ 0 GOPs computational demand (standby, paging)

¬ State of the art battery with 1400 mAh capacity

What if we use 2 general purpose processors (like the ones in your desktop PC), assuming they would be powerful enough?

¬ 60 W peak power consumption

¬ 20 W standby power consumption

Result

Active Time: 40 s

Standby Time: 30 min

We are building SoCs which are 100-1000x more energy efficient than state of the art GP processors and at the same time more efficient, faster, smaller and cheaper


Throughput


Wireless Data Rate Evolution

1992 2000 2004 20121

Bit

s p

er s

eco

nd

1996 2008

HSDPA

Digital Voice

Multimedia Messaging,Medium-Speed,Packet Data

802.llag802.lln

Bluetooth

UMTS

GSM

3G2G

Broadband Multimedia,Broadcast Video,High-Speed Packet Data

4G

802.llb

UWB

106

109

LTE

CELLULARCELLULAR

Doubling Every 16 Months !

Source: C. Drewes, Infineon

NOMADIC/WLANNOMADIC/WLANMAN / LAN / PANMAN / LAN / PAN


How to Address the Challenge

“Shannon beats Moore”

Increasing gap between chip technology and throughput requirements

Architecture + Algorithm

2G: DSP Centric Architectures

3.XG: + Dedicated HW Centric Architectures

4G : + More Efficient Transmission Technology (OFDM)

Throughput requirements are extremely tough

but can be met with state of the art

architectures + methodology


Latency Requirements


Network <-> Modem InteractionNetwork View

MRC MRC

Radio Network Controller

Radio Network Controller

Base Stations

ClosedLoop

TransmitDiversity

Highly advanced Signal Processing Algorithms plus Radio Link Adaptation and fast Scheduling


Network <-> Modem Interaction Digital Baseband Architectural View

3G R

F F

ron

ten

d

3G Tx Modulator

3G Inner Receiver

3G Tx Framing & Channel Coding

3G Outer Receiver

Cell Search

Delay Profile Estimation

Layer 2/3 Stack (MAC, RLC, RRC)

Layer 1 Schedulers, FSMs, Drivers

Modem Core SW Layer 1 Schedulers, FSMs, DriversDL Power Control

Physical Layer Re-Config

Intra-Frequency MeasurementsHSDPA HARQ (ACK/NACK) & CQIHSUPA HARQ (ACK/NACK)

Soft HandoverAGC

Sync.

HSUPA E-DCH E-TFC Selection

Data L1 Config/Ctrl System Information/Higher Layer Ctrl

Transport Channel Reconfig

TFCI


Example: 3G Power control

Data2Data1

*1,2 The SIR measurement periods illustrated here are examples. Other ways of measurement are allowed to achieve accurate SIR estimation.

*3 If there is not enough time for UTRAN to respond to the TPC, the action can be delayed until the next slot.

Data1TPC

Data1TPC

PILOTPILOT

PILOT

ResponseTo TPC (*3)

TPC

DL SIRmeasurement (*1)

PILOT TFCI TPC

DL-UL timing offset (1024 chips)

Slot (2560 chips)

PILOTPILOT Data2Data1TPC

PILOTPILOT TFCI TPC

Slot (2560 chips)

Propagation delay

UL SIRmeasurement (*2)

Responseto TPC

DL DPCCHat UTRAN

Propagation delay

DL DPCCHat UE

UL DPCCHat UTRAN

UL DPCCHat UE

512 chips

TFCI

TFCI

Latency + Reconfiguration dominates system architecture

Deterministic Scheduling is a must

System Requirements must be known to the deepest detail


System Configurability


Example: UMTS TX

TX accountsonly for a few percent of

silicon area + functionality


source coding Modulation

TX Processing for UMTS Rel. 6

Coding +Interleaving~ 300

Parametersframe/subframe

Modulator:~ 70

Parametersframe / slot

FW Config

extremely timingcritical RX / TX

interaction


System Configurability

3G Transmitter:

Well defined serial bit processing

But: parameter flow can exceed data-flow

3G Receiver: much much more complicated

Multiple Base Stations, Soft Handover, Transmit Diversity

Multiple Rake Fingers, Receive Diversity

Complex Reconfigurations

Additional Neighbor Cell BCH

No exhaustive test possible

Even minimum testing leads to thousands of complex test-cases


System Development and Bringup

Exhaustive verification impossible

Flexibility required for very late changes

ChipDevelopement

SystemBringup

IOT LiveNetwork

SW integration

Algorithmissues

HW issues

SW issues


Architecture


System Design Paradigms

System Predictability

Localized FunctionalityDivide and Conquer: Cluster Functionality

Self-Contained HW & FW Blocks

Localized Functionality, Lean Interfaces

Simplified Integration & Verification

Sometimes Extra HW Needed

Divide and Conquer: Cluster FunctionalitySelf-Contained HW & FW Blocks

Localized Functionality, Lean Interfaces

Simplified Integration & Verification

Sometimes Extra HW Needed

Limited HW-SW InteractionHW-SW Split: Encapsulate Functionality in HW

HW-SW Interface Natural Boundary for Function Clusters

Latency Critical Paths in HW

Simplified SW Scheduling

No Critical HW-SW Interactions

Configuration Granularity: UMTS Slot (667 µs) and Frame (10 ms) Boundaries

Simplified Verification

HW-SW Split: Encapsulate Functionality in HWHW-SW Interface Natural Boundary for Function

Clusters

Latency Critical Paths in HW

Simplified SW Scheduling

No Critical HW-SW Interactions

Configuration Granularity: UMTS Slot (667 µs) and Frame (10 ms) Boundaries

Simplified VerificationPerformance vs Complexity

Flexibility Where NeededAlgorithm Design:

Robust and “As Good As Needed”Algorithm Design:

Robust and “As Good As Needed”

Static real-time scheduling based on Worst Case Execution Times (WCETs)


Digital Baseband Detailed Architecture

RAM

µC (RTOS, Layer 1 SW + Protocol Stack)

P P

Chip Control HW Peripherals

RAM/ROM

Bus Interface

IRQ Reset

Signal Processing HW Peripherals/DSPs

Bus Interface

IRQ Reset

Signal Processing HW Peripherals/DSPs

Data Path Bus

Bus Interface

IRQ Reset

Signal Processing HW Peripherals /DSPs / ASIPs

Control Bus System

Separate functionality into autonomous subsystems


HW

CE FWCV

System Architecture Concept

“System View“ Required (Cross-Layer, -Functional, -Disciplinary)

HW/SWArchitecture

Concept/AlgorithmDesign

Requirements

Synthesis & Layout

ProductionTest

HW/SWIntegration

SystemIntegration

Compliance& IOT

SW DesignFine Architecture& VP Model

RTL Design

VP

Platform

Con-current Development

split up development in parallel streams

one team for each HW-Processing element

cross-functional setup

system level oriented flow for each sub-component:


Team & Project Setup

interdisciplinary teams:

Concept & Algorithms

HW development

SW development

System verification

interdisciplinary teams:

Concept & Algorithms

HW development

SW development

System verification

SW & FW Develop-ment

Chip Development & Verification

Architecture& Algorithm Design

Block level design & verif.

Architecture refinement

HW/FW codesign

System integration

Block level design & verif.

Architecture refinement

HW/FW codesign

System integration

jointresponsibility


Methodology


Key Methodology: Virtual Prototype

System architects

explore/evaluate chip architectures

by simulation

early proof of concept

System testersearly availability

sophisticated debugging features

no pcb-limitation

SW developersearly SW integration on virtual hardware

no pcb-limitation

HW designersreference for verification(Executable

Specification)

VP


Methodology: Bridging Levels of Abstraction

3GPPstandard

verification

algomodel

code generation

interfacedescription

code generation

HW model

verification

SW

verification

VP

fastHW model

TestConfig

verification

test / regression system


Methodology

VP is the essential vehicle for system integration and verification

Integrated tool landscape to provide maximum reuse

Seamless transition between different levels of abstraction

Platform for cross-functional team interaction

Provide uniform touch-and-feel throughout all project phases

methodology

team setup /processes

system architecture


Conclusion

Wireless SoC design is one of the biggest challenges in the industry

Greatest challenge:

System reconfigurability

Latency critical loops

Not data-throughput

Success requires a system-level approach:

Exhaustive and detailed system knowledge

Interdisciplinary teams

Integrated design and verification flow

Documents

Design & Verification Challenges for 3G/3.5G/4G Wireless Baseband