Description Registri Apz 30 33

8/2/2019 Description Registri Apz 30 33

1/23

DESCRIPTION 3/1551-CNZ 214 012 Uen A

ERROR INTERRUPT INFORMATION FIGURES

Contents

1 Error signal principles

2 Registers2.1 ACKER-A2.2 ACKER-B2.3 ADER0-7

2.4 ASAPAR12.5 CACCR

2.6 CWSR

2.7 EIRH0-212.8 EIRL0-212.9 EMR2.10 ERR-A2.11 ERR-B2.12 ERTR0-72.13 IMDSER

2.14 IMMAER2.15 IMPRSERH

2.16 IMPRSERL2.17 IMSLER

2.18 INF

2.19 INF02.20 INF12.21 MAMAER2.22 MASLER02.23 MASLER12.24 MISR2.25 MWSR

2.26 PCWSR2.27 PDECI

2.28 PDECS2.29 RPMR2.30 RPSR0

2.31 RPSR12.32 SMMAER2.33 SMSLER2.34 SRSCR2.35 SSMAER

2.36 SSRPER2.37 SSSLER

2.38 SYER0-72.39 UBSLER2.40 WSM02.41 WSM12.42 WSS02.43 WSS1

1 Error signal principles
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E~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.3#CHAPTER2.3http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.3#CHAPTER2.3http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.4#CHAPTER2.4http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.4#CHAPTER2.4http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.5#CHAPTER2.5http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.5#CHAPTER2.5http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.6#CHAPTER2.6http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.6#CHAPTER2.6http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.7#CHAPTER2.7http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.7#CHAPTER2.7http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.8#CHAPTER2.8http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.8#CHAPTER2.8http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.9#CHAPTER2.9http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.9#CHAPTER2.9http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.10#CHAPTER2.10http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.10#CHAPTER2.10http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.11#CHAPTER2.11http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.11#CHAPTER2.11http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.12#CHAPTER2.12http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.12#CHAPTER2.12http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.13#CHAPTER2.13http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.13#CHAPTER2.13http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.14#CHAPTER2.14http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.14#CHAPTER2.14http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.15#CHAPTER2.15http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.15#CHAPTER2.15http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.16#CHAPTER2.16http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.16#CHAPTER2.16http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.17#CHAPTER2.17http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.17#CHAPTER2.17http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.18#CHAPTER2.18http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.18#CHAPTER2.18http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.19#CHAPTER2.19http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.19#CHAPTER2.19http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.20#CHAPTER2.20http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.20#CHAPTER2.20http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.21#CHAPTER2.21http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.21#CHAPTER2.21http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.22#CHAPTER2.22http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.22#CHAPTER2.22http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.23#CHAPTER2.23http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.23#CHAPTER2.23http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.24#CHAPTER2.24http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.24#CHAPTER2.24http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.25#CHAPTER2.25http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.25#CHAPTER2.25http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.26#CHAPTER2.26http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.26#CHAPTER2.26http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.27#CHAPTER2.27http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.27#CHAPTER2.27http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.28#CHAPTER2.28http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.28#CHAPTER2.28http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.29#CHAPTER2.29http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.29#CHAPTER2.29http://c/DOCUME~1/05324920/LOCALS~1/Temp/ALEX_TMP/1006/alex0140.htm#CHAPTER2.30#CHAPTER2.30http://c/DOCUME~1/05324920/LOCALS~1/T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2/23

DSC 0-7 IPC MAI (POWC) AMU(DAC MODE) /---------\ /---------\ /-------\/ - - -\ |/-------\|IPCDERR| |SLE-A | |SLE-B

/------\ ||IMPRSER||>----->| |>---->| |------->||IMDSER || | | | |||ERTR|| |\-------/| IMMAE | |MAE-A | |MAE-B|\----/||DHDSSLE |/-------\|>----->| |>---->| |------->||IMSLER || |/-------\| | || || |\-------/| ||MASLER0|| |/-----\|| |/ |/-------\| |\-------/| ||ERR-A||\------/ ||IMMAER || IMSLE | | |\-----/|

|\-------/|>----->| |PHE-A | |PHE-B\---------/ | |>---->| |----->|\-------/| | |

|\-------/| | |VOE-A | |VOE-B\---------/ | |>---->| |----->||MAMAER ||CLKE-A| |CLKE-B|\-------/| |\-------/|>---->| |----->| | | ||\-------/| | | | |\---------/ | | | |

RHC 0-15 SSC | |BTE-A | |BTE-B/ - - \ /---------\ | |>---->| |----->| || | |\-------/| | ||/---\ || |/-------\| SSMAE | |||EIR| | ||SSMAER ||>----->| ||\---/ || |\-------/| | || | |/-------\| SSRPE | || ||> - - - >||SSRPER ||>----->| || |/ |\-------/| | |\------/ \---------/ | |

VOE RPHM0-1| |---------->| |

SMPERR | |/----->| |>--\| \---------/ |\--------------------/

CP SIDE A CP SIDE B

2 Registers

2.1 ACKER-A

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | | | | | | |\---------------------------------------------------------------/

RECRDY ENDSDP DATPR
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CPRES RUNSDP MAINTCPRES CPU restart acknowledge errorDATPR Data preservation acknowledge errorENDSDP Stop side determining programRECRDY Reconfiguration ready

acknowledge error

RUNSDP Start side determining programMAINT Maintenance interruptacknowledge error

2.2 ACKER-B

The bit disposition is the same as for acker-a.

2.3 ADER0-7

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| |\---------------------------------------------------------------/

DSABB31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16/---------------------------------------------------------------\| - - | | |\---------------------------------------------------------------/

DSBAB DSABDSAB DS Ram AddressDSBAB DS Bank Address

2.4 ASAPAR1


IAB31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16

/---------------------------------------------------------------\| | |\---------------------------------------------------------------/

IL BN

BN Block number IA Next instruction address

IL Instruction length

2.5 CACCR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | - | | | |\---------------------------------------------------------------/

XWRI-B XWRI-A SBAASBAA SB access allowed

XWRBI-A Inhibits access from CP-A againstAMU registers

XWRBI-B Inhibits access from CP-B against
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AMU registers

2.6 CWSR

B7 B6 B5 B4 B3 B2 B1 B0

/---------------------------------------------------------------\| - | - | - | | | | | |\---------------------------------------------------------------/

FMMAN FM AEX SBS-B1 SBS-B0AEX A-side executiveFM Fault markedFMMAN Manually fault markedSBS-B0 Stand-by substate bit 0SBS-B1 Stand-by substate bit 1SB-side substate SBS-B1,B0 :00 separated (SE)01 halted (HA)10 updating (UP)

11 working (WO)

2.7 EIRH0-21

For a serial or parallel RPB type RPH:

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | |\---------------------------------------------------------------/

RPBS0_EIR RPBS1_EIR RPHB_EIR0 RPHB_EIR1

B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16/---------------------------------------------------------------\| | | | |\---------------------------------------------------------------/

RPBP0_EIR RPBP1_EIR SCGS_EIR0 SCGS_EIR1B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32/---------------------------------------------------------------\| | | | |\---------------------------------------------------------------/

EXC_EIR0 EXC_EIR1 SGC_EIR0 SGC_EIR1EXC_EIR0 Executive control error register, bus 0

EXC_EIR1 Executive control error register, bus 1

RPBP0_EIR Parallel RPB port error register, bus 0

RPBP1_EIR Parallel RPB port error register, bus 1RPBS0_EIR Serial RPB port error register, bus 0

RPBS1_EIR Serial RPB port error register, bus 1RPHB_EIR0 RPHB interface error register, bus 0

RPHB_EIR1 RPHB interface error register, bus 1SCGS_EIR0 Serial signal control error register, bus 0

SCGS_EIR1 Serial signal control error register, bus 1SGC_EIR0 Parallel signal control error register, bus 0

SGC_EIR1 Parallel signal control error register, bus 1

For an IPN type RPH:
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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | |\---------------------------------------------------------------/

DMAC_DEIR RPHBI_DEIR RXF_DEIRB31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16

/---------------------------------------------------------------\| | | - |\---------------------------------------------------------------/

MHF_EIR XC_EIRB47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32

/---------------------------------------------------------------\| | | | |\---------------------------------------------------------------/

DMAC_EIR RPHBI_EIR RXF_EIR TXF_EIRDMAC_DEIR DMA control detailed error register

DMAC_EIR DMA control error registerMHF_EIR Message handling function error register

RPHBI_DEIR RPHB interface detailed error register

RPHBI_EIR RPHB interface error registerRXF_DEIR Receive FIFO detailed error register

RXF_EIR Receive FIFO error registerTXF_EIR Transmit FIFO error registerXC_EIR Cross Connection error register

2.8 EIRL0-21

For a serial or parallel RPB type RPH:

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | |\---------------------------------------------------------------/

RPBS1_DEIR RPHB_DEIR IBC_DEIRB31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16

/---------------------------------------------------------------\| | | | |\---------------------------------------------------------------/

RPBP0_DEIR RPBP1_DEIR SGCS_DEIR RPBS0_DEIRB47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32

/---------------------------------------------------------------\

| | | | |\---------------------------------------------------------------/

IBC_EIR RHC_INTNL_EIR EXC_DEIR SGC_DEIREXC_DEIR Executive control detailed error registerIBC_EIR Internal bus control error register

IBC_DEIR Internal bus control detailed error registerRHC_INTNL_EIR RHC external block error registerRPBP0_DEIR Parallel RPB port detailed error register, bus 0

RPBP1_DEIR Parallel RPB port detailed error register, bus 1RPBS0_DEIR Serial RPB port detailed error register, bus 0

RPBS1_DEIR Serial RPB port detailed error register, bus 1RPHB_DEIR RPHB interface detailed error registerSGC_DEIR Parallel signal control detailed error registerSGCS_DEIR Serial signal control detailed error register
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For an IPN type RPH:

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - |\---------------------------------------------------------------/

B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16/---------------------------------------------------------------\| - |\---------------------------------------------------------------/

B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32/---------------------------------------------------------------\| | | | - |\---------------------------------------------------------------/

TXF_DEIR MHF_DEIR XC_DEIRMHF_DEIR Message handling function detailed error registerTXF_DEIR Transmit FIFO detailed error register

XC_DEIR Cross connection detailed error register

2.9 EMR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | | | | - | | | |\---------------------------------------------------------------/

PHEI-B MAEI-B SLEI-B PHEI-A MAEI-A SLEI-AMAEI Match error inhibit

The reaction on a match error signalis inhibited.

PHEI Program handling error inhibitThe reaction on a program handling errorsignal is inhibited.

SLEI Side locating error inhibitThe reaction on a side-locating errorsignal is inhibited, in other words SLE,VOE-CPU and CLKE are inhibited.

2.10 ERR-A

B7 B6 B5 B4 B3 B2 B1 B0

/---------------------------------------------------------------\| - | | | | | | | |\---------------------------------------------------------------/

PAE-M BTE MAE PHE CLKE VOE-CPU SLEBTE Correctable bit errorCLKE Clock error

A CPU clock error has been recorded.MAE Match error

A match error between the CPU sideshas been recorded in MAMAER in CPU.

PAE-M Parity error on data from CP to MAU.PHE Program handling error

An error signal for a program handling

error has been recorded.SLE Side locating errorA side locating error has been recordedin MASLER in the CPU.


7/23

VOE-CPU Voltage error in CPUAn error signal which indicates powerfailure in the CPU.

2.11 ERR-B

The bit disposition is the same as for ERR-A.

2.12 ERTR0-7

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/

B7 B6 B5 B4 B3 B2 B1 B0

B0 Bank error ADC refresh errorB1 Address parity 0

B2 Address parity 1B3 Data parity 0

B4 Data parity 1B5 Bank error DACB6 DS uncorrectable data errorB7 Correctable data error ECC

2.13 IMDSER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | | |\---------------------------------------------------------------/

DSDHBAB DSDHCDERRDSDHBAB Data store to data handler bank

address busDSDHCDERR Data store to data handler

correctable data error

2.14 IMMAER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | | | | | | | |\---------------------------------------------------------------/

IQDE1MAE IPCMAE DSOUTMAE IPSPMAEIQDE0MAE DSINMAE SPIPMAEDSINMAE DS to DSH match errorDSOUTMAE DSH to DS match errorIPCMAE IPU control signal match errorIPSPMAE IPU to SPU match errorIQDE0MAE Destination data bus 0 match errorIQDE1MAE Destination data bus 1 match error

SPIPMAE SPU to IPU match error
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2.15 IMPRSERH

B47 B46 B45 B44 B43 B42 B41 B40 B39 B38 B37 B36 B35 B34 B33 B32/---------------------------------------------------------------\| | |\---------------------------------------------------------------/

PSMHDC PSSYNBB50 B49 B48/-----------\| | |\-----------/

PSMHDCPSCDERR

PSCDERR PRSU to IMAI correctable dataerror on reads from PRS

PSMHDC PRSU memory handler access typePSSYNB PS syndrome bus data

2.16 IMPRSERL


PRSAB

B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16/---------------------------------------------------------------\| | |\---------------------------------------------------------------/

PSSYNB PRSABPRSAB PRS address bus data. Bit 26indicates that the SRAM hasbeen accessed.

PSSYNB PS syndrome bus data

2.17 IMSLER

B3 B2 B1 B0/-----------------------------------\| | | | |\-----------------------------------/

DSDBPERR ICM0PERRICM1PERR CMPERR

B7 B6 B5 B4/-----------------------------------\| | | | |\-----------------------------------/DSDERR DSHERR

DSCONFERR DSHSPIERR

B11 B10 B9 B8/-----------------------------------\| | | | |

\-----------------------------------/L2TAGPERR PRSDERR

PRSOAERR JAMPERR
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9/23

B15 B14 B13 B12/-----------------------------------\| | | | |\-----------------------------------/RMDEERR PSBPMPERR

RMPERR PSOCDPERR

B19 B18 B17 B16/-----------------------------------\| | | | |\-----------------------------------/SIMEMPERR SIDBPERR

SICBPERR RMSRCERR

B23 B22 B21 B20/-----------------------------------\| | | | |\-----------------------------------/RWRDB0PERR STSWODBPERR

STSWIDBPERR ISMEMPERRB26 B25 B24/--------------------------\| | | |\--------------------------/

PDE-IDHL2CDERR RWRDB1PERR

CMPERR Parity error in microprogram control memoryDHL2CDERR DSCM parity errorDSCONFERR Configuration error in DSDSDBPERR Data parity error on data bus DSH,DSDSDERR Side locating error detected in DS set by:

-DSH reflected interface parity errorSet when the reflected parity bits generatedby DSU on the received signals DSAB (RAMaddress bus), DSBAB (Bank and board addressbus) and DSOB (Order bus), are not equal tothe expected parity bits, which have beengenerated by DSH.

or-Parity error on write dataDSU checks incoming parity against generatedodd parity on write data. An error sets DHDSSLEwhich is sent to DSH together with read data

DSHERR Internal error detected in DSDSHSPIERR Interface error between DSH and IQCICM0PERR Parity error in IDEC control memory 0ICM1PERR Parity error in IDEC control memory 1ISMEMPERR IPU to SPU memory parity errorJAMPERR Parity error in JAML2TAGPERR TAG-data parity error in L2 cachePDE-I Program detected errorPRSDERR Detected and uncorrectable error in PRSPRSOAERR Over addressing error in PRSPSBPMPERR BPM parity errorPSOCDPERR OCDBATM parity errorRMDEERR Destination address error in RMRMPERR Parity error in RM

RMSRCERR Source address error in RMRWRDB0PERR Remote write databus lower parity errorRWRDB1PERR Remote write databus upper parity error


10/23

SICBPERR Parity error on SICB or IPU-SPU status busSIDBPERR Parity error on SIDBSIMEMPERR SPU to IPU memory parity errorSTSWIDBPERR State switch input data bus parity errorSTSWODBPERR State switch output data bus parity error

2.18 INF

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | | | | |\---------------------------------------------------------------/

IQCND1 IQCND0 IPMAE IPSLEIPMAE IPC match errorIPSLE IPC side locating errorIQCND0 Jump taken for executed conditional

jump in position 0IQCND1 Jump taken for executed conditional

jump in position 1

2.19 INF0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0- ------------------------------------------------------------\

| | -- | -- | | | | | |- ------------------------------------------------------------/

IQMITDB IQV0 IQCND0 | IQJMP | IPSLEIPEXTRIG IPMAE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/------------------------------------------------------------ -|\------------------------------------------------------------ -

IQMITDBB35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24

/-----------------------------------------------------------\| -- | -- | |\-----------------------------------------------------------/

IQDE0ABIPEXTRIG IPC external trigIPMAE IPC match error signalIPSLE IPC side locating error signalIQCND0 IQC conditional signal 0IQDE0AB IQC destination address bus 0IQJMP IQC ASA jump signalIQMITDB IQC MIT data busIQV0 IQC valid signal

2.20 INF1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0- ------------------------------------------------------------\

| | -- | -- | | | | | |- ------------------------------------------------------------/

IQMITDB IQV1 IQCND1 | IQJMP | IPSLE

IPEXTRIG IPMAEB23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/------------------------------------------------------------ -|


11/23

\------------------------------------------------------------ -IQMITDB

B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24/-----------------------------------------------------------\| -- | -- | |\-----------------------------------------------------------/

IQDE1ABIPEXTRIG IPC external trigIPMAE IPC match error signalIPSLE IPC side locating error signalIQCND1 IQC conditional signal 1IQDE1AB IQC destination address bus 1IQJMP IQC ASA jump signalIQMITDB IQC MIT data busIQV1 IQC valid signal

2.21 MAMAER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | - | | | |\---------------------------------------------------------------/

SSMAE SMMAE IPMAEIPMAE IPC match error.

A match error between the CPU-IPUsides has been recorded in IMMAERin IPC.

SMMAE SMC match errorA match error between the CPU-SPUmaster sides has been recorded inSMMAER in SMC.

SSMAE SSC match error.A match error between the CPU-SPUslave sides has been recorded inSSMAER in SSC.

2.22 MASLER0

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/MABPERR CTBPERR SMPERR SSRPE SSSLE SMSLE UBSLE IPSLE

CTBPERR CTB parity errorIPSLE IPC side locating error

A side locating error signal hasbeen recorded in IMSLER.

MABPERR MAB parity errorSMPERR SPU to MAI parity error

This signal is activated when MAIdetects a parity error on the orderbus between SPU and MAI (SMOB), oron the data bus (SMDB)

SMSLE SMC side locating errorA side locating error signal hasbeen recorded in SMSLER

SSRPE SSC RPH parity errorA side locating error signal hasbeen recorded in SSRPER


12/23

SSSLE SSC side locating errorA side locating error signal hasbeen recorded in SSSLER

UBSLE UBC side locating errorA side locating error signal hasbeen recorded in UBSLER

2.23 MASLER1

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | - | - | - | |\---------------------------------------------------------------/

VOEALSRPHMVOEALSRPHM Voltage error in RPHM

2.24 MISR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | - | - | - | - | - | - |\---------------------------------------------------------------/MIST-B MIST-A

MIST-A/B Maintenance Interrupt Signal TestWhen MIS is sent to CPU-A/B, thebit is set to one. Writable onlyto "0"

2.25 MWSR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/MAUBSY CLKEMAU ACMB ACM-A

MAUERR VOE-MAU ACM-B AAMAAM AMU active modeACM-A AMU check mode from CPU-A sideACM-B AMU check mode from CPU-B sideACMB AMU check mode from both sidesCLKEMAU Clock error in MAU

MAUBSY MAU is busyMAUERR MAU internal errorVOE-MAU Voltage error in MAU

2.26 PCWSR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | - | | | | | |\---------------------------------------------------------------/RECREQ FM PSBS-B1

FMREQ FMMAN PAEX PSBS-B0

FM Fault markedFMMAN Manually fault markedFMREQ Fault marked requestPAEX Pre A-side executive


13/23

PSBS-B0 Pre stand-by substate bit 0PSBS-B1 Pre stand-by substate bit 1RECREQ Reconfiguration requestSB-side substate PSBS-B1,B0 :00 Separated (SE)01 Halted (HA)

10 Updating (UP)11 Working (WO)

2.27 PDECI

Error detecting part in routine test:

H'1 DS read testH'2 Unused DS test

H'3 BPM address testH'4 OCDBAT testH'5 L2C address testH'6 PS DRAM address testH'7 PS SRAM address testH'8 BPM data testH'9 PS DRAM data testH'A PS SRAM data testH'B L2C data testH'C PS DRAM read testH'D PS SRAM read testH'E L2C read testH'F BPM read testH'10 OCDBAT read testH'11 Unused PS test

H'12 Instruction exercise

H'13 RM read testH'14 RM pler testH'15 RM R1 R2 testH'16 RM RMAR testH'17 RM OBAB testH'18 LMU register read test

H'19 LNKR address testH'1A LNKR data testH'1B Unused DS test

H'1C JAM read testH'1D JAM address testH'1E Jump and sig testH'1F IA trace test

H'20 CM checksum test

H'21 Subvar testH'22 Address calculation testH'23 SW supervision test

H'24 ATU,IQC test

DS data testH'30 Board 0H'31 Board 1H'32 Board 2
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14/23

H'33 Board 3H'34 Board 4H'35 Board 5H'36 Board 6H'37 Board 7

DS address testH'38 Board 0H'39 Board 1H'3A Board 2H'3B Board 3H'3C Board 4H'3D Board 5H'3E Board 6H'3F Board 7

Error detecting part in side determining test program:

H'100 PS OCDBAT address test

H'101 PS L2C address testH'102 PS SRAM address testH'103 PS DRAM address test

H'104 RM PLER address testH'105 RM R1 R2 address test

H'109 LNKR address testH'10A LNKR data testH'10B LNKR supervision test

H'10C JAM data parity testH'10D JAM address test

H'10E JAM jump recording testH'10F IATR0 and IATR1 data test

H'110 CM checksum testH'111 ICM checksum test

H'112 Subvariable testH'113 Variable address calculation test

using index and pointer

H'114 ALU testH'115 LMU testH'116 ATU and IQC test

H'120 - H'127 DRS address testH'130 - H'13F Spare

2.28 PDECS

Background test Master:

H'2001 - H'2027 MKU updating and verification testH'2028 - H'2034 JBMU updating and verification testH'2035 - H'2035 JBM updating and verification testH'2036 - H'203B IPI updating and verification test

H'203C - H'2041 SMUM updating and verification testH'2042 - H'2042 STIM updating and verification test

Background test Slave:


15/23

H'A001 - H'A020 SKU updating and verification testH'A021 - H'A02A RPIU updating and verification testH'A02B - H'A031 RPMU updating and verification testH'A032 - H'A039 RSIU updating and verification testH'A03A - H'A03A RPM updating and verification testH'A03B - H'A03C SMUS updating and verification test

H'A03D - H'A03D STIS updating and verification test

Other error Master:

H'701 CPT interrupt but no signal in FIFOH'702 CPT signal corruptH'703 WaitForSlaveReply has timed outH'704 Parity error when reading SPIB

Other error Slave:

H'8701 RPIM full

H'8702 RPOM fullH'8703 RPIM over addressingH'8704 RPOM over addressingH'8705 IRCM overflowH'8706 RJCM overflowH'8707 Update EMG bit error (XMPI 98 and XMPI 99)H'8708 RPH stop fault during MALH'8709 RPH stop faultH'870A Timeout during RPH initialization

RPHB_Config signalH'870B Timeout during RPH initialization

RPHB_Start signalH'870C RPHI order resulted in an unexpected error

H'870D Number of RPBHs in RPBH_Config signal toolargeH'870E RP que handling faultH'87FF MIP fault

Recovery test Master:

H'2101 - H'2125 MKU recovery testH'2126 - H'2132 JBMU recovery testH'2133 - H'2133 JBM recovery testH'2134 - H'2139 IPI recovery testH'213A - H'213F SMUM recovery testH'2140 - H'2140 STIM recovery test

Recovery test Slave:

H'A101 - H'A120 SKU recovery testH'A121 - H'A12D RPIU recovery testH'A12E - H'A141 RPMU recovery testH'A142 - H'A149 RSIU recovery testH'A14A - H'A14C RPM recovery testH'A14D - H'A14F SMUS recovery testH'A150 - H'A150 STIS recovery test

Recovery test Master/Slave:

H'21F5 Test nr returned when an RP blocked signalcaused a match error

H'21F6 Test nr returned when an RP ack blocked signal


16/23

caused a match errorH'21F7 Program error in IPU SDPH'21F8 Illegal slave interruptH'21F9 General error during malrecovH'21FA Preservation fault in MALDATA during

recovery

H'21FB Restore fault in MALDATA during recoveryH'21FC Error in SDMP in SPU slaveH'21FD Resending to an RP caused a match errorH'21FE RP soft error signal is discovered after

finishing malrecovH'21FF SDP clean-up failed

2.29 RPMR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | |

\---------------------------------------------------------------/RPMR_MAE_RPBHNO

RPMR_MAE_RPBHNO This register is frozen when a matcherror occurs. The register containsinformation about the responsibleRPBH which caused the mismatch betweenthe CP sides.

2.30 RPSR0

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | | - | - | - | - | |\---------------------------------------------------------------/

RPSR_RPHECH RPSR_RPHIINFRPSR_RPHECH Error information channel (bit 6-0 of

2nd RPHB word)RPSR_RPHIINF Error information copied from the

error information time slot

2.31 RPSR1

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

/---------------------------------------------------------------\| - | - | - | - | - | - | - | - | - | - | - | - | |\---------------------------------------------------------------/

RPSR_TSNORPSR_TSNO The faulty channel on which the error

was received

2.32 SMMAER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |

\---------------------------------------------------------------/ISSBMAE JBMUMAE MCMABMAE RESBMMAE

SIBMAE ISDBMAE JBMDBMAE CNDMMAECNDMMAE Match error on branch condition


17/23

ISDBMAE Match error on IPU to SPU data BusISSBMAE Match error on IPU to SPU status busJBMDBMAE Match error on JBM data or address

BusJBMUMAE Match error on JBM write/strobe

signal

MCMABMAE Match error on control memoryaddressRESBMMAE Match error on result busSIBMAE Match error on SPU to IPU outgoing

bus

2.33 SMSLER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/

RPJBDPERR IVTMMPERR OPBMPERR UMMPERRJBPMPERR JBMDPERR MCMAPERR OPAMPERR

B15 B14 B13 B12 B11 B10 B9 B8/---------------------------------------------------------------\| - | - | | | | | | |\---------------------------------------------------------------/

SMDPERR SIDPERR ISDPERRPDESM ISHPERR ISSPERRISDPERR Parity error on IPU to SPU data busISHPERR Parity error on IPU SPU handler busISSPERR Parity error on IPU to SPU statusIVTMMPERR Parity error on IVTM memoryJBMDPERR Parity error on JBM data bus

JBPMPERR Parity error on JBM pointer memoryMCMAPERR Parity Error on control memoryOPAMPERR Parity error on operand A busOPBMPERR Parity error on operand B busPDESM Program detected error SPU masterRPJBDPERR Parity error on RP to JBM data busSIDPERR Parity error on SPU to IPU data busSMDPERR Parity error on SPU-MAI data busUMMPERR Parity error on update and match bus

2.34 SRSCR

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | |\---------------------------------------------------------------/

PROGEPROGE Set by MAS-SW if program error

is detectedB7-B1 Used by MAS software

2.35 SSMAER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | | | | | | |\---------------------------------------------------------------/


18/23

RPHIOMAE SCMABMAE RESBSMAERPMUMBMAE RPHIINMAE CNDSMAERESBSMAE Match error on result busCNDMMAE Match error on branch conditionSCMABMAE Match error on control

memory address

RPHIINMAE Match error on RPHB input directionRPHIOMAE Match error on RPHB output directionRPMUMBMAE Match error on RPIM or RPOM data,

address or control bits

2.36 SSRPER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/

RPHBLME RPHBISE RPHBFLE RSDPERR

RPHBESE RPBHE RPHBSQE RPHBCLERPBHE RPHB detected Error. An error

information time slot has beenreceived from RPHB

RPHBCLE RPHB clock errorRPHBESE Received endless signal from one RPHRPHBFLE Frame length error on frame received

from RPHBRPHBISE Information source error on time

slot received from RPHBRPHBLME Length mismatch error on signal from

RPBHRPHBSQE Sequence error on signal received

from RPHB. A non expected TSTfield has been received

RSDPERR RSDP parity Error

2.37 SSSLER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| | | | | | | | |\---------------------------------------------------------------/

IRMPERR IVTMSPERR OPBSPERR UMSPERRRPOMPERR ISHRPDPERR SCMAPERR OPASPERR

B15 B14 B13 B12 B11 B10 B9 B8/---------------------------------------------------------------\| - | | | | | | | |\---------------------------------------------------------------/

ORDERPERR OLOHMPERR TSAMPERR RPIMPERRTLIHMPERR STMMPERR RJMPERR

B23 B22 B21 B20 B19 B18 B17 B16/---------------------------------------------------------------\| - | - | - | - | | - | - | - |\---------------------------------------------------------------/

PDESSIRMPERR Parity error on IRCMISHRPDPERR Parity error on IPI to RPHI data bus

IVTMSPERR Parity error on IVTM memoryOPASPERR Parity error on operand A busOPBSPERR Parity error on operand B bus


19/23

OLOHMPERR Parity error on OLOHM1-6ORDERPERR Parity error on order in RPHIPDESS Program detected error, SPU SlaveRICRPERR Set to 0RJMPERR Parity error on RJCMRPIMPERR Parity error on RPIM

RPMDMPERR Parity error on RPM-DMU Bus,set to 0RPOMPERR Parity error on RPOMSCMAPERR Parity error on control memory

addressSTMMPERR Parity error on STMM1-2TLIHMPERR Parity error on TLIHM1-5TSAMPERR Parity error on TSAMUMSPERR Parity error on update and match

bus

2.38 SYER0-7

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| |\---------------------------------------------------------------/

B7-B0 DS Syndrome Word

2.39 UBSLER

B7 B6 B5 B4 B3 B2 B1 B0/---------------------------------------------------------------\| - | - | - | - | - | - | | |\---------------------------------------------------------------/

IPUBDBPERRUMDBPERR

IPUBDBPERR IPU to UBC Data Parity errorParity error generated in UBCon data sent on IPC to UBC bus

UMDBPERR Update and match data bus parity errorParity error generated on datareceived from UMB

2.40 WSM0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/-----------------------------------------------\| - | | | | | | - | - | | |\-----------------------------------------------/

ISRC RESP RES17P SMMAERES19P RES16P SMSLE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| - | | - | | - | |\-----------------------------------------------/

SIRC SICB ISCBB35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24

/-----------------------------------------------\| | | - | | - | | - | - | |\-----------------------------------------------/V CND CPCP_ JBIFSET JBMODE


20/23

IRQCND Branch conditionCPCP_IRQ CPCP interrupt requestISCB IPU-SPU control busISRC Read controller for ISM/ISF (transfer from

IPI to RPHI/JBM/MKU)

JBIFSET JBMU autonomous interface selection:b'000 = Autonomous mode idleb'001 = Auto mode/SIH transferb'010 = Auto mode/RPHI transferb'011 = Auto mode/ISH transferb'100 = Executive updateb'101 = Mixed mode/SIH transferb'110 = SSM transferb'111 = Mixed mode/ISH transfer

JBMODE JBMU mode selection:b'00 = Maint modeb'01 = Mipmem modeb'10 = Mixed mode

b'11 = Auto modeRES16P Parity for 16 bitsRES17P Parity for 17 bitsRES19P Parity for 19 bitsRESP Parity for 24 bitsSICB SPU-IPU control busSIRC SIM read controllerSMMAE MAE error signalSMSLE SLE error signalV Data valid, 0=valid

2.41 WSM1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/-----------------------------------------------\| - | | - | - | - | - | - | - | | |\-----------------------------------------------/

ISRC SMMAESMSLE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| - | | - | | - | |\-----------------------------------------------/

SIRC SICB ISCBB35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24

/-----------------------------------------------\| | - | - | | - | | - | - | |\-----------------------------------------------/V CPCP_ JBIFSET JBMODE

IRQCND Branch conditionCPCP_IRQ CPCP interrupt requestISCB IPU-SPU control busISRC Read controller for ISM/ISF (transfer from

IPI to RPHI/JBM/MKU)JBIFSET JBMU autonomous interface selection:

b'000 = Autonomous mode idleb'001 = Auto mode/SIH transfer

b'010 = Auto mode/RPHI transferb'011 = Auto mode/ISH transferb'100 = Executive updateb'101 = Mixed mode/SIH transfer


21/23

b'110 = SSM transferb'111 = Mixed mode/ISH transfer

JBMODE JBMU mode selection:b'00 = Maint modeb'01 = Mipmem modeb'10 = Mixed mode

b'11 = Auto modeRES16P Parity for 16 bitsRES17P Parity for 17 bitsRES19P Parity for 19 bitsRESP Parity for 24 bitsSICB SPU-IPU control busSIRC SIM read controllerSMMAE MAE error signalSMSLE SLE error signalV Data valid, 0=valid

2.42 WSS0

PHASE2 = 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/-----------------------------------------------\| - | - | | | | | | - | | | |\-----------------------------------------------/

CHT_O RES22P RES16P SSRPE SSSLERESP RES17P SSMAE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| - | - | - | | - | - | |\-----------------------------------------------/

CH_O RJCMB27 B26 B25 B24

/---------------\| | - | - | |\---------------/V CND

PHASE2 = 1

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0/-----------------------------------------------\| - | - | | | | | | - | | | |\-----------------------------------------------/

CHT_I RES22P RES16P SSRPE SSSLE

RESP RES17P SSMAEB23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| - | - | - | | - | - | |\-----------------------------------------------/

CH_I IRCMB27 B26 B25 B24

/---------------\| | - | - | |\---------------/V CND

CH_O Channel number in out direction on RPHB busCH_I Channel number in in direction on RPHB bus

CHT_O Channel type in out directionb'00 = Time slot type is SYNCH,PHASE2=0

b'01 = Time slot type is CSC (common channel),


22/23

PHASE2=0b'10 = Time slot type is DSC (dedicated channel),

PHASE2=0b'11 = PHASE2=1

CHT_I Channel type in in directionb'00 = Time slot type is SYNCH,

PHASE2=0b'01 = Time slot type is CSC (common channel),PHASE2=0

b'10 = Time slot type is DSC (dedicated channel),PHASE2=0

b'11 = PHASE2=1CND Branch conditionIRCM Current IRPMRES16P Parity on 16 bits on RESBRES17P Parity on 17 bits on RESBRES22P Parity on 22 bits on RESBRESP Parity on 24 bits on RESBRJCM Current RPJM

SL SLIH is not emptySSMAE MAE error signalSSRPE RPE error signalSSSLE SLE error signalV Data valid, 0=validWL WLIH is not empty

2.43 WSS1

PHASE2 = 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

/-----------------------------------------------\| - | - | 1 1 | - | - | - | - | - | | | |\-----------------------------------------------/

SSRPE SSSLESSMAE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| | - | | | - | - | | - | - | |\-----------------------------------------------/V OL BR TST_O RJCM

PHASE2 = 1

B11 B10 B9 B15 B14 B13 B12 B11 B10 B9 B8

/-----------------------------------------------\| - | - | 1 1 | - | - - | - | - | | | |\-----------------------------------------------/

SSRPE SSSLESSMAE

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12/-----------------------------------------------\| | - | | | - | - | | - | - | |\-----------------------------------------------/V WL SL TST_I IRCM

BR Break information for signals in out directionIRCM Current IRPMOL OLOH is not empty

RES16P Parity on 16 bits on RESBRES17P Parity on 17 bits on RESBRES22P Parity on 22 bits on RESBRESP Parity on 24 bits on RESB


23/23

RJCM Current RPJMSL SLIH is not emptySSMAE MAE error signalSSRPE RPE error signalSSSLE SLE error signalTST_O Code field of Time Slot Type for signals

in out directionb'00 = Administrative TS (SYN, IDLE, WOI,EI or BR)

b'01 = FINF TS (First Info Word of signal)b'10 = INF TS (Info Word)b'11 = LINF TS (Last Info Word)

TST_I Code field of Time Slot Type for signalsin in directionb'00 = Administrative TS (SYN, IDLE, WOI,

EI or BR)b'01 = FINF TS (Fisrt Info Word of signal)b'10 = INF TS (Info Word)b'11 = LINF TS (Last Info Word)

V Data valid, 0=validWL WLIH is not empty
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