(1/24) Confidential

Dependable Wireless Solid-State Drive (SSD)

Ken Takeuchi, Chuo University Tadahiro Kuroda, Keio University Hiroki Ishikuro, Keio University

Wireless Memory Card NAND Flash Memory

Chip

Nested Clover Coilsfor Simultaneous

Power/Data Transmission

Dat

a

Wireless Memory Card Host

HostChip

Pow

er

20µm-Thick Card Chip (Upper)

Host Chip (Lower)

700µm

Prx, Dtx in Card Chip

Ptx, Drx in Host Chip

Prx Coil

Ptx Coil

Dtx Nested Clover Coil

300µm

Drx Nested Clover Coil

20µm-Thick Card Chip (Upper)

Host Chip (Lower)

700µm

Prx, Dtx in Card Chip

Ptx, Drx in Host Chip

Prx Coil

Ptx Coil

Dtx Nested Clover Coil

300µm

Drx Nested Clover Coil

High voltage MOS(20V NAND flash process)

Area: 0.175mm2

Inductor(Interposer)

Area: 25mm2

16Gbit NAND flashBoost converter controller(0.18µm standard CMOS)

Area: 0.231mm2

Daughter board

NAND Flash memories

SSD controller

NAND Flash memory

DVLSI International Symposium 2013 (2013/12/6)

(2/24) Confidential

Objectives of Research

Wireless SSD/Memory card and its host system Robust against memory cell error, contact error, ESD,

EMI and waterproof High-speed near field wireless communication Target : 10-50Gbps at 1mm distance

Wireless power delivery with MHz load variability Target : 1-3W

(3/24) Confidential

11 ISSCC Presentations ISSCC 2014

Takeuchi “Hybrid Storage of ReRAM/TLC Flash for Cloud Data Centers” Kuroda, Ishikuro “Electromagnetic Clip Connector for In-vehicle LAN”

ISSCC 2013 Takeuichi “Unified Solid-State Storage” Kuroda, Ishikuro “A 0.15-mm-Thick Non-Contact Connector for MIPI” Kuroda “Inductive-Coupling Wake-Up Transceiver for Non-Contact Memory

Card” Kuroda “Retrodirective Transponder Array with Universal On-Sheet

Reference for Wireless Mobile Sensor Networks” ISSCC 2012

Takeuchi “Error-Prediction LDPC” Kuroda, Ishikuro “7Gb/s/Link Non-Contact Memory Module” Ishikuro “Voltage-Boosting Wireless Power Delivery System”

ISSCC 2011 Takeuchi “Asymmetric Coding for SSD” Kuroda, Ishikuro “12Gb/s non-contact interface”

(4/24) Confidential

Dependable Memory System

0.0001

0.001

0.01

0.1

1

0 5 10 15 20 25

Dat

a re

tent

ion

erro

r (a.

u.)

3Xnm

4Xnm

Time (days)

×37

Program/Erase 5000 cycles @85degC1

10-1

10-2

10-3

10-4

e-0V

0V0VVTH

Carrier ejection

0.0001

0.001

0.01

0.1

1

0 5000 10000Prog

ram

dis

turb

err

or (a

.u.)

4Xnm

2Xnm

3Xnm

1

10-1

10-2

10-3

10-4

×32

Program/Erase cycles

@RT

Carrier injection

e-

10V

VTH

×4.5

20V

Programmed cell

Disturbed cells

10V

10V

Data retention error and program disturb error become worse as the memory cell is scaled.

ECC should be improved with the device scaling.

Feature size (nm)

Acc

epta

ble

BER

of E

CC

10 30 50 70 90

512Byte codeword (BCH)

1KByte codeword (BCH)

LDPC ECC is needed.

10-1

10-2

10-3

10-4

10-5

10-6

10-7

20 40 60 80 100

(5/24) Confidential

Highly Dependable Memory System In total, >1000X reliability improvement Reliability

Improvement

20X

11X

32X

22X

17X 2009: Adaptively change ECC correctability

（IMW2010:Dynamic Codeword Transition ECC）

2010: Correct the asymmetric memory error（ISSCC2011:Asymmetirc Coding）

2011: Fast and Extremely Reliable LDPC（ISSCC2012:Error Predicting LDPC）

2012: Unified Storage System（ISSCC2013:Riverse Mirroring）

2013: Integrated Error Correction of ReRAM and Flash Memory (ISSCC 2014）

(6/24) Confidential

Asymmetric Coding (ISSCC 2011) Increase “0” for Upper page and “1” for Lower page X20 Better Reliability

Overhead

Modified data1: 0 0 1 0 0 1 1 1

Modified data2: 1 1 0 1 1 0 1 1 1 0Bit flip

Flag

Data unit1

Do NOT flip

Data unit2

e.g. Code length: 4

Asymmetric Coding

Daughter board

NAND Flash memories

SSD controller

NAND Flash memory

VTH

# of cells

1 1 0 1 0 0 1 0

1 0 error(Upper page)

0 1 error(Lower page)

e-

Data retention error : Vth decrease due to the charge leakage

(7/24) Confidential

Error Predicting LDPC (ISSCC 2012)

CG

FG

CG

FG

CG

FG

VTH1 1 0 1 0 0 1 0

# of cellse-

Compensate the capacitive interference by using the neighboring cell data

Compensate the Vth decrease during data retention by write/erase cycles and data retention time data

X11 Better Reliability

Vth decrease during data retention FG-FG interference

VTH

Vref Vref Vref

VTH

Vref1 Vref21Conventional

Proposed

(8/24) Confidential

Unified Solid-State Storage (ISSCC 2013) Unified Storage Controller integrating SSD controller and

RAID controller. Use ReRAM as NV-Cache. X32 Better Reliability

AB

CD

RAID

ABCD

ABCD

AB

EF

AR

TZ

Server 0 Server 1 Server N-1

Host

ECC, Redundancy (Mirror server)

ECC Redundancy (Mirror array/drive)

NAND flash

memory

Solid-State Drive

Redundant server

ECC, Redundancy (Spare space)

SSD controller

RAID controller

Primary Mirror

Unified storage controller

Host

ReRAM - Mirroring buffer- Parity buffer- Error-location table

(1) Reverse-mirroring (RM)(2) Error-reduction synthesis (ERS)(3) Page-RAID(4) Error-masking (EM)

NAND

ABC

NAND

ABC

Mirroring (RAID-1)Primary Mirror

(9/24) Confidential

Reverse-mirroring (ISSCC 2013)

# of cells

VTH

Lower page:Upper page:

1 1 0 01001

0

0.005

0.01

0.015

0.02

0 64 128 192 256Prog

ram

dis

turb

BER

Page number

Lower page errors

Upper page errors

W/E cycle: 10k

2Xnm0

0.01

0.02

0.03

0 64 128 192 256

2Xnm

Dat

a re

tent

ion

BER

10 hours @ 85 °CW/E cycle: 10k

Page number

Source-line side Bit-line side

Lower page

Upper page

SSLBL

Upper page

Lower page

P.D. BER

DSLWL0 WL1 WL126 WL127

Program data

Page0(Data0)

Page2(Data2)

Page252(Data252)

Page254(Data254)

Page1(Data1)

Page3(Data3)

Page253(Data253)

Page255(Data255)

SSLBL

DSL WL0WL1WL126WL127

Page254(Data1)

Page252(Data3)

Page2(Data253)

Page0(Data255)

Page255(Data0)

Page253(Data2)

Page3(Data252)

Page1(Data254)

P.D. BERLower

Upper

Lower

Upper

Primary NAND

Page #D.R

. B

ER

Mirrored NAND

Page #

D.R

. B

ERPair Pair

Write from Page0

Mirroring buffer

(ReRAM)

Page position inversion

Assign data to primary and mirror Storage to minimize errors.

Extension board for storage(NAND flash)

Storage controller

board

Extension board for storage(NVMs)

Storage controllerchip

(10/24) Confidential

Page RAID (ISSCC 2013) Storage HDD NAND (USSS)

Failure Disk(Mechanical)

Page(Bit-errors)

RedundancyScheme

RAID Page-RAID

HDD1

HDD2

HDD3

Replace

WL0

WL1

WL2

WL3

•No disk exchange•Low cost

(11/24) Confidential

Page RAID (ISSCC 2013)

1 0 1 0 1 0 0 0

1 1 0 1 1 1 0 0

0 1 1 0 1 0

XOR (Page-RAID)(BL direction)

ECC (Conv.)(WL direction)

0 0 0 1 1 1 1 0

0 1 1 0 1 0 1 0

ReRAM (Parity buffer)Write block-parity to NAND

User data

ECC(for ReRAM)

ECC

Npage -1

NAND write/erase cycle

Page#ReRAM is suitable

for parity bufferdue to large

endurance cycle.

ReRAM write/erase cycle

NAND blockNpage: Page number in a block (e.g. 256)

WL0

WL1

WL126

WL127

Block-parity

RAID optimized for flash memory, Repair failed word-line Store parity in ReRAM >X10 Better Reliability

(12/24) Confidential

Non-contact Connector

Issues and challenges - dependability (non-waterproof) - signal integrity (crosstalk, reflection) - farm factor (big, thick, heavy) - assembly (manual labor, large force)

+ non-contact + no mechanical structure + impedance controlled + easy to put on and take off

Conventional Connector Mechanical contacts

Non-contact Connector Near-field coupling

(13/24) Confidential

Transmission Line Coupler (TLC)

0 5 10 15 20 25 30 Frequency [GHz]

0

-10

-20

-30

-40 Cou

plin

g G

ain

[dB

]

L=3mm L=5mm L=7mm

L

d L

Length (L)

Port1

Port2

Width (W)

Misalignment (h) [mm] 0.6 0.4 0.2 0

W=0.4mm

h

Offset (h)

Substrate

0

-10

-20

-30

-40

(14/24) Confidential

Applications

Automotive, Computer High speed & Low error

DIMM High speed：5x（12.5Gb/s）

Multi-drop bus ISSCC2012, CICC2012

Transmission Line Coupler (TLC)

In-vehicle LAN Reduced weight : 30%

EMC ISSCC2014

SD

Memory Card High speed：50x（12Gb/s）

Low power：1/500 Sealing：waterproof

ISSCC2011, ISSCC2013

Display Thin：1/10（0.15mm）

High speed：10x（6Gb/s） Low energy：1/10（16pJ/b）

ISSCC2013

LCD

Mobile Terminal Small size & Low cost

Dependable Assembly

(15/24) Confidential

Memory Card (ISSCC2011)

10-7

BER

Data rate [Gb/s] 10-13

10-11

10-9

4 6 8 10 12 14

1mm

TLC

Delay Time [ps]

10-12

10-9

10-6

10-3

1

-40 -20 0 20 40

BER

Power Link ON

Timing Margin =0.5 UI

Power Link OFF

231-1 PRBS @ 12Gb/s

TLC

75mArms 13.56MHz

20mm x 20mm Power Link Coil

Wireless Memory Card NAND Flash Memory

Chip

Nested Clover Coilsfor Simultaneous

Power/Data Transmission

Dat

a

Wireless Memory Card Host

HostChip

Pow

er

(16/24) Confidential

LCD Module (ISSCC2013)

TLC

0.15mm-Thick

Host Board

LCD Module TLC

Frequency [GHz]

Cou

plin

g G

ain

[dB

]

2 6 8 4 10

-10

-20

-30

-40

0 -50

0

Port 4

Port 3

Port 2

Port 1

S31

S41

20dB

305 ps 2Links in one TLC 2Gb/s x 2Links =4Gb/s/coupler

(17/24) Confidential

Memory Bus (ISSCC2012, CICC2012)

DRAM

#1 #2 #3 #4 #5 Controller

TLC 0 4 8 12 16 20 0

2

4

6

8

CICC’12

ISSCC’11

JSSC’12

ISSCC’12

ISSCC’11 Num

ber o

f Mod

ules

Data Rate [Gb/s/lane]

JSSC’13

ISSCC’03

DDR4

TLC: 12.5Gb/s 5Drops

(18/24) Confidential

In-vehicle LAN (ISSCC2014) “An Electromagnetic Clip Connector for In-vehicle LAN to Reduce Wire Harness Weight by 30%” (Paper 30.6)

(19/24) Confidential

Summary: Non-Contact Connector

Automotive, Computer High speed & Low error

DIMM High speed：5x（12.5Gb/s）

Multi-drop bus ISSCC2012, CICC2012

Transmission Line Coupler (TLC)

In-vehicle LAN Reduced weight : 30%

EMC ISSCC2014

SD

Memory Card High speed：50x（12Gb/s）

Low power：1/500 Sealing：waterproof

ISSCC2011, ISSCC2013

Display Thin：1/10（0.15mm）

High speed：10x（6Gb/s） Low energy：1/10（16pJ/b）

ISSCC2013

LCD

Mobile Terminal Small size & Low cost

Dependable Assembly

(20/24) Confidential

Dependable Wireless Power Delivery System

Switch between fres, and fres/3 Small size, battery-less application Requirement : Fast load tracking and low EMI

(21/24) Confidential

Single-Channel Dual-Output WPD System

TX

fin(6.78MHz)

VOH

VOL Vref

Vref ∆Σ Controller

C1

C2

C3

CLKin

Vb

Diode Driver

Amp Buffer

Duty Controller

PRS-PWM Module

Power Controller ISSCC2012

A-SSCC2013

(22/24) Confidential

Test Chip and WPD Module

2.5mm

2.5m

m

VO

V SS

V coi

l_n

V coi

l_p

Enab

le

Switc

h

Buf

fer

VDL

PMOS

PMOS

Coupled NMOS

CLK Comp & TDC

Coil size 2cmx2cm

Resonance capacitor: 5 Smoothing capacitor: 2

(23/24) Confidential

Output voltage regulated at 16V and 8V Power efficiency: 40%

Power Efficiency and Output Regulation

POL[W] POL[W] POH[W] POH[W]

Effic

ienc

y[%

]

Out

put V

olta

ge[V

]

2.5mm

(24/24) Confidential

POH

POL

Fast Load Tracking and EMI Reduction

Load transition point

VOH(16V)

Mode control

VOL(8V)

0.157W

0.206W

0.341W

0.085W 2.5mm