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DEPARTMENT OF INFORMATION TECHNOLOGY

Question Bank

Subject Name : Digital Principles and System Design

Year / Sem : II Year / III Sem

Batch : 2011 – 2015

Name of the Staff : Mr M.Kumar AP / IT

Prepared By Verified By Approved By

Mr M.Kumar Mrs R.Punithavathi Dr. V.Parthasarathy

Asst. Professor / IT HOD / IT Principal

DIGITAL PRINCIPLES AND SYSTEM DESIGN

Unit – I

Boolean Algebra and Logic Gates

Part - A 1. Define binary logic?

Binary logic consists of binary variables and logical operations. The variables

are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having

only two distinct values: 1 and 0. There are three basic logic operations: AND, OR, and

NOT.

2. What are the basic digital logic gates?

The three basic logic gates are

AND gate

OR gate

NOT gate

3. What is a Logic gate?

Logic gates are the basic elements that make up a digital system. The electronic

gate is a circuit that is able to operate on a number of binary inputs in order to perform a

particular logical function.

4. Give the classification of logic families

5. Which gates are called as the universal gates? What are its advantages?

The NAND and NOR gates are called as the universal gates. These gates are

used to perform any type of logic application.

6. Classify the logic family by operation?

The Bipolar logic family is classified into

Saturated logic

Unsaturated logic. The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family. The Schottky TTL, and ECL logic comes under the unsaturated logic family.

7. Define Fan-out?

Fan out specifies the number of standard loads that the output of the gate can

drive without impairment of its normal operation.

8. Define power dissipation?

Power dissipation is measure of power consumed by the gate when fully driven

by all its inputs.

9. What is propagation delay?

Propagation delay is the average transition delay time for the signal to propagate

from input to output when the signals change in value. It is expressed in ns.

10. Define noise margin?

It is the maximum noise voltage added to an input signal of a digital circuit that

does not cause an undesirable change in the circuit output. It is expressed in volts.

11. Define fan in?

Fan in is the number of inputs connected to the gate without any degradation

in the voltage level.

12. What is Operating temperature?

All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which the performance of the IC is effective is called as operating temperature. Operating temperature of the IC vary from 00 C to 700 c.

13. What is High Threshold Logic?

Some digital circuits operate in environments, which produce very high noise

signals. For operation in such surroundings there is available a type of DTL gate

which possesses a high threshold to noise immunity. This type of gate is called HTL

logic or High Threshold Logic.

14. Which gate is equal to AND-invert Gate?

NAND gate.

15. Which gate is equal to OR-invert Gate?

NOR gate.

16. Bubbled OR gate is equal to NAND gate

17. Bubbled AND gate is equal to NOR gate

18. Define the term digital.

The term digital refers to any process that is accomplished using discrete units

19. What is meant by bit?

A binary digit is called bit

20. What is the best example of digital system?

Digital computer is the best example of a digital system.

21. Define byte?

A group of 8 bits.

22. List the number systems?

i) Decimal Number system

ii) Binary Number system

iii) Octal Number system

iv) Hexadecimal Number system

23. State the sequence of operator precedence in Boolean expression?

i) Parenthesis

ii) NOT

iii) AND

iv) OR

24. What is the abbreviation of ASCII and EBCDIC code? ASCII-American Standard Code for Information Interchange. EBCDIC-Extended

Binary Coded Decimal Information Code.

25. What are the different types of number complements?

i) 1‟sComplement (r-1‟s complement)

ii) 2‟s Complement (r‟s complement)

26. Why complementing a number representation is needed?

Complementing a number becomes as in digital computer for simplifying the

subtraction operation and for logical manipulation complements are used.

27. How to represent a positive and negative sign in computers?

Positive (+) sign by 0

Negative (-) sign by 1.

28. What is meant by Map method?

The map method provides a simple straightforward procedure for minimizing

Boolean function.

29. What is meant by two variable map?

Two variable map have four minterms for two variables, hence the map consists of

four squares, one for each minterm

30. What is meant by three variable map? Three variable map have 8 minterms for three variables, hence the map consists of 8

squares, one for each minterm

31. What is the use of Don’t care conditions?

Any digital circuit using this code operates under the assumption that these unused

combinations will never occur as long as the system

32. Express the function f(x, y, z)=1 in the sum of minterms and a product of

maxterms? Minterms=∑ (0,1,2,3,4,5,6,7)

Maxterms=Nomaxterms.

33. What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate?

F=xy‟+x‟y

F=xy +x‟y‟

34. What are the methods adopted to reduce Boolean function? i) Karnaugh map

ii) Tabular method or Quine mccluskey method

iii) Variable entered map technique.

35. Why we go in for tabulation method? This method can be applied to problems with many variables and has the advantage

of being suitable for machine computation.

36. State the limitations of Karnaugh map. i) Generally it is limited to six variable map (i.e.) more than six variable involving

expressions are not reduced.

ii) The map method is restricted in its capability since they are useful for simplifying

only Boolean expression represented in standard form.

37. What is tabulation method? A method involving an exhaustive tabular search method for the minimum

expression to solve a Boolean equation is called as a tabulation method.

38. What are prime-implicants? The terms remained unchecked are called prime-implicants. They cannot be reduced

further.

39. Explain or list out the advantages and disadvantages of K-map method?

The advantages of the K-map method are

i. It is a fast method for simplifying expression up to four variables.

ii. It gives a visual method of logic simplification.

iii. Prime implicants and essential prime implicants are identified fast.

iv. Suitable for both SOP and POS forms of reduction.

The disadvantages of the K-map method are

i. It is not suitable for computer reduction.

ii. K-maps are not suitable when the number of variables involved exceed four.

iii. Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or)

don‟t care terms.

40. List out the advantages and disadvantages of Quine-Mc Cluskey method?

The advantages are,

a. This is suitable when the number of variables exceed four.

b. Digital computers can be used to obtain the solution fast.

c. Essential prime implicants, which are not evident in K-map, can be clearly seen in the

final results.

The disadvantages are,

a. Lengthy procedure than K-map.

b. Requires several grouping and steps as compared to K-map.

c. It is much slower.

d. No visual identification of reduction process.

e. The Quine Mc Cluskey method is essentially a computer reduction method.

41. Define Positive Logic.

When high voltage or more positive voltage level is associated with binary „1‟ and

while the low or less positive level is associated with binary „0‟ then the system adhering to

this is called positive logic.

42. Define Negative Logic. When high voltage level is associated with binary „0‟ and whiles the low level is

associated with binary „1‟ then the system adhering to this is called negative logic.

43. List the characteristics of digital Ics i) propagation delay

ii) power dissipation

iii) Fan-in

iv) Fan-out

v) Noise margin

44. Why parity checker is needed?

Parity checker is required at the receiver side to check whether the expected parity

is equal to the calculated parity or not. If they are not equal then it is found that the received

data has error.

45. What is meant by parity bit?

Parity bit is an extra bit included with a binary message to make the number of 1‟s

either odd or even. The message, including the parity bit is transmitted and then checked at

the receiving and for errors.

46. Why parity generator necessary?

Parity generator is essential to generate parity bit in the transmitter.

47. What is IC?

An integrated circuit is a small silicon semiconductor crystal called a chip

containing electrical components such as transistors, diodes, resistors and capacitors. The

various components are interconnected inside the chip to form an electronic circuit.

48. What are the needs for binary codes?

a. Code is used to represent letters, numbers and punctuation marks.

b. Coding is required for maximum efficiency in single transmission.

c. Binary codes are the major components in the synthesis (artificial generation) of

speech and video signals.

d. By using error detecting codes, errors generated in signal transmission can be

detected.

e. Codes are used for data compression by which large amounts of data are

transmitted in very short duration of time.

49. Mention the different type of binary codes?

The various types of binary codes are,

a. BCD code (Binary Coded decimal).

b. Self-complementing code. h. The excess-3 (X‟s-3) code. i. Gray code.

c. Binary weighted code.

d. Alphanumeric code.

e. The ASCII code.

f. Extended binary-coded decimal interchange code (EBCDIC).

g. Error-detecting and error-correcting code.

h. Hamming code.

50. List the advantages and disadvantages of BCD code?

The advantages of BCD code are

a. Any large decimal number can be easily converted into corresponding binary number

b. A person needs to remember only the binary equivalents of decimal number from 0 to 9.

c. Conversion from BCD into decimal is also very easy.

The disadvantages of BCD code are

a. The code is least efficient. It requires several symbols to represent even small numbers.

b. Binary addition and subtraction can lead to wrong answer.

c. Special codes are required for arithmetic operations.

d. This is not a self-complementing code.

e. Conversion into other coding schemes requires special methods.

51. What is meant by self-complementing code?

A self-complementing code is the one in which the members of the number system

complement on themselves. This requires the following two conditions to be satisfied.

a. The complement of the number should be obtained from that number by replacing 1s with

0s and 0s with 1s.

b. The sum of the number and its complement should be equal to decimal 9. Example of a

self-complementing code is

i. 2-4-2-1 code.

ii. Excess-3 code.

52. Mention the advantages of ASCII code? The following are the advantages of ASCII code

a. There are 27 =128 possible combinations. Hence, a large number of symbols, alphabets

etc.., can be easily represented.

b. There is a definite order in which the alphabets, etc.., are assigned to each code word.

c. The parity bits can be added for error-detection and correction.

53. What are the disadvantages of ASCII code? The disadvantages of ASCII code are

a. The length of the code is larger and hence more bandwidth is required for transmission.

b. With more characters and symbols to represent, this is not completely sufficient.

54. What is the truth table?

A truth table lists all possible combinations of inputs and the corresponding outputs.

55. Define figure of merit?

Figure of merits is defined as the product of speed and power. The speed is specified

in terms of propagation delay time expressed in nano seconds. Figure of merits=Propagation

delay time (ns)* Power (mw). It is specified in pico joules (ns*mw=PJ).

Part - B 1. Simplify the following Boolean function by using Tabulation method

F (w, x, y, z) =Σ(0,1,2,8,10,11,14,15)

Determination of Prime Implicants

Selection of prime Implicants

2. Simplify the following Boolean functions by using K’Map in SOP & POS.

F (w, x, y, z) =Σ(1,3,4,6,9,11,12,14)

Find the Number of variable map

Draw the Map

Simplification of SOP & POS

3. Simplify the following Boolean functions by using K-Map in SOP & POS.

F (w, x, y, z) =Σ(1,3,7,11,15) + d(0,2,5)

Find the Number of variable map

Don‟t care treat as variable X.

Draw the Map

Simplification of SOP & POS

4. Reduce the given expression. [(AB)’ + A’ +AB] using Boolean algebra Laws and

theorems.

Use Boolean laws and theorems to simplify the expression

Use De-Morgan‟s theorem

Use associative law of Boolean function

5. Reduce the given function minimum number of literals. (ABC)1+ A

1+AC Reduce the

expression using Boolean algebra Laws and theorems

Use Boolean laws and theorems to simplify the expression

Use three variable De-Morgan‟s theorem

Use associative law of Boolean function

6. Simplify the following Boolean expression using Quine McCluskey method:

F = Σm (0, 9,15, 24, 29, 30) + d (8,11, 31) . (16)

The don‟t care minterms are included

Find minterms, binary A,B,C,D ,No of 1‟s , minterms group, index, binary A,B,C,D

All the terms which remain unchecked are PIs,Moreover one of two same

combinations is eliminated.

Prepare a PI chart to determine EPIs .

All the minterms have been covered by EPIs.

Unit – II

Combinational Logic

Part - A

1. Define Combinational circuit.

A combinational circuit consist of logic gates whose outputs at anytime are

determined directly from the present combination of inputs without regard to previous

inputs.

2. Explain the design procedure for combinational circuits

• The problem definition

• Determine the number of available input variables & required O/P variables.

• Assigning letter symbols to I/O variables

• Obtain simplified Boolean expression for each O/P.

• Obtain the logic diagram.

3. What is a half-adder?

The combinational circuit that performs the addition of two bits is called a half-

adder.

4. What is a full-adder?

The combinational circuit that performs the addition of three bits is called a half-

adder.

5. What is half-subtractor?

The combinational circuit that performs the subtraction of two bits is called a half-

sub tractor.

6. What is a full-subtractor?

The combinational circuit that performs the subtraction of three bits is called a half-

sub tractor.

7. What is Binary parallel adder?

A binary parallel adder is a digital function that produces the arithmetic sum of two

binary numbers in parallel.

8. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum

digit also in BCD.

9. Give the truth table for a half adder.

Input Output

X Y Sum ( S ) Carry ( C )

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

10. Give the truth table for a half Subtractor.

Input Output

X Y Difference (D) Borrow ( B )

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

11. From the truth table of a half adder derive the logic equation

S = X ⊕ Y

C = X . Y

12. From the truth table of a half subtractor derive the logic equation

D = X ⊕Y

B = X‟. Y

13. From the truth table of a full adder derive the logic equation

S = X ⊕ Y ⊕ Z

C = XY + YZ + XZ

14. What is code conversion?

If two systems working with different binary codes are to be synchronized in

operation, then we need digital circuit which converts one system of codes to the other. The

process of conversion is referred to as code conversion.

15. What is code converter?

It is a circuit that makes the two systems compatible even though each uses a

different binary code. It is a device that converts binary signals from a source code to its

output code. One example is a BCD to Excess3 converter.

16. What do you mean by analyzing a combinational circuit?

The reverse process for implementing a Boolean expression is called as analyzing a

combinational circuit. (ie) the available logic diagram is analyzed step by step and finding

the Boolean function

17. Give the truth table for a full Subtractor.

Input Output

X Y Bin Difference (D) Borrow ( B )

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

18. Give the truth table for a full adder.

Input Output

X Y Cin Sum ( S ) Carry ( C )

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

19. From the truth table of a full subtractor derive the logic equation

S = X ⊕ Y ⊕ Z

C = X‟Y + YZ + X‟Z

20. What are the two types of logic circuits for digital systems?

Combinational Logic circuit and Sequential Logic circuit

21. Draw the logic diagram for half adder.

22. Draw the logic diagram for the Boolean expression ((A + B) C)′D using NAND gates.

23. With block diagram show how a full adder can be designed by using two half adders and

one OR gate.

24. List the modeling techniques available in HDL.

Structural Modeling

Dataflow Modeling

Behavioural Modeling

25. Realize the half adder using equal number of OR and AND gates.

In half adder Sum =A XOR B=AB‟+BA‟)

Carry = (A‟+B‟)‟

PART B

1. Design a combinational logic circuit to convert the Gray code into Binary code

Draw the truth table for Gray code to binary code

For Each and every output draw the Karnaugh map

Simplify the Karnaugh map and get the output Boolean function

Draw the Logic Diagram

2. Draw the truth table and logic diagram for full-Adder

Draw the truth table for full adder

For Sum and Carry, draw the Karnaugh map



3. Draw the truth table and logic diagram for full-Subtractor

Draw the truth table for full subtractor

For Difference and Borrow output draw the Karnaugh map



4. Explain Binary parallel adder.

Draw the 4 bit binary adder as an example for parallel adder

Explain the function of parallel adder using full adder

Give example input and output

5. Design a combinational logic circuit to convert the BCD to Binary code

Draw the truth table for BCD code to binary code




6. Design a 4-bit binary adder/subtractor circuit.

Basic equations Comparison of equations

Design using twos complement Circuit diagram

7. Design and explain a comparator to compare two identical words.

Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0

Draw the truth table for A & B as input and A=B, A>B, A<B as outputs




8. Explain in detail the look ahead carry generator.

Draw the Block diagram of look ahead carry adder

Explain the function of look ahead carry adder

Give example inputs and outputs

Explain the way the output is generated

Unit – III

Design With MSI Devices

Part - A

1. Give the function of Multiplexer. Multiplexing means transmitting a large number of information units over a smaller

number of channels or lines.

2. What is priority encoder?

A priority encoder is an encoder that includes the priority function. The operation

of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the

input having the highest priority will take precedence.

3. Mention the uses of Demultiplexer. i) It finds its application in Data transmission system with error detection.

ii) One simple application is binary to Decimal decoder.

4. Give the function of Demultiplexer.

Demultiplexer is used in computers when a same message has to be sent to different

receivers. Not only in computers, but any time information from one source can be fed to

several places.

5. What is the function of the enable input in a Multiplexer?

The function of the enable input in a MUX is to control the operation of the unit.

6. Can a decoder function as a Demultiplexer? Yes. A decoder with enable can function as a Demultiplexer if the enable line E is

taken as a data input line A and B are taken as selection lines.

7. List out the applications of multiplexer?

The various applications of multiplexer are

a. Data routing.

b. Logic function generator.

c. Control sequencer.

d. Parallel-to-serial converter.

8. List out the applications of decoder?

The applications of decoder are

a. Decoders are used in counter system.

b. They are used in analog to digital converter.

c. Decoder outputs can be used to drive a display system.

9. List out the applications of comparators? The following are the applications of comparator

a. Comparators are used as a part of the address decoding circuitry in computers to select a

specific input/output device for the storage of data.

b. They are used to actuate circuitry to drive the physical variable towards the reference

value.

c. They are used in control applications.

10. What are the applications of seven segment displays?

The seven segment displays are used in

a. LED displays

b. LCD displays

11. List the types of ROM.

i) Programmable ROM (PROM)

ii) Erasable ROM (EPROM)

iii) Electrically Erasable ROM (EEROM)

12. Differentiate ROM & PLD’s ROM (Read Only Memory)

PLD‟s (Programmable Logic Array)

1.It is a device that includes both the decoder and the OR gates within a single IC package

2. It is a device that includes both AND and OR gates within a single IC package

3.ROM does not full decoding of the variables and does generate all the minterms

4. PLD‟s does not provide full decoding of the variable and does not generate all the

minterms

13. What are the different types of RAM?

The different types of RAM are

a. NMOS RAM (Nitride Metal Oxide Semiconductor RAM)

b. CMOS RAM (Complementary Metal Oxide Semiconductor RAM)

c. Schottky TTL RAM

d. ELL RAM.

14. What are the types of arrays in RAM?

RAM has two type of array namely,

a. Linear array

b. Coincident array

15. Explain DRAM? The dynamic RAM (DRAM) is an operating mod, which stores the binary

information in the form of electric charges on capacitors. The capacitors are provided inside

the chip by MOS transistors. DRAM cell Storage capacitor Column (sense line) Row

(control line)

16. Explain SRAM?

Static RAM (SRAM) consists of internal latches that store the binary information.

The stored information remains valid as long as the power is applied to the unit. SRAM is

easier to use and has shorter read and write cycle. The memory capacity of a static RAM

varies from 64 bit to 1 mega bit.

17. What are the terms that determine the size of a PAL?

The size of a PLA is specified by the

a. Number of inputs

b. Number of products terms

c. Number of outputs

18. What are the advantages of RAM?

The advantages of RAM are

a. Non-destructive read out

b. Fast operating speed

c. Low power dissipation

d. Compatibility

e. Economy

19. What is VHDL?

VHDL is a hardware description language that can be used to model a digital

system at many level of abstraction, ranging from the algorithmic level to the gate level.

The VHDL language as a combination of the following language.

a. Sequential language

b. Concurrent language

c. Net-list language

d. Timing specification

e. Waveform generation language.

20. What are the features of VHDL?

The features of VHDL are

a. VHDL has powerful constructs.

b. VHDL supports design library.

c. The language is not case sensitive.

21. Define entity?

Entity gives the specification of input/output signals to external circuitry. An entity

is modeled using an entity declaration and at least one architecture body. Entity gives

interfacing between device and others peripherals.

22. List out the different elements of entity declaration?

The different elements of entity declaration are:

1. entity_name

2. signal_name

3. mode

4. in:

5. out:

6. input

7. buffer

8. signal_type

23. Give the syntax of entity declaration? ENTITY

entity_name is

PORT (signal_name: mode signal_type;

signal_names: mode signal_type;

signal_names: mode signal_type;

END entity_name;

24. What do you meant by concurrent statement?

Architecture contains only concurrent statements. It specifies behavior,

functionality, interconnections or relationship between inputs and outputs.

25. What are operates used in VDHL language? There are different types of operators used in VHDL language

Logical operators: AND, OR, NOT, XOR, etc.,

Relational operator : equal to, <less than etc.,

Shift operators : SLL- Shift Left Logical, ROR- Rotate Right Logical etc.,

Arithmetic operators: Addition, subtraction etc.,

Miscellaneous operators: <= assign to etc.,

26. Define VHDL package?

A VHDL, package is a file containing definitions of objects which can be used in

other programs. A package may include objects such as signals, type, constant, function,

procedure and component declarations

27. What is meant by memory decoding?

The memory IC used in a digital system is selected or enabled only for the range of

addresses assigned to it.

28. What is access and cycle time? The access time of the memory is the time to select word and read it. The cycle time

of a memory is a time required to complete a write operation.

29. Give other name for Multiplexer and Demultiplexer.

Multiplexer is otherwise called as Data selector.

Demultiplexer is otherwise called as Data distributor.

30. What is Magnitude Comparator? A Magnitude Comparator is a combinational circuit that compares two numbers, A

and B and determines their relative magnitudes.

31. What is decoder? A decoder is a combinational circuit that converts binary information from „n‟ input

lines to a maximum of 2n unique output lines.

32. What is encoder?

A decoder is a combinational circuit that converts binary information from 2nInput

lines to a maximum of „n‟ unique output lines.

33. List basic types of programmable logic devices.

• Read only memory

• Programmable logic Array

• Programmable Array Logic

34. Explain ROM

A read only memory (ROM) is a device that includes both the decoder and the OR

gates within a single IC package. It consists of n input lines and m output lines.

Each bit combination of the input variables is called an address. Each bit combination

that comes out of the output lines is called a word. The number of distinct addresses

possible with n input variables is 2n.

35. Define address and word:

In a ROM, each bit combination of the input variable is called on address.

Each bit combination that comes out of the output lines is called a word.

36. State the types of ROM

• Masked ROM.

• Programmable Read only Memory

• Erasable Programmable Read only memory.

• Electrically Erasable Programmable Read only Memory.

37. What is programmable logic array? How it differs from ROM?

In some cases the number of don‟t care conditions is excessive, it is more

economical to use a second type of LSI component called a PLA. A PLA is similar

to a ROM in concept; however it does not provide full decoding of the variables

and does not generates all the minterms as in the ROM.

38. Explain PROM.

• PROM (Programmable Read Only Memory)

It allows user to store data or program. PROMs use the fuses with material

like nichrome and polycrystalline. The user can blow these fuses by

passing around 20 to 50 mA of current for the period 5 to 20µs.The

blowing of fuses is called programming of ROM. The PROMs are one

time programmable. Once programmed, the information is stored

permanent.

39. Explain EPROM.

• EPROM (Erasable Programmable Read Only Memory)

EPROM use MOS circuitry. They store 1‟s and 0‟s as a packet of charge in a

buried layer of the IC chip. We can erase the stored data in the EPROMs by

exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is

not possible to erase selective information. The chip can be reprogrammed.

40. Explain EEPROM.

• EEPROM (Electrically Erasable Programmable Read Only Memory)

EEPROM also use MOS circuitry. Data is stored as charge or no charge on an

insulated layer or an insulated floating gate in the device. EEPROM allows selective

erasing at the register level rather than erasing all the information since the

information can be changed by using electrical signals.

41. List the major differences between PLA and PAL

PLA:

PAL

Both AND and OR arrays are

programmable and Complex

AND arrays are programmable OR

arrays are fixed

Costlier than PAL

Cheaper and Simpler

42. Define PLD.

Programmable Logic Devices consist of a large array of AND gates and OR

gates that can be programmed to achieve specific logic functions.

43. Give the classification of PLDs.

PLDs are classified as PROM (Programmable Read Only Memory), Programmable

Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL)

44. Give the comparison between PROM and PLA.

PROM

PLA

1. And array is fixed and OR Array is

programmable.

Both AND and OR Arrays are

Programmable.

2. Cheaper and simple to use. Costliest and complex than PROMS.

PART B

1. Implement the following function using PLA.

A (x, y, z) =Σm (1, 2, 4, 6)

B (x, y, z) =Σm (0, 1, 6, 7)

C (x, y, z) =Σm (2, 6)

Simplify all the expression using Karnaugh map

Draw the PLA table containing all the minterms

From the PLA table draw the logic diagram of the function

2. Implement the following function using PAL.

W (A, B, C, D) =Σm (2, 12, 13)

X (A, B, C, D) =Σm (7, 8, 9, 10, 11, 12, 13, 14, 15)

Y (A, B, C, D) =Σm (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)

Z (A, B, C, D) =Σm (1, 2, 8, 12, 13)


Draw the PAL table containing all the minterms

From the PAL table draw the logic diagram of the function

3. Implement the given function using multiplexer F(A,B,C,D)=∑(1,3,5,6)

Draw the truth table of the given function

Convert the truth table as Implementation table

Select the required type of multiplexer.

Multiplexer Implementation

4. Explain about Encoder and Decoder?

Define the encoder and decoder

Draw the truth table of encoder and decoder

Draw the Logic Diagram of encoder and decoder

Types of encoder

Applications of encoder and decoder

5. Explain in detail about PLA and PAL.

Logic difference between PROM & PLA

Logic diagram implementing a function

Logic difference between PROM & PAL

Logic diagram implementing a function

6. Implement F(A,B,C,D)= (1,3,4,11,12,13,14,15) using multiplexer.

Draw the truth table of the given function

Convert the truth table as Implementation table

Select the required type of multiplexer.

Multiplexer Implementation

7. Implement W(A,B,C,D) = Σ (2,12,13)

X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15)

Y(A,B,C,D) = Σ(0,2,3,4,5,6,7,8,10,11,15)

Z (A,B,C,D) = Σ (1,2,8,12,13) using PAL


Draw the PAL table containing all the minterms

From the PAL table draw the logic diagram of the function

Unit – IV

Synchronous Sequential Logic

Part - A

1. What is sequential circuit?

Sequential circuit is a broad category of digital circuit whose logic states depend on

a specified time sequence. A sequential circuit consists of a combinational circuit to which

memory elements are connected to form a feedback path.

2. List the classifications of sequential circuit. i) Synchronous sequential circuit.

ii) Asynchronous sequential circuit.

3. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from

the knowledge of its signal at discrete instants of time.

4. What is a clocked sequential circuit?

Synchronous sequential circuit that use clock pulses in the inputs of memory

elements are called clocked sequential circuit. One advantage as that they don‟t cause

instability problems.

5. What is called latch?

Latch is a simple memory element, which consists of a pair of logic gates with their

inputs and outputs inter connected in a feedback arrangement, which permits a single bit to

be stored.

6. List different types of flip-flops. i) SR flip-flop

ii) Clocked RS flip-flop

iii) D flip-flop

iv) T flip-flop

v) JK flip-flop

vi) JK master slave flip-flop

7. What do you mean by triggering of flip-flop.

The state of a flip-flop is switched by a momentary change in the input signal. This

momentary change is called a trigger and the transition it causes is said to trigger the flip-

flop

8. What is an excitation table?

During the design process we usually know the transition from present state to next

state and wish to find the flip-flop input conditions that will cause the required transition. A

table which lists the required inputs for a given chance of state is called an excitation table.

9. Give the excitation table of a JK flip-flop

Present State Next State Flip Flop Inputs

Qn Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

10. Give the excitation table of a SR flip-flop


Qn Qn+1 R S

0 0 X 0

0 1 0 1

1 0 1 0

1 1 0 X

11. Give the excitation table of a D flip-flop


Qn Qn+1 D

0 0 0

0 1 1

1 0 0

1 1 1

12. Give the excitation table of a T flip-flop


Qn Qn+1 T

0 0 0

0 1 1

1 0 1

1 1 0

13. What is a characteristic table?

A characteristic table defines the logical property of the flip-flop and completely

characteristic its operation.

14. Give the characteristic equation of a SR flip-flop.

Q(t+1)=S+R‟Q

15. Give the characteristic equation of a D flip-flop.

Q(t+1)=D

16. Give the characteristic equation of a JK flip-flop.

Q(t+1)=JQ‟+K‟Q

17. Give the characteristic equation of a T flip-flop.

Q(t+1)=TQ‟+T‟Q

18. What is the difference between truth table and excitation table?

i) An excitation table is a table that lists the required inputs for a given change of state.

ii) A truth table is a table indicating the output of a logic circuit for various input states.

19. What is counter?

A counter is used to count pulse and give the output in binary form.

20. What is synchronous counter?

In a synchronous counter, the clock pulse is applied simultaneously to all flip-flops.

The output of the flip-flops change state at the same instant. The speed of operation is high

compared to an asynchronous counter

21. What is Asynchronous counter?

In a Asynchronous counter, the clock pulse is applied to the first flip-flops. The

change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and

so on. Here all the flip-flops do not change state at the same instant and hence speed is less.

22. What is the difference between synchronous and asynchronous counter?

Synchronous counter

1. Clock pulse is applied simultaneously Clock pulse is applied to the first flip-flop, the

change of output is given as clock to next flip-flop.

2. Speed of operation is low.

Asynchronous counter

1. Clock pulse is applied to the first flip-flop, the change of output is given as clock to

next flip-flop

2. Speed of operation is high.

23. Name the different types of counter.

a) Synchronous counter

b) Asynchronous counter

i) Up counter

ii) Down counter

iii) Modulo – N counter

iv) Up/Down counter

24. What is up counter?

A counter that increments the output by one binary number each time a clock pulse

is applied.

25. What is down counter?

A counter that decrements the output by one binary number each time a clock pulse

is applied.

26. What is up/down counter?

A counter, which is capable of operating as an up counter or down counter,

depending on a control lead.

27. What is a ripple counter?

A ripple counter is nothing but an asynchronous counter, in which the output of the

flip-flop changes state like a ripple in water.

28. What are the uses of a counter?

i) The digital clock

ii) Auto parking control

iii) Parallel to serial data conversion.

29. What is meant by modulus of a counter?

By the term modulus of a counter we say it is the number of states through which a

counter can progress.

30. What is meant by natural count of a counter?

By the term natural count of a counter we say that the maximum number of states

through which a counter can progress.

31. The number of flip-flops required for modulo-18 counter is---- ---

Ans: n2 T. Therefore 5 flip flops required.

32. What is a ring counter?

A counter formed by circulating a „bit‟ in a shift register whose serial output has

been connected to its serial input.

33. What is BCD counter?

A BCD counter counts in binary coded decimal from0000 to 1001 and back to0000.

Because of the return to0000 after a count of 1001, a BCD counter does not have a regular

pattern as in a straight binary counter.

34. What is a register?

Memory elements capable of storing one binary word. It consists of a group of flip-

flops, which store the binary information.

35. What is a shift register?

In digital circuits, data are needed to be moved into a register (shift in) or moved

out of a register (shift out). A group of flip-flops having either or both of these facilities is

called a shift register.

36. What is serial shifting?

In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the

technique is called serial shifting.

37. Define state of sequential circuit?

The binary information stored in the memory elements at any given time defines the

“state” of sequential circuits.

38. Define state diagram.

A graphical representation of a state table is called a state diagram.

39. What is the use of state diagram?

i) Behavior of a state machine can be analyzed rapidly.

ii) It can be used to design a machine from a set of specification.

40. What is state table?

A table, which consists time sequence of inputs, outputs and flip-flop states, is

called state table. Generally it consists of three section present state, next state and output.

41. What are the different types of shift type?

There are five types. They are,

Serial In Serial Out Shift Register

Serial In Parallel Out Shift Register

Parallel In Serial Out Shift Register

Parallel In Parallel Out Shift Register

Bidirectional Shift Register

42. Give the comparison between combinational circuits and sequential circuits.

Combinational circuits Sequential circuits

Memory unit is not required Memory unity is required

Parallel adder is a combinational

circuit

Serial adder is a sequential circuit

PART B

1. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6. Use

JK Flip-flop.

Draw the State diagram from the given specifications

Draw the Excitation State table from state diagram

Using K‟Map, Simplify the output and state equation

Draw the Logic diagram of the obtained Boolean function

2. Describe the operation of SR flip-flop

Draw the Logic Diagram of SR flip flop

Draw the Graphical Symbol of SR flip flop

Draw the Characteristics table of SR flip flop

Write the Characteristics equation of SR flip flop

Explain the function of SR flip flop

3. The count has a repeated sequence of six states, with flip flops B and C repeating the

binary count 00, 01, 10 while flip flop A alternates between 0 and 1 every three counts.

Designs with JK flip-flop





4. Design a 3-bit T flip-flop counter





5. Explain the working of BCD Ripple Counter with the help of state diagram and

logic diagram.

BCD Ripple Counter Count sequence

Truth Table

State diagram representing the Truth Table

Truth Table for the J-K Flip Flop

Logic Diagram

6. Design a sequential detector which produces an output 1 every time the input

sequence 1011 is detected.

Construct state diagram

Obtain the flow table

Obtain the flow table & output table

Transition table Select flip flop Excitation table Logic diagram

7. Explain in detail about serial in serial out shift register.

Block diagram Theoretical explanation

Logic diagram

Working principle

Unit – V

Asynchronous Sequential Logic

Part - A

1. What is flow table?

During the design of asynchronous sequential circuits, it is more convenient to name

the states by letter symbols without making specific reference to their binary values. Such

table is called Flow table.

2. What is primitive flow table?

A flow table is called Primitive flow table because it has only one stable state in

each row.

3. Define race condition.

A race condition is said to exist in asynchronous sequential circuit when two or

more binary state variables change, the race is called non-critical race.

4. Define critical & non-critical race with example.

The final stable state that the circuit reaches does not depend on the order in which

the state variables change, the race is called non-critical race. The final stable state that the

circuit reaches depends on the order in which the state variables change, the race is called

critical race.

5. How can a race be avoided?

Races can be avoided by directing the circuit through intermediate unstable states

with a unique state – variable change.

6. Define cycle and merging?

When a circuit goes through a unique sequence of unstable states, it is said to have a

cycle. The grouping of stable states from separate rows into one common row is called

merging.

7. Give state – reduction procedure.

The state – reduction procedure for completely specified state tables is based on the

algorithm that two states in a state table can be combined in to one if they can be shown to

be equivalent.

8. Define hazards.

Hazards are unwanted switching transients that may appear at the output of a circuit

because different paths exhibit different propagation delays.

9. Does Hazard occur in sequential circuit? If so what is the problem caused?

Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit. It

may result in a transition to a wrong state.

10. Give the procedural steps for determining the compatibles used for the purpose of

merging a flow table.

The purpose that must be applied in order to find a suitable group of compatibles

for the purpose of merging a flow table can be divided into 3 procedural steps.

i. Determine all compatible pairs by using the implication table.

ii. Find the maximal compatibles using a Merger diagram

iii. Find a minimal collection of compatibles that covers all the states and is closed.

11. What are the types of hazards?

The 3 1) Static – 0 hazards

2) Static – 1 hazard

3) Dynamic hazards

12. What is mealy and Moore circuit?

Mealy circuit is a network where the output is a function of both present state and

input. Moore circuit is a network where the output is function of only present state.

13. Differentiate Moore circuit and Mealy circuit?

Moore circuit

Mealy circuit

a. It is output is a function of present state

only.

a. It is output is a function of present state as

well as the present input.

b. Input changes do not affect the output. b. Input changes may affect the output of the

circuit.

c. Moore circuit requires more number of

states for implementing same function.

c. It requires less numbers of states for

implementing same function.

14. How can the hazards in combinational circuit be removed?

Hazards in the combinational circuits can be removed by covering any two min

terms that may produce a hazard with a product term common to both. The removal of

hazards requires the addition of redundant gates to the circuit.

15. How does an essential hazard occur?

An essential hazard occurs due to unequal delays along two or more paths that

originate from the same input. An excessive delay through an inverter circuit in comparison

to the delay associated with the feedback path causes essential hazard.

16. What is Timing diagram?

Timing diagrams are frequently used in the analysis of sequential network. These

diagrams show various signals in the network as a function of time.

17. What is setup and hold time?

The definite time in which the input must be maintained at a constant value prior to

the application of the pulse is setup time. The definite time is which the input must not

change after the application of the positive or negative going transition of the pulse based

on the triggering of the pulse.

18. Define equivalent state.

If a state machine is started from either of two states and identical output sequences

are generated from every possible set of sequences, then the two states are said to be

equivalent.

19. What is gate delay?

If the change in output is delayed by a time ε with respect to the input. We say that

the gate has a propagation delay of ε. normally propagation delay for 0 to 1 output (ε1) may

be different than the delay for 1 to 0 changes (ε2).

20. Define state reduction algorithm.

State reduction algorithm is stated as “Two states are said to be equivalent if, for

each member of the set of inputs they give the same output and send the circuit either to the

same state or to an equivalent state. When two states are equivalent, one of them can be

removed without altering the input-output relation.

21. What is meant by level triggering?

In level triggering the output of the flip-flop changes state or responds only when the

clock pulse is present.

22. What are the problems involved in asynchronous circuits?

The asynchronous sequential circuits have three problems namely,

a. Cycles

b. Races

c. Hazards

23. Give t h e c o m p a r i s o n b e t w e e n s y n c h r o n o u s & s y n c h r o n o u s

s e q u e n t i a l circuits?

Synchronous sequential circuits Asynchronous sequential circuits.

Memory elements are clocked flip-

Flops

Memory elements are either unlocked

flip - flops or time delay elements.

Easier to design More difficult to design

24. What is fundamental mode sequential circuit?

input variables changes if the circuit is stable

inputs are levels, not pulses

only one input can change at a given time

25. What is pulse mode circuit?

inputs are pulses

widths of pulses are long for circuit to respond to the input

pulse width must not be so long that it is still present after the

new state is reached

26. What is the significance of state assignment?

In synchronous circuits-state assignments are made with the objective of

circuit reduction. Asynchronous circuits-its objective is to avoid critical races

27. What is SM chart?

Just as flow charts are useful in software design, flow charts are useful in the

hardware design of digital systems. These flow charts are called as State Machine Flow

Charts or SM charts. SM charts are also called as ASMC (Algorithmic State machine chart).

ASM chart describes the sequential operation in a digital system.

28. What are the three principal components of SM charts?

The 3 principal components of SM charts are state box, decision box &

Conditional output box.

29. What is decision box?

A diamond shaped symbol with true or false branches represents a decision box. The

condition placed in the box is a Boolean expression that is evaluated to determine which

branch to take in SM chart.

30. What is link path? How many entrance paths & exit paths are there in SM block? A path through an SM block from entrance to exit is referred to as link path.

An SM block has one entrance and exit path.

31. Differentiate ASM chart and conventional flow chart?

A conventional Flow chart describes the sequence of procedural steps and decision

paths for an algorithm without concern for their time relationship. The ASM chart describes

the sequence of events as well as the timing relationships between the states of a sequential

controller and the events that occur while going from one state to the next.

PART B

1. Design an Asynchronous sequential circuit using SR latch with two inputs A and B and

one output y. B is the control input which, when equal to 1, transfers the input A to

output y. when B is 0, the output does not change, for any change in input.

State Table

Primitive Flow Table

Formal Reduction (Implication Method)

Merging

Reduced Table

K‟Map Simplification

Logic Diagram

2. Give hazard free relation for the following Boolean function.

F (A, B, C, D) =Σm (0, 2, 6, 7, 8, 10, 12)

K‟Map simplification

Group the non-connected terms

Write the new Boolean expression

Create Hazard free link

3. Explain about Hazards?

Define Hazard

Explain Static Hazard

Explain Dynamic Hazard

Give example for each type of Hazard

4. Explain about Races?

Explain Critical Race

Explain Non-Critical Race

Give example for each type Races and cycle

5. Design T Flip flop from Asynchronous Sequential circuit?

State Table

Primitive Flow Table

Formal Reduction (Implication Method)

Merging

Reduced Table

K‟Map Simplification

Logic Diagram

6. Explain with neat diagram the different hazards and the way to eliminate them.

Classification of hazards

Static hazard & Dynamic hazard definitions

K map for selected functions Method of elimination Essential hazards

7. State with a neat example the method for the minimization of primitive flow

table.

Consider a state diagram


Using implication table reduce the flow table Using merger graph obtain maximal

compatibles Verify closed & covered conditions Plot the reduced flow table

8. Design a asynchronous sequential circuit with 2 inputs T and C. The output

attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0.

Obtain the state diagram


Using implication table reduce the flow table Using merger graph obtain maximal

compatibles Verify closed & covered conditions Plot the reduced flow table

Obtain transition table

Excitation table

Logic diagram

9. Explain in detail about Races.

Basics of races

Problem created due to races

Classification of races Remedy for races cycles

10. Explain the different methods of state assignment

Three row state assignment Shared row state assignment

Four row flow table

Multiple row state assignment

Prevention of races.

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2009

Third Semester

Computer Science and Engineering

CS 2202 — DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

PART A — (10 × 2 = 20 Marks)

1. Draw the logic diagram for the Boolean expression ((A + B) C)′D using NAND gates.

2. Perform subtraction using 1’s complement (11010)2 – (10000)2.

1‟s complement of (10000)2=(01111)2

Add (11010)2 with ( 01111)2

11010

01111 (+)

----------

101001

----------

Add carry 01010

3. Perform 9’s and 10’s complement subtraction between 18 and –24.

9‟s complement subtraction

18

+ 75 9‟s complement of -24

----------------------

93 -6 9‟s complement of 93

----------------------

10‟s complement subtraction

9‟s complement of -24 75

10‟s complement of -2476

18

+ 76

-----------------------

94

-----------------------

10‟s complement of 94 -16 Drop carry-6

4. Draw the logic diagram for half adder.

5. What is the difference between decoder and demultiplexer?

S.No Decoder Demultiplexer

1 Decoder is a many input to many

output device.

Demultiplexer is a one input to many

output devices.

2 There are no selection lines. The selection of specific output line is

controlled by the value of selection lines.

6. What is programmable logic array? How does it differ from ROM?

The most flexible PLD is the programmable logic array (PLA), where both the AND and

OR arrays can be programmed. The product term in the AND array may be shared by any

OR gate to provide the required sum of product implementation.

7. Write down the difference between sequential and combinational circuits.

Combinational circuits Sequential circuits

Memory unit is not required Memory unity is required

Parallel adder is a combinational circuit

Serial adder is a sequential circuit

8. What is race around condition?

In a JK latch, when J and k are both high, then the output toggles continuously. This

condition is called a race around condition.

Due to this, in the positive half cycle of the clock pulse (Enable), if J and K both are

HIGH, then the output toggles continuously.

To avoid this condition, an edge triggered or pulse triggered JK flip-flop is created.

In this flip-flop, the output changes only at the positive edge or a negative edge of the clock.

9. What is meant by lockout condition?

The counter may enter one of the unused states and may keep shuttling between the

unused states and not come out of this situation. This condition may develop because of

external noise, which may affect states of the flip-flops. If a counter has unused states with

this characteristic, it is said to suffer from lockout.

10. What are the steps for design of asynchronous sequential circuit?

1. Construction of a primitive flow table from the problem statement.

2. Primitive flow table is reduced by eliminating redundant states using the state

reduction.

3. State assignment is made.

4. The primitive flow table is realized using appropriate logic elements.

PART B — (5 × 16 = 80 Marks)

11. (a) Simplify the following Boolean expression using Quine McCluskey method :

F = Σm (0, 9,15, 24, 29, 30) + d (8,11, 31) . (16)

The don‟t care minterms are included

Find minterms, binary A,B,C,D ,No of 1‟s , minterms group, index, binary A,B,C,D

All the terms which remain unchecked are PIs,Moreover one of two same

combinations is eliminated.

Prepare a PI chart to determine EPIs .

All the minterms have been covered by EPIs.

Or

(b) (i) Implement Boolean expression for EXOR gate using NAND and NOR gates. (8)

Write the Boolean expression for EXOR gate.

By using NAND conversion rule, convert EXOR gate to NAND gates.

By using NOR conversion rule, convert EXOR gate to NOR gates.

(ii) Prove that (AB + C + D)(C′ + D)(C′ + D + E) = ABC + D . (4)

Multiply all the group of variables to single group.

By using the Boolean laws and theorems the L.H.S and R.H.S are proved.

(iii) Using 2’s complement perform (42)10– (68)10. (4)

Convert the decimal number into equivalent binary number.

Determine 2‟s complement of the subtrahend.

Add this to the minuend.

Omit the carry.

12. (a) (i) Explain the gray code to binary converter with the necessary diagram. (10)

Write the gray code truth table

By using the logic gray code to binary code ,gray code will convert to binary code.

Write the binary truth table.

Draw the logic diagram for the both.

(ii) Design a half subtractor circuit. (6)

Write the truth table.

Design K-map for difference and borrow.

By using the simplified difference and borrow draw the half subtractor circuit.

Or

(b) With neat diagram explain BCD subtractor using 9’s and 10’s complement

method. (16)

Add the 10‟s complement of subtrahend to minuend.

Apply the rules of BCD addition to verify that result of addition is valid BCD.

Apply the rules of 10‟s complement on the result obtained in step 2, to declare the

final result i.e., to declare the result of subtraction.

13. (a) Explain with necessary diagram a BCD to 7 segment display decoder.(16)

Decoder

BCD to 7 segment display decoder.

7 segment decoder block diagram and explanation

7 segment decoder truth table.

7 segment display LED.

Or

(b) (i) Write the comparison between PROM, PLA, PAL. (6)

Compare about AND carry and OR carry.

Compare about in terms operation.

Compare about Boolean function.

(ii) Design a BCD to excess-3 code converter and implement using PLA. (10)

Write the BCD truth table

By using the logic BCD to excess -3 code ,BCD will convert to Excess-3.

Write the Excess-3 truth table.

Draw the logic diagram for the both.

Implement using PLA.

14. (a) Design and implement a Mod-5 synchronous counter using JK flip-flop. Draw

the timing diagram also(16)

Determine how many flip-flops are needed.

Determine the numbers that come after the number that your counter needs to reach.

Place an AND gate with its inputs tied to the Q‟s of those flip flops producing a

logic 1.

Draw the timing diagram.

Or

(b) (i) Explain the working of master slave JK flip-flop. (10)

Composed 2 sections: Master section & Slave section.

Both sections are gated latch

EXCEPT the slave section is clocked on the inverted clock pulse and is controlled

by the outputs of the master section.

(ii) Draw the diagram for a 3 bit ripple counter. (6)

T flip-flops are needed.

Output of the first flip flop is applied to the clock pulse of the second flip flop

likewise the clock pulses are applied.

15. (a) (i) Design a comparator. (6)

The two numbers are equal if all pairs of significant digits are equal

To determine if A > B or A < B or A=B, we check the relative magnitude of pairs of

significant digits starting from MSB.

Write the truth table.

Form the K map and simplify the map.

Draw the logic diagram.

(ii) Design a non-sequential ripple counter which will go through the states 3, 4, 5, 7, 8,

9, 10, 3, 4 .................. draw bush diagram also. (10)

Design a non-sequential ripple counter.

The ripple counter activate only limited no of states.

Draw the push diagram for the counter.

Or

(b) (i) Design a parity checker. (6)

To check accuracy we can generate and transmit an extra bit along with the message

(data).

This extra bit is known as the parity bit and it decides wheather the data transmitted

is error free or not.

Even parity and odd parity .

(ii) Design a sequential circuit with JK flip-flop. (10)

Draw the present state-next state table for JK flipflop.

Draw Aplication or excitation table for JK flipflop.

Write the characteristics equation of JK flipflop.

Design the sequential circuit with JK flipflop.

Question Paper Code:55293

B.E./B.Tech. DEGREE EXAMINATION,NOVEMBER/DECEMBER 2011.

Third Semester

Computer Science and Engineering

CS 2202-DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

PART A-(10X2=20 marks)

1.Perform the following code conversions:

(1010.10)16(?)2(?)8(?)10

(1010.10)16

=1x163= 4096

=0x162= 0

=1x161= 16

=0x160= 0

=1x16-1

= 0.0.625

=0x16-2

= 0

----------------

(4112.0625)10

----------------

(1010.10)16=(4112.0625)10

Divide 4112 by 2 we get (100000010000)

0.0625X2=0.1250

0.1250X2=0.2500

0.2500X2=0.5000

0.5000X2=1.0000

(1000000010000.0001)2

(1 000 000 010 000.000 1)2

(10020.01)8

2.State the different ways for representing the signed binary numbers.

Sign magnitude (SM)

Diminished radix complement (DRC)

Radix complement (RC)

3.With block diagram show how a full adder can be designed by using two half adders

and one OR gate.

4.List the modeling techniques available in HDL.

Structural Modeling

Dataflow Modeling

Behavioural Modeling

5.Define decoder. Draw the block diagram and truth table for 2 to 4 decoder.

A decoder is a combinational circuit that decodes the binary information on „n‟ inputlines to

a maximum of 2n unique output lines.

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

6.What is the difference between Programmable array logic(PAL) and Programmable

logic array(PLA)?

S.No PLA PAL

1

PLA is a device with a

programmable AND array and

programmable OR array

PAL is a programmable logic device

with a fixed OR array and

programmable AND array.

2

PLA is comparatively difficult

to program, as both AND and

OR array are programmable.

PAL is easier to program as only AND

gates are programmable.

3 It is flexible. It is less flexible than PLA.

7.How many flip flops are required for designing synchronous MOD60 counter?

2n>=N

26>=60

Therefore 6 flip flops are needed.

8. Write down the characteristic equarion for JK and T flip flops.

JK Flip flop : Qn+1=J(Qn „)+(k‟)Qn

T flipflop : T=0 Qn+1=Qn T=1 Qn+1=Qn‟

9. What is meant by Race condition in Asynchronous sequential circuit?

A race condition is said to exist in an asynchronous sequential circuit when two or more

binary state variables changes value in response to a change in an input variable.

10.Define Hazard. List the Hazards in combinational circuit.

Hazards are unwanted switching transients that may appear at the output ofa circuit because

different paths exhibit different propagation delays.

Static 1-hazard: a circuit output may momentarily go to 0 when it should remain a constant

1

Static 0-hazard: a circuit output may momentarily go to 1 when it should remain a constant

0

Dynamic hazard:a circuit output may change 3 or more times when it should change from

0 to 1 (or 1 to 0)

PART B--(5X16=80 marks)

11.(a) Simplify the following Boolean function F using Karnaugh map method:

(i)F(A,B,C,D)=∑(1,4,5,6,12,14,15) (4)

(ii)F(A,B,C,D)=∑(0,1,2,4,5,7,11,15) (4)

(iii)F(A,B,C,D)=∑(2,3,10,11,12,13,14,15) (4)

(iv)F(A,B,C,D)=∑(0,2,4,5,6,7,8,10,13,15) (4)

(i) Mapping the function using Karnaugh map method.

(ii)We get F=BD’ +A’C’D+ABC .

(iii)Likewise perform the K map and write the simplified boolean function F.

(or)

(b) simplify the following Boolean expressions to a minimum number of literals:

(i) (AC)’+ABC+AC’ (2)

(ii)XYZ+X’Y+XYZ’ (2)

(iii)XY+YZ+XY’Z (2)

(iv) AB’+ABD+ABD’+(ACD)’+A’BC’ (5)

(v) BD+BCD’+A(BCD)’ (5)

(i) Simplifying the function using boolean laws we get A’+C’+ABC

(ii) Simplify all the boolean expression .

(iii) We get the minimum number of literals.

12.(a) Consider the combinational circuit shown in Figure 1.

(i) Derive the Boolean expressions for T1 through T4. Evaluate the outputs F1 and F2

as a function of the four inputs. (4)

(ii) List the truth table with 16 binary combinations of the four input variables. Then

list the binary values for T1 through T4 and outputs F1 and F2 in the table. (4)

(iii)Plotthe output Boolean function obtained in part (ii) on maps and show that

simplified Boolean expressions are equivalent to the ones obtained in part (i) (8)

(i)T1=B‟C

T2=A‟B

T3=A+T1=A+B‟C

T4=T2 XOR D=A‟B XOR D

F1=T3+T4=A+B‟C+A‟B XOR D

F2=D+T2=D + A‟B

(ii) Make the truth table and verify the F1 and F2

(iii)Simplify the boolean function

(or)

(b) (i) With suitable block diagram explain binary multiplier. (8)

(ii) Write a detailed note on carry propagation. (8)

(i)One logical approach is to form the partial-products one at a time and sum them

as they are generated.

(2)Draw the binary multiplier.

(3)The entire process consists of three steps, partial product generation, partial

product reduction and final addition.

(ii)As in any combinational ckt, the signal must propagate through the gates before

the correct output sum is available in the output terminals.

(2)Draw the 4 bit full adder circuit.

13. (a) construct a 5 to 32 line decoder with four 3 to 8 line decoders with enable and a

2 to 4 line decoder. Use block diagrams for components. (16)

(i)We need four 3-to-8 decoder for the last stage

(ii) one 2-to-4 decoder for selecting each of them at the first stage

(or)

(b) (i) Implement the following Boolean function with 16X1 multiplexer:

F(A,B,C,D)=∑(0,1,3,4,8,9,15),

Use block diagram representation. (6)

(i)This is a four variable function and, therefore we need a multiplexer with three selection

lines and eight inputs.

(ii)We choose to apply variables B,C and D to the selection lines.

(iii)The first half of the min terms are associated with A‟ and second half are associated

with A.

(iv)By circling the min terms of the function and applying rules for finding values for the

multiplexer inputs.

(ii) Write HDL gate level description for 3 to 8 line decoder. (4)

(i)Write the module and module name

(ii)Specifying the input and output

(iii)Perform the corresponding operation

(iv)Finally end module

(iii) With suitable timing diagram explain how Read operation is performed in

Random access memory.(6)

1.Transfer the binary address of the desired word to the address lines.

2.Activate the read input.

14.(a) Design a MOD 16 up counter using JK Flip flops. (16)

(i)4 flipflops are needed for MOD 16 up counter

(ii)The inputs are clock,high,clear(bar),pre(bar)

(or)

(b) With suitable example explain state reduction and state assignment. (16)

(i)State reduction algorithms are concerned with procedures for reducing the number of

states in a state table while keeping the external input-output requirements unchanged.

(ii)State assignment procedures are concerned with methods for assigning binary values to

states in such a way to reduce the cost of the combinational circuit that drives the flip-flops.

15.(a) write a detailed note on Race free state assignment. (16)

(i)Three row flow table example

(ii)Four row flow table example

(iii)Multiple row method

(or)

(b) With suitable design example, explain ASM chart. (16)

State box

Decision Box

Conditional box

ANNA UNIVERSITY OF TECHNOLOGY, COIMBATORE

B.E./B.TECH. DEGREE EXAMINATIONS: APRIL/MAY 2011

REGULATIONS: 2008

THIRD SEMESTER

DIGITAL PRINCIPLES AND SYSTEM DESIGN

Time : 3 Hours Max.Marks:100

(20x2=40 MARKS)

PART A

ANSWER ALL THE QUESTIONS

1. What is meant by maxterm?

Each individual term in standard POS form is called maxterms.

2. Simplify the following Boolean function:

a) zx+zx’y b)(x+y)(x+y’)

ZX+ZX‟Y=Z(X+Y) (X+Y)(X+Y‟)

=XX+XY+XY‟+YY‟

=X+XY+XY‟

=X(1+Y+Y‟)

=X

3. What are the ways to implement the 2’s complement?

Find the 1‟s complement of the specified number(i.e. 10 and 01)

Add one with 1‟s complement result .

4. Implement the following Boolean function using only AND and NOT gates.

F=XY+X’Y’+Y’Z

F=(XY+X’Y’+Y’Z)bar bar

F=((XY)bar(X’Y’)bar(Y’Z)bar)bar

5. Give the steps of the design procedure of combinational circuit.

o The problem definition. Determine the number of available input variables &

required O/P variables.

o Assigning letter symbols to I/O variables

o Obtain simplified Boolean expression for each O/P. Obtain the logic

diagram.

6. List out the various types of modeling used in HDL.

Gate level modeling using instantiation of primitive gates and user-defined modules.

Data flow modeling, using continuous assignment statements with keyword

‘assign’.

Behavioral modeling using procedural assignment with keyword ‘always’.

7. Realize the half adder using equal number of OR and AND gates.

In half adder Sum =A XOR B=AB‟+BA‟ Carry

=AB=((AB)‟)‟=(A‟+B‟)‟

8. In what way the don’t care combinations are analized?

The don‟t care condition is analized using X. Thus, an X inside a square in the map

indicates that we don‟t care whether the value of 0 or 1 .When simplifying the function , we

can choose to include each don‟t care minterm with either the 1‟s or the 0‟s, depending on

which combination gives the simplest expression.

9. Why the priority encoder is called so?

A priority encoder is an encoder that includes the priority function. The operation of

the priority encoder is such that if two or more inputs are equal to 1 at the same time, the

input having the highest priority will take precedence.

Inputs Outputs

D0 D1 D2 D3 Y1 Y0 V

0

1

x

x

x

0

0

1

x

x

0

0

0

1

x

0

0

0

0

1

x

0

0

1

1

x

0

1

0

1

0

1

1

1

1

10. Mention any two applications of multiplexers.

The various applications of multiplexer s are

1.Data routing.

2. Logic function generator.

3. Control sequencer.

4. Parallel-to-serial converter.

11. Define the terms with referred to ROM: address ,word

Each bit combination of the input variable is called on address. Each bit combination that

comes out of the output lines is called a word.

12. Draw the general block diagram of PLA.

13.Differentiate between a latch and flipflop.

Latch is a sequential device that checks all of its inputs continuously and changes its

outputs according to any time, independent of a clocking signal.

Flip-flop is a sequential device that samples its inputs and changes its outputs only

at times determined by clocking signal.

14.Draw the state diagram of JK flip-flop.

15. A 4 bit circulating register is initially set to (0001) where ‘1’ is the true output of

LSB flip-flop. What is the number preset at the end of 15 clock pulse?

16. Signify the switch-tail ring counter.

17. What is the effect of unequal delays in asynchronous sequential logic?

When two or more binary state variables change their value in response to a change in an

input variable, race condition occurs in asynchronous sequential circuits.

In case of unequal delays, a race condition may cause the state variables to change in an

unpredictable manner.

18. How two states are said to be compatible?

Two states are compatible if and only if, for every possible input sequence both producethe

same output sequence whenever both outputs are specified and their next states

arecompatible whenever they are specified. The unspecified outputs and states shown as

dashesin the flow table have no effect for compatible states.

19. Define hazards in combinational circuit. What is the cause of it?

The unwanted switching transients that may appear at the output of a circuit are called

hazards. The hazards cause the circuit to malfunction. The main cause of hazards is the

different propagation delays at different paths.

Hazards occur in the combinational circuits, where they may cause a temporary false

output value. When such combinational circuits are used in the asynchronous sequential

circuits, they may result in a transition to a wrong stable state.

20. List the elements in the ASM chart.

1. State box

2. Decision box

3. Conditional output box.

PART –B(5*12=60)

ANSWER ANY FIVE QUESTIONS

21.Simplify the boolean function and realize it using gates:

F(w,x,y,z)=∑ (0,1,2,4,5,6,8,9,12,13,14)

(i) Form the K-Map for the specified F(w,x,y,z)

(ii) Write the simplified Boolean function from the k map.

(iii)Realizing the simplified boolean function using logic gates.

22. a. Implement the following function with the NAND gate:

F(x,y,z)= ∑(2,3,6,7)

(i) Simplify the function using k-map.

(ii) By using NAND gate replace all other gates.

b. Using two half –adders implement a full-adder by using an OR gate

(i) First write the truth table for full adder.

(ii)By using k-map simplify the sum and carry.

(iii)Finally draw the full adder by using two half adders and an OR gate.

23. Perform the BCD to Excess – 3 code conversion using combinational logic

circuits.Draw the logic diagram.

(i)Write the BCD truth table

(ii)By using the logic BCD to excess -3 code ,BCD will convert to Excess-3.

(iii)Write the Excess-3 truth table.

(iv)Draw the logic diagram for the both.

24. a.Write a HDL code for 4 to 1 Multiplexer.

(i)Initialize the library file.

(ii)Declare all the input and output in entity part.

(iii)Perform multiplexer operation in architecture part.

b. Implement the following Boolean function with a 4x1 multiplexer

F(A,B,C,D)=∑(1,3,5,6)

(i) S2=A, S1=B and S0=C

(ii) D1=D3=D5=D6=1

(iii)D0=D2=D4=D7=0

25. a. Explain the basic structure of a ROM memory.

(i) A read –only memory (ROM) is a combinational circuit with n inputs and b outputs.

(ii)A ROM stores the truth table of n input b output combinational function.

b. List the PLA program table for the following Boolean function.

F1(x,y)= ∑(0,3)

F2(x,y)= ∑(1,2,3)

(i) First write the truth table.

(ii) Map simplification.

(iii)Draw the PLA program table(it consists of product term,inputs and outputs)

26. Construct a mod-12 counter using 4-bit binary counter with parallel load.

The input load control when equal to 1 disables the count sequence and causes a transfer of

data from inputs I1 through I4 into flipflops .

27. a. Explain the working principle of clocked RS flip-flop.

(i)When clock (abbreviated as CLK) is LOW, outputs of gates G1 and G2 are forced to 0,

which is applied to flip-flop inputs.

(ii) When clock is HIGH, gates G1 and G2 are transparent and signals S and R can reach

to flip-flop inputs S1 and R1.

b. Signify the triggering of flip-flops.

(i) Edge trigger

(ii) Level (pulse) trigger

28. Illustrate how static hazards are avoided in asynchronous sequential circuits with

an example.

(i)Essential hazard occurs normally in toggling type circuits.

(ii)(i) Make a state assignment which is free of critical races.

(ii) Design the combinational part of the network so that it is free of hazards (if require

by adding redundant gates).

(iii) Add delays in the feedback paths for the state variables as required to eliminate

essential hazards.

(iv)Hazards can be eliminated by enclosing two minterms or maxterms.

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