Department of Computer ENGINEERING - Networks College of

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Department of Computer ENGINEERING - Networks

College of computer & information system

Jazan University, Jazan

KINGDOM OF SAUDI ARABIA

Class notes

Microprocessor & assembly language

(CNET 315)

COURSE COORDINATOR: NAASIR KAMAAL KHAN

REVISED: SEPTEMBER 2014

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Chapter 1

Introduction to Microprocessors

Computer:

Computer is an electronic device for storing and processing data, typically in binary form,

according to instructions given to it in a variable program. Computer performs basically five

major computer operations or functions irrespective of their size and make. These are

1. It accepts data or instructions by way of input,

2. It stores data,

3. It can process data as required by the user,

4. It gives results in the form of output, and

5. It controls all operations inside a computer.

Block Diagram of Computer:

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Components of Computer:

1. Central Processing Unit (CPU)

The task of performing operations like arithmetic and logical operations is called

processing. The Central Processing Unit (CPU) takes data and instructions from the

storage unit and makes all sorts of calculations based on the instructions given and the

type of data provided. It is then sent back to the storage unit. CPU includes Arithmetic

logic unit (ALU) and control unit (CU)

2. Primary Memory

Primary Memory can be further classified as RAM and ROM.

RAM or Random Access Memory is the unit in a computer system. It is the place in a

computer where the operating system, application programs and the data in current use

are kept temporarily so that they can be accessed by the computer’s processor. It is said

to be ‘volatile’ since its contents are accessible only as long as the computer is on. The

contents of RAM are no more available once the computer is turned off.

ROM or Read Only Memory is a special type of memory which can only be read and

contents of which are not lost even when the computer is switched off. It typically

contains manufacturer’s instructions. Among other things, ROM also stores an initial

program called the ‘bootstrap loader’ whose function is to start the operation of computer

system once the power is turned on.

3. Input / Output Devices

These devices are used to enter information and instructions into a computer for storage

or processing and to deliver the processed data to a user. Input/Output devices are

required for users to communicate with the computer. In simple terms, input devices

bring information IN to the computer and output devices bring information OUT of a

computer system. These input/output devices are also known as peripherals since they

surround the CPU and memory of a computer system.

System Bus:

System bus is a single computer bus that connects the major components of a computer system.

The technique was developed to reduce costs and improve modularity. It combines the functions

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of a data bus to carry information, an address bus to determine where it should be sent, and

a control bus to determine its operation.

Types of Computer:

Computers can be generally classified by size and power as follows, though there is considerable

overlap:

Personal computer: A small, single-user computer based on a microprocessor.

Workstation: A powerful, single-user computer. A workstation is like a personal

computer, but it has a more powerful microprocessor and, in general, a higher-quality

monitor.

Minicomputer: A multi-user computer capable of supporting up to hundreds of users

simultaneously.

Mainframe: A powerful multi-user computer capable of supporting many hundreds or

thousands of users simultaneously.

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Supercomputer: An extremely fast computer that can perform hundreds of millions of

instructions per second.

Supercomputer and Mainframe

Mainframe was a term originally referring to the cabinet containing the central processor unit or

"main frame" of a room-filling Stone Age batch machine. After the emergence of smaller

"minicomputer" designs in the early 1970s, the traditional big iron machines were described as

"mainframe computers" and eventually just as mainframes. Nowadays a Mainframe is a very

large and expensive computer capable of supporting hundreds, or even thousands, of users

simultaneously. The chief difference between a supercomputer and a mainframe is that a

supercomputer channels all its power into executing a few programs as fast as possible, whereas

a mainframe uses its power to execute many programs concurrently.

Minicomputer

It is a midsize computer. In the past decade, the distinction between large minicomputers and

small mainframes has blurred, however, as has the distinction between small minicomputers and

workstations. But in general, a minicomputer is a multiprocessing system capable of supporting

from up to 200 users simultaneously.

Workstation

It is a type of computer used for engineering applications (CAD/CAM), desktop publishing,

software development, and other types of applications that require a moderate amount of

computing power and relatively high quality graphics capabilities. Workstations generally come

with a large, high-resolution graphics screen, at large amount of RAM, built-in network support,

and a graphical user interface.

Micro Computers / Personal Computer:

It can be defined as a small, relatively inexpensive computer designed for an individual user.

Personal computers first appeared in the late 1970s. One of the first and most popular personal

computers was the Apple II, introduced in 1977 by Apple Computer. During the late 1970s and

early 1980s, new models and competing operating systems seemed to appear daily. Then, in

1981, IBM entered the fray with its first personal computer, known as the IBM PC.

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Personal Computer Types

Actual personal computers can be generally classified by size and chassis / case. The chassis also

contains slots for expansion boards. If you want to insert more boards than there are slots, you

will need an expansion chassis, which provides additional slots. Then comes the portable

computers that are computers small enough to carry. Portable computers include notebook and

subnotebook computers, hand-held computers, palmtops, and PDAs.

The invention of microprocessor (single chip CPU) gave birth to the much cheaper micro

computers. They are further classified into

Desktop Computer

Notebook computer

Laptop computer

Subnotebook computer

Hand-held computer

Palmtop

PDA

Block Diagram of Microcomputer:

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Bus: Bundle of wires, activated together to transfer information.

Address Bus: Unidirectional, carries address

If there are N address lines, CPU can address 2N

memory locations.

Example: for N=20, No of memory locations = 1,048,576

Data Bus: Bidirectional carries data

Control Bus (Signal): ???? Memory Read, Memory Write, I/O Read, I/O Write

Microcomputer BUS Operation:

1) Fetch the Instruction from the memory

◦ Fetches the operands of the Instruction from memory

2) Decode the Instruction using Instruction decoder.

3) Execute the Instruction into series of small actions

CPU continuously does the (Fetch-Decode-Execute) Cycle

Introduction to Microprocessors:

A Microprocessor or Microprocessor Unit (MPU) does the same task for Microcomputer as CPU

does for General Computer. The Size of Microprocessor is defined by its ALU.

Microprocessor Year of Invention ALU Size

INTEL 4004 1971 4 – bit

8008 1972 8 – bit

8080 1974 8 – bit

8085 1976 8 – bit

8086 1978 16 – bit

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32-bit - 80286 (1982), 80386 (1985), 80486 (1989), Pentium (1993), Pentium II (1997),

Celeron and Pentium III (1999) and Pentium 4 (2000)

64-bit - Itanium (2001), Pentium 4 and Xeon (2005)

128-bit – Different types of Microcontrollers (after 2005)

A Microprocessor is silicon chip (IC) that contains the ALU where most of the calculations are

performed.

Microprocessors are distinguished by 3 characteristics

◦ Instruction set: the set of instructions that the microprocessor can execute.

◦ Bandwidth: the number of bits processed in each instruction.

◦ Clock speed: (MHz) It determines how many instructions/second the processor

can execute

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Key Features of 8086 Microprocessors:

1) Upward compatible

2) Has six byte queue

3) 16-bit data bus

4) 20-bit address bus

5) +5 volt supply

6) Package: 40 pin DIP (Dual-in-line Package)

7) Operate in minimum and maximum mode

8) CPU clock rate : 5 MHz, 8MHz and 10 MHz

9) Work as Uniprocessor and multiprocessor

10) Powerful and flexible instruction set.

11) 256 Vectored interrupts

12) Fabrication Technology: H-MOS, N-channel, depletion load silicon gate

13) It has multiplexed address and data bus

Microprocessor Applications:

Toys : video games, programmable robots

Complex intelligent product controllers : VCR control and programming, security

systems, lighting system controllers

Computer peripherals: video display, higher-speed printers. Modems, plotters,

communication controllers.

Industrial controllers : robotics, processing control, sequence control, machine tool

control

Instruments : logic analyzers, communication analyzers, disk drive testers, digital

oscilloscopes, smart voltmeters.

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Scope of this Course: Microprocessor & Assembly Language

Interrupts

o Interrupt Vector Table

o 8259A Priority Interrupt Controller

8087 Math Co-processor

o Architecture

o Data Types

o Instruction Set Programming

Numerical Problems

8086 Microprocessor

Hardware Software

Architecture –

Block Diagram

Functionality -

PIN Diagram

Instruction Set + Assembler

Directives + Assembly Language

Programs

Programming

Addressing Modes

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Chapter 2

8086 Microprocessor Architecture

8086 Architecture / Block Diagram

8086 CPU is divided into two functional Units,

Bus Interface Unit (BIU) and

Execution Unit (EU)

The major reason for this separation is to increase the processing speed of the processor

The BIU has to interact with memory and input/output devices in fetching the instructions and

data required by the EU.

EU is responsible for executing the instructions of the programs and to carry out the required

processing.

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Tasks of BIU

It sends out address.

It fetches instruction from memory.

It reads data from memory and ports.

It writes data to memory and ports.

Tasks of EU

It tells the BIU from where to fetch the instruction or data.

It decodes the fetched instruction.

It executes the decoded instruction.

Execution Unit (Detail Explanation)

Parts of Execution Unit

Control Unit

Arithmetic and Logical Unit (ALU)

Instruction Decoder (Not Shown in figure)

General Purpose Registers

Flag Register

Pointer and Index Register (Special Purpose Register)

Control Unit: Directs Internal Operation.

ALU: This 16 bit ALU can add, subtract, AND, OR, XOR, INC, DEC, complement or shift

binary numbers i.e it is responsible for all arithmetic and logical operation.

Instruction Decoder: It translates the instruction fetched from memory into a series of action

which the EU carries out.

General Purpose Register: 8086 has four 16 bit registers or eight 8 bit registers. The

advantage of using internal register for temporary storage of data is

that, it can be accessed more quickly since the data is already in

EU.

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Category Bit Register Name

General Purpose Register 16 AX,BX,CX,DX

General Purpose Register 8 AH,AL,BH,BL,CH,CL,DH,DL

Pointer Register 16 SP (Stack Pointer)

BP (Base Pointer)

Index Register 16 SI (Source Index)

DI (Destination Index)

Segment Register 16 CS (Code Segment)

DS (Data Segment)

SS (Stack Segment)

ES (Extra Segment)

Instruction Pointer Register 16 IP (Instruction Pointer)

Status Register (Flag) 16 F

General Purpose Register:

Register Function

AX Accumulator Register

For arithmetic, logic and data transfer operation

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BX Base Register

Also as address register

CX Count Register

Used for loop counter, shift and rotate bits

DX Data Register

Used in division and multiplication also I/O operation

16 bit register can be divided into two 8- bit register

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Pointer & Index Register (Special Purpose Register) :

These registers are used to store relative shifting value (offset) for memory address location

There are 2 pointer registers:

Stack Pointer (SP) – point to the top of stack

Base Pointer (BP) – used to fetch data in data segment

There are 2 index registers:

Source Index (SI) – contains offset address for source operand in data segment

Destination Index (DI) - contains offset value for destination operand in segment

Flag Register:

It is a 16-bit register with each bit corresponding to a flip-flop. It changes its status according to

the stored output in the accumulator. A flag can control certain operation of the EU.

U – Undefined, R – Reserved

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8086 has 16 bit flag register with 9 active flags, out of which 6 are conditional and 3 are control.

Flag Register

Conditional Flags (6)

1)Carry Flag

2)Parity Flag

3)Auxillary Flag

4)Zero Flag

5)Sign Flag

6)Overflow Flag

Control Flags (3)

1)Trap flag

2)Interrupt Enable flag

3)Direction flag

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Bus Interface Unit (Detail Explanation)

Parts of Bus Interface Unit

Instruction stream byte queue

Segment Registers

Instruction Pointer

Instruction stream byte Queue (Six Byte):

While the Execution Unit is decoding or executing an instruction which does not

require the use of buses the BIU fetches upto six instruction byte for the following

instruction.

The BIU stores these prefetched bytes in a FIFO register set called a queue.

Fetching the next instruction while the current instruction executes is called

Pipelining.

8086 instructions vary from 1 to 6 bytes, when the EU is ready for its next

instruction, it reads the instruction byte for the instruction from the queue in BIU.

Fetch and execution are taking place parallel, in order to improve the

performance of the microprocessor.

Segment Registers:

8086 BIU sends out 20 bit addresses, so it can address upto 220

or 1,048,576 bytes

in memory. However at any given time the 8086 works with only four 65536 byte

(64KB) logical segments within this 1MB range.

Four segment registers in the BIU are used to hold the upper 16 bits of the initial

addresses of four memory segments that the 8086 is working with at a particular

time.

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These 16 bit Segment registers are Code Segment Register, Data Segment

Register, Stack Segment Register and Extra Segment Register.

Hardwired Zero: BIU always insert a zero (lowest 4 bits) to make the address

20 bit is called as hardwired zero.

Segment in 8086 Memory:

The Memory of 8086 is divided into four 64 KB logical segments

Segment Usage

Code (CS) Space to store program that will be executed

Data (DS) Space to store data that will be processed

Stack (SS) Special space to store information needed by microprocessor to

execute subroutine or interrupt service. Offset address is stored

in 16-bit stack pointer register

Extra (ES) Function is the same as DS

Segments can be adjacent, disjoint, partially overlap or fully overlap.

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Instruction Pointer:

It is a 16-bit register used to store the 16-bit effective address for CS

register.

Each time instruction is fetched from memory to be executed in processor,

IP content will be added so that it always show to the next instruction .

If it is branch instruction, the IP content will be loaded with new value

which is the branch address.

Base address: Offset address Notation

Address of 20 bit in 8086 is generally represented as Base Address: Offset address

Notation.

16 bit Base address is stored in one of the segment register and 16 bit of offset

address is stored in special purpose register.

Default Segment Register: Offset Pair.

CS:IP

DS:SI

ES:DI

SS:SP

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Physical Address Generation

Segment addresses must be stored in segment registers.

Effective address / Offset is derived from the combination of pointer registers, the

Instruction Pointer (IP), and immediate values .

Examples:

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Memory Banking:

In 8086 there is 20 bit address bus, so it can address 1,048,576 addresses.

At each address we can store 8 bit address (1-byte)but if want to write a word (16-bit) into a

memory segment to store data in byte form then we write the data in two consecutive memory

address which are even (low) and odd (high) memory.

*This concept will be more clear in the Chapter of Addressing modes.

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PIN Diagram of 8086

Signal Description of 8086:

AD15±AD0

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address and

data bus.

ALE

Address Latch Enable. A HIGH on this line causes the lower order 16 bit address bus to be

latched that stores the addresses and then, the lower order 16 bit of the address bus can be used

as data bus.

READY

READY is the acknowledgement from the addressed memory or I/O device that it will complete

the data transfer.

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INTR

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledges

operation. A subroutine is vectored to via an interrupt vector lookup table located in system

memory. It can be internally masked by software resetting the interrupt enable bit. INTR is

internally synchronized. This signal is active HIGH.

INTA'

Interrupt Acknowledge from the Microprocessor.

NMI

NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt request to

the MP. A subroutine is vectored to via an interrupt vector lookup table located in system

memory. NMI is not maskable internally by software.

RESET: causes the processor to immediately terminate its present activity. The signal must be

active HIGH for at least four clock cycles. It restarts execution

MN/MX' (pin number 33)

MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

M/IO': Differentiate between the Memory and I/O operation. A LOW on this pin indicated I/O

operation and a HIGH indicated a Memory Operation

HOLD : The 8086 has a pin called HOLD. This pin is used by external devices to gain control of

the busses.

HLDA :

When the HOLD signal is activated by an external device, the 8086 stops executing instructions

and stops using the busses.

8086 MINIMUM AND MAXIMUM MODES of operation

MN/MX Minimum mode: The 8086 processor works in a single processor environment. All control

signals for memory and I/O are generated by the microprocessor.

Maximum mode is designed to be used when a coprocessor exists in the system. 8086 works in a

multiprocessor environment. Control signals for memory and I/O are generated by an external

BUS Controller.

*Timing diagrams are beyond the scope of this Course

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Chapter 3

Addressing Modes of 8086 Microprocessor

Addressing Mode:

Study of addressing mode is first step towards assembly language programming. An assembly

language program statement is written in a form that has four fields

Label / Address Opcode Operand Comment

NEXT / 2000:0100 MOV AX, BX Copy the contents of

BX to AX

Addressing mode is a technique to determine which operand is to be fetched.

(Opcode : Operation to be performed; Operand = argument for an operator or for machine

language instruction i.e data to be operated on)

Addressing modes Characteristics:

1. It give flexible programming to user

2. It uses pointers to memory,

3. Has counter for loop control,

4. Index for data and program replacement

5. Reduce bit numbers in address field for an instruction

There are basically 4 types of addressing mode in 8086 register:

1. Immediate Addressing Mode

2. Register Addressing Mode

3. Memory Addressing Modes

3.1 Direct Addressing Mode

3.2 Register Indirect Addressing Mode

3.3 Based Addressing Mode

3.4 Indexed Addressing Mode

3.5 Based Indexed Addressing Mode

4. Relative Addressing Modes

4.1 Register Relative Addressing Mode

4.2 Based Relative Addressing Mode

4.3 Index Relative Addressing Mode

4.4 Base Indexed Relative Addressing Mode

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Immediate addressing mode and register addressing mode does not require BUS, as

communication is inside the microprocessor, whereas Memory and Relative addressing mode

requires BUS for fetching the data from memory.

As we have studies earlier that Physical /Actual address is combination of Base address and

effective address, so if you want the data stored in memory the first step is to find out the

physical address of that particular memory location.

Immediate Addressing:

Here the immediate data, is part of instruction, and appears in the form of successive byte or

bytes.

MOV Destination, Source

Ex. MOV AX, 5678

Register Addressing:

Here the data is stored in a register and it is referred using the particular register.

All the registers, except IP, may be used in this mode


Ex. MOV AX, BX

Memory addressing modes

Before coming to memory and relative addressing mode we will see the General formula to

calculate the Physical Address

General Formula:

Physical Address = Base Address + Effective Address

= [DS/ES/SS/CS] * 10H + [BX/BP]+[SI/DI]+8/16 bit displacement

# 16 decimal is equal to 10 hexadecimal , Solve

(16)10 = (10)16

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a) Direct addressing Mode :

In this mode, a 16-bit memory address (offset) is directly specified in the

instruction as a part of it.

MOV AX, offset

Ex. MOV AX, [5000H]

This means offset = 5000 , add it to base address (already specified in question, generally

DS) obtain physical address, go to that physical address, obtain data and put this data in

AX

Ex: DS = 2100, offset = 5000 so physical address = 2100*10 + 5000 = 26000, go to 26000

obtain LSB, copy it to AL, go to 26001 obtain MSB, copy it to AH (Memory banking)

Here point to be noted is that, we don’t know the value of data which actually moves into AX.

b) Register Indirect addressing:

In this mode, the address of the memory location which contains data or operand

is determined in an indirect way, using offset registers.

The offset address of data is in either BX or SI or DI registers.

The default segment is either DS or ES.

MOV AL, [SI]

(or) MOV AX, [BX]

(or) MOV AX, [DI]

c) Based Memory addressing:

In this mode, offset of the operand is stored in one of the base registers.

The offset address of data is in either BX or BP.

MOV AX, [BX]

(or) MOV AX, [BP]

d) Indexed memory addressing:

In this mode, offset of the operand is stored in one of the index registers.

DS is the default segment for index registers SI and DI.

MOV [SI], AL

(or) MOV AX, [DI]

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e) Based indexed memory addressing:

The effective address is formed, by adding content of a base register (BX or BP)

to the content of an index register (SI or DI).

The default segment register may be ES or DS

MOV AX, [BX] [SI]

MOV [BX] [DI], AL

Relative addressing modes

a) Register relative addressing mode

MOV AX, [BX] + offset

b) Based relative addressing mode


c) Indexed relative addressing mode

MOV AX, [DI] + offset

d) Based Index relative addressing mode

MOV AX, [BX] [DI] + offset

Question: The contents of different registers are given below. Form Physical addresses for all

memory addressing modes.

Offset = 0050, DS = 2100, BX=0500, DI= 1000 (All numbers in hexadecimal)

Solution:

(1) Immediate Addressing Mode

MOV AX, 0500

(2) Register Addressing Mode

MOV AX, BX

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(3) Memory addressing modes

(Add 0 at the end of the address AX, which is called as hard-wired 0)

(a) Direct addressing mode

MOV AX, offset

Physical Address (PA) = 2100 0

+ 0050

-------------

21050

-------------

(b) Register Indirect addressing mode

MOV AX, [BX] (or) MOV AX, [DI]


+ 0500

-------------

21500

-------------


+1000

-------------

22000

c) Based Memory addressing mode

MOV AX, [BX]


+ 0500

-------------

21500

-------------

d) Indexed memory addressing mode

MOV AX, [DI]


+ 1000

-------------

22000

-------------

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e) Based indexed memory addressing mode

MOV AX, [BX] [DI]


0500

+ 1000

-------------

22500

-------------

Relative addressing modes

a) Register relative addressing mode



0500

+ 0050

-------------

21550

-------------

b) Based relative addressing mode



0500

+ 0050

-------------

21550

-------------

c) Indexed relative addressing mode

MOV AX, [DI] + offset


1000

+ 0050

-------------

22050

30

-------------

d) Based Index relative addressing mode

MOV AX, [BX] [DI] + offset


0500

1000

+ 0050

-------------

22550

-------------

ASSIGNMENT:

Q – 1. The contents of different registers are given below. Form Physical addresses for all

memory addressing modes.

Offset (displacement) = 5050, AX = 1100, BX=2100, SI= 0300, DI= 0400 BP = 5000, SP =

6000 CS = 7000, DS = 9000, SS = 2000, IP = 7000 (All numbers in hexadecimal)

Q – 2. The contents of different registers are given below. Form Physical addresses for all

memory and relative addressing modes.

Offset (displacement) = 5000, AX = 1000, BX=2000, SI=3000,DI=4000 BP = 5000,

SP = 6000 CS = 7000, DS = 1000, SS = 2000, IP = 7000 (All numbers in hexadecimal)

Q – 3. If CS = 2000, IP = 0100, DS = 5000, BX = 0200, SI = 0010, Displacement ARRAY =

0050. Find Physical address for all types of memory addressing mode.

Q – 4. If DS = 1200, BX = 0900, SI = 0800, Displacement DISP = 5000. Find Physical address

for all types of relative addressing mode.

Q – 5. If DS = 3500, BX = 1200, SI = 3000, Displacement OFFSET = 1000. Find Physical

address for all types of memory addressing mode.

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Instruction Set of 8086

Data Transfer Arithmetic Bit Manipulation String Program Transfer Process Group Group Group Instruction Instruction Control Instruction

Logical Shift Rotate

Addition Subtraction Multiply Divide Unconditional Conditional Iteration Interrupt Control Instruction

General Input / Address Flag Purpose Output Object Transfer Flag operation External synchronization No operation

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CHAPTER – 4

Instruction Set of 8086 Microprocessor

Benefits of Assembly Language Programming

1) It takes up less memory

2) It executes much faster

3) Used for real time applications

4) Good for controlling hardware devices

5) Also performs pure software operations

DATA TRANSFER INSTRUCTIONS

(1) MOV: Move instruction transfers data from one register/memory

location to another register/memory location.


Ex. MOV AX, BX

MOV AX, [SI]

Note: Both, source and destination cannot be memory locations

(2) PUSH: Push to Stack. This instruction pushes the contents of the specified

register/memory location on to the stack.

PUSH Source

Ex. PUSH AX

PUSH DS

Note: Push operates only on 16-bit data

(3) POP: Pop from Stack. This instruction pops the contents of the specified

register/memory location off the stack.

POP destination

Ex. POP AX

(4) XCHG: Exchange byte or word

XCHG CX, BX

(Contents of BX & CX will be swapped)

Note: Exchange of contents of two memory locations is not permitted.

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(5) XLAT: Translate or replace byte. This instruction is used to translate a byte from one

code to another code.

DATA TRANSFER INSTRUCTIONS – INPUT / OUTPUT

(1) IN: Input the port. This instruction is used for reading an input port.

IN AX, Port address

Ex. IN AX, 03

(here 03 is port address not data)

(2) OUT: Output to the port. This instruction is used for writing to an output port.

OUT Port address, AX

Ex. OUT 03, AX

(here 03 is port address not data)

DATA TRANSFER INSTRUCTIONS – ADDRESS OBJECT

(1) LEA: Loads Effective Address. This instruction loads the effective address by

destination operand into the specified source register.

LEA register, source

Ex: LEA BX, Total

(2) LDS / LES: Load pointer with DS/ES. This instruction loads the DS or ES register and

specified destination register with the content of memory location specified as source in the

instruction.

LDS register, source Ex: LDS BX, Total

LES register, source Ex: LES BX, Total

Two memory locations will be copied to ES and next two memory locations will be

copied to BX.

Note: Source cannot be a register

DATA TRANSFER INSTRUCTIONS – FLAG TRANSFER

(1) LAHF: Loads AH from Lower Byte of Flag

(2) SAHF: Store AH to Lower Byte of Flag Register

(3) PUSH F: Push flags to stack

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(4) POP F: POP flags from stack

ARITHMETIC INSTRUCTIONS

ARITHMETIC INSTRUCTIONS – ADDITION

(1) ADD: Add byte or word

ADD destination, source

Ex: ADD AX, BX ; AX AX + BX

Note: Register cannot be segment register

(2) ADC: Add byte or word with Carry

ADC destination, source with carry

Ex: ADC AX, BX ; AX AX + BX + Carry Flag

(3) INC: Increment byte or word by 1

INC destination

Ex: INC AX ; AX AX + 1

(4) AAA: ASCII adjust after addition

(5) DAA: Decimal adjust for addition

ARITHMETIC INSTRUCTIONS – SUBTRACTION

1) SUB: Subtract byte or word

SUB destination, source

Ex. SUB AX, BX ; AX AX - BX

2) SBB: Subtract byte or word with borrow

Ex. SBB AX, BX

3) DEC: Decrement byte or word by 1

DEC destination ; destination = destination - 1

Ex: DEC AX ; AX AX - 1

4) AAS: ASCII adjust after Subtraction

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5) DAS: Decimal adjust for Subtraction

6) NEG: Negate byte or word

Ex. NEG AX

Note: NEG instruction do 2’s complement of number

7) CMP: Compare byte or word

Ex. CMP AX, BX

This instruction performs subtraction but result is not stored anywhere, only flags are

affected

FLAG AX>BX AX=BX AX<BX

CF 0 0 1

ZF 0 1 0

SF 0 0 1

ARITHMETIC INSTRUCTIONS – MULTIPLICATION

1) MUL: Multiply byte or word unsigned or word by the contents of AL.

MUL source

Ex. MUL BX

2) IMUL: Integer Multiply byte or word

IMUL source

Ex. IMUL CX

3) AAM: ASCII adjust after Multiplication

ARITHMETIC INSTRUCTIONS – DIVISION

1) DIV: Divide byte or word unsigned

DIV source

Ex. DIV BX

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2) IDIV: Integer Divide byte or word

IDIV source

3) AAD: ASCII adjust for Division

4) CBW: Convert byte to word

5) CWD: Convert word to double word

BIT MANIPULATION INSTRUCTIONS

LOGICAL INSTRUCTIONS: (bit by bit)

1) NOT: NOT byte or word (1’s Complement)

NOT destination

Ex. NOT BX

2) AND: AND byte or word

AND destination, source

Ex. AND AX, BX

3) OR: OR byte or word

OR destination, source

Ex. OR AX, BX

4) XOR: Exclusive OR byte or word

XOR destination, source

Ex. XOR AX,BX

5) TEST: Logical Compare Instruction - Test byte or word

TEST destination, source

Ex. TEST AX, BX

37

BIT MANIPULATION INSTRUCTION – SHIFT

1) SHL / SAL: Shift logical / Arithmetic left byte or word.

This instruction shift the operand word or byte, bit by bit to the left and insert

zeros in the newly introduced least significant bits (LSBs).

SHL destination, count

Ex. SHL BX, 04 (if BX = 1010 1111 1100 0110)

Result: 1111 1100 0110 0000

2) SHR: Shift logical right byte or word

This instruction performs bit-wise right shifts on the operand word or byte that

resides in a register or a memory location, by the specified count in the instruction and

inserts zeros in the shifted positions.

SHR destination, count

Ex. SHR BX, 04 (if BX = 1010 1111 1100 0110)

Result: 0000 1010 1111 1100

3) SAR: Shift Arithmetic right byte or word

This instruction performs right shifts on the operand word or byte that may be a register

or a memory location by the specified count in the instruction. It inserts the most significant

bit (MSB) of the operand in the newly inserted position. The result is stored in the destination

operand.

SAR destination, count

Ex. SAR BX, 04 (if BX = 1010 1111 1100 0110)

Result: 1111 1010 1111 1100

38

BIT MANIPULATION INSTRUCTION – ROTATE

1) ROL: Rotate Left byte or word without Carry

This instruction rotates the content of the destination operand to the left by the

specified count (bit-wise) excluding carry. The most significant bit (MSB) is

pushed into the carry flag as well as the LSB position at each operation.

ROL destination, count

Ex. ROL BX, 04 (if BX = 1010 1111 0010 1100 )

Result: 1111 0010 1100 1010

2) ROR: Rotate right byte or word without Carry

This instruction rotates the content of the destination operand to the right by the

specified count (bit-wise) excluding carry. The least significant bit (LSB) is

pushed into the carry flag as well as the MSB position at each operation.

39

ROR destination, count

Ex. ROR BX, 04 (if BX = 1010 1111 0010 1100 )

Result: 1100 1010 1111 0010

3) RCL: Rotate left byte or word through Carry

This instruction rotates the content of the destination operand to the left by the

specified count (bit-wise) through the carry flag. For each operation, the carry flag is

pushed into LSB, and the MSB operand is pushed into carry flag. The remaining bits are

shifted left by the specified positions.

RCL destination, count

CF

Ex. RCL BX, 01 (if BX = 0 1010 1111 0010 1100

Result: 1 0101 1110 0101 100 0

4) RCR: Rotate through carry right byte or word

This instruction rotates the contents of the destination operand right by the

specified count (bit-wise) through the carry flag. For each operation, the carry flag is

pushed into MSB, and the LSB operand is pushed into carry flag. The remaining bits are

shifted right by the specified positions.

RCR destination, count

CF

Ex. RCR BX, 01

(if BX = 1010 1111 0010 1101 0

Result: 0101 0111 1001 0110 1

STRING MANIPULATION INSTRUCTIONS

1) CMPS: Compare two string byte or string word. The length of the string must be stored

in the register CX. If both the byte or the word strings are equal, zero flag is set.

2) MOVSB / MOVSW: String bytes or string words are moved to another set of destination

locations.

3) SCAS: Scan string byte or string word.

40

4) LODS: Load String Byte or string word.

5) STOS: Store String Byte or String word.

PROGRAM TRANSFER INSTRUCTIONS

Unconditional Branch Instructions

(1) CALL: Unconditional Call – Call a procedure.

NEAR CALL: Call a procedure in the same segment

FAR CALL: Call a procedure in some other segment

(2) RET: Return from the Procedure. At the end of the procedure, the RET instruction must

be executed.

(3) INT N: Interrupt type N.

(Discussed in detail in chapter 6 - Interrupts)

(4) JMP: Unconditional Jump – transfers the control of execution to the specified address

using a displacement.

(5) IRET: Return from ISR - when ISR is executed, the values of IP,CS and flags are

retrieved from the stack to continue the execution of the main program.

(6) LOOP: Loop unconditionally – this instruction executes the part of the program from

the label, specified in the instruction up to the loop instruction, CX number of times.

41

Important Conditional Branch Instruction

JC Jump if carry

JZ/JE Jump if Zero

JNC Jump if no carry

JNE/JNZ Jump if no zero

Unconditional Branch Instructions

CALL Call Procedure

RET Return from Procedure

JMP Jump

Iteration Control

LOOP Loop unconditionally

LOOPE/LOOPZ Loop if equal / zero

LOOPNE/LOOPNZ Loop if not equal/not zero

JCXZ Jump if register CX=0

Interrupts

INT Interrupt

INTO Interrupt if overflow

BOUND Interrupt if out of array bounds

IRET Interrupt return

Flag Operations

STC Set Carry Flag

CLC Clear Carry Flag CMC Complement Carry Flag STD Set Direction Flag CLD Clear Direction Flag STI Set Interrupt Flag CLI Clear Interrupt Flag

42

External Synchronization

HLT Halt until interrupt or reset

WAIT Wait for TEST pin active

ESC Escape to external processor

LOCK Lock bus during next instruction

NOP - No Operation

43

CHAPTER – 5

Assembler Directives of 8086 Microprocessor

• An assembler is a program used to convert an assembly language program into the

equivalent machine code modules which may further converted to executable codes.

• Assembler directives give instruction to the assembler to prepare the codes.

• The popular assemblers like the Intel 8086 macro assembler, the turbo assembler and the

IBM macro assembler use common assembler directives

Important Directives

DB: Define Byte - The DB directive is used to reserve byte or bytes of memory locations in

the available memory

Examples:

RANKS DB 01H, 02H ; reserve 2 memory locations & initialize the

values specified

NAME DB ‘JAZAN’; reserve number of characters in the string &

initialize those locations by the ASCII equivalent

characters.

VALUE DB 25H ; reserve 25H memory byte & uninitialized.

DW: Define Word – DW directive serves the same purposes as the DB directive, but

reserves the number of memory words (16-bit).

Example:

WORDS DW 1234H, 09ACH ; reserves 2 words in memory (4 bytes), &

initialize the values specified.

DQ: Define Quadword – DQ directive is used to direct the assembler to reserve 4 words (8

bytes) of memory for the specified variable and may initialize it with the specified values.

DT: Define Ten Bytes – DT directive directs the assembler to define the specified variable

equiring 10-bytes for its storage and initialize the specified values.

44

ASSUME: Assume Logical Segment Name – used to inform the assembler, the names of

the logical segments to be assumed for different segments used in the program.

Examples:

ASSUME CS:CODE; directs the assembler that the machine codes are

available in a segment named CODE, and CS register is loaded

with the codes.

ASSUME DS: DATA; directs the assembler that the data are available in a logical

segment named DATA, and DS register is loaded with the data.

Note: The ASSUME statement is a must at the starting of each assembly language

program.

END: END of Program – The END directive marks the end of the assembly language program.

Program statements after the END statement will be ignored.

ENDP: END of Procedure – In assembly language programming, procedure / subroutines are

called by the main program. The ENDP directive is used to indicate the end of the procedure. A

procedure is usually assigned by a name, i.e., label, and to mark the end of the procedure, the

name of the procedure, i.e., label may appear as a prefix with the ENDP directive.

Example:

PROCEDURE ABC

-----

-----

-----

ABC ENDP

ENDS: END of Segment – This directive marks the end of a logical segment. The logical

segments are assigned with the names using the ASSUME directive. The names appear with the

ENDS directive as prefixes to mark the end of those particular segments.

Example:

DATA SEGMENT

-------

-------

DATA ENDS

ASSUME CS : CODE, DS : DATA

CODE SEGMENT

-----

-----

CODE ENDS

45

END

EXAMPLE PROGRAMS

1. Write a Program in TASM to Add two 16 bit numbers.

DATA SEGMENT

NUM1 DW 4321H

NUM2 DW 1234H

RESULT DW ?

CARRY DB 00H

DATA ENDS

CODE SEGMENT

ASSUME CS:CODE,DS:DATA

START: MOV AX,DATA

MOV DS,AX

MOV AX,NUM1

ADD AX,NUM2

JNC JUMP

MOV CARRY,01H

JUMP: MOV RESULT,AX

INT 03H

CODE ENDS

END START

2. Write a Program in TASM to subtract two 16 bit numbers.

DATA SEGMENT

NUM1 DW 4321H

NUM2 DW 1234H

RESULT DW ?

BORROW DB 00H

DATA ENDS

CODE SEGMENT


START:MOV AX,DATA

MOV DS,AX

MOV AX,NUM1

SUB AX,NUM2

JNC JUMP

46

MOV BORROW,01H

JUMP:MOV RESULT,AX

INT 03H

CODE ENDS

END START

3. Write a Program in TASM to multiply two 16 bit numbers.

DATA SEGMENT

NUM1 DW 4321H

NUM2 DW 1234H

RESULT DD ?

DATA ENDS

CODE SEGMENT


START: MOV AX,DATA

MOV DS,AX

MOV DX,0000H

MOV AX,NUM1

MUL NUM2

MOV WORD PTR RESULT,AX

MOV WORD PTR RESULT+2,DX

INT 03H

CODE ENDS

END START

4. Write a Program in TASM to divide two 16 bit numbers.

DATA SEGMENT

NUM1 DW 4321H

NUM2 DW 1234H

REM DW ?

QUO DW ?

RESULT DD ?

DATA ENDS

CODE SEGMENT


START: MOV AX,DATA

MOV DS,AX

MOV DX,0000H

MOV AX,NUM1

DIV NUM2

47

MOV QUO,AX

MOV REM,DX

INT 03H

CODE ENDS

END START

5. Write a program in Assembly language to find out the number of even and odd numbers

from a given series of 16-bit hexadecimal numbers.

ASSUME CS: CODE, DS: DATA

DATA SEGMENT

LIST DW 2357H, 0A579H, 0C322H, 0C91EH, 0C000H, 0957H

COUNT EQU 006H

DATA ENDS

CODE SEGMENT

START: XOR BX, BX

XOR DX, DX

MOV AX, DATA

MOV DS, AX

MOV CL, COUNT

MOV SI, OFFSET LIST

AGAIN: MOV AX, [SI]

RCR AX, 01

JC ODD

INC BX

JMP NEXT

ODD: INC DX

NEXT: ADD SI, 02

DEC CL

JNZ AGAIN

MOV AH, 4CH

INT 21H

CODE ENDS

END START

48

CHAPTER – 6

8086 Interrupts

INTERRUPTS

There are two main types of interrupt in the 8086 microprocessor, internal and external

hardware interrupts. Hardware interrupts occur when a peripheral device asserts an

interrupt input pin of the microprocessor. Whereas internal interrupts are initiated by the

state of the CPU (e.g. divide by zero error) or by an instruction.

Provided the interrupt is permitted, it will be acknowledged by the processor at the end of

the current memory cycle. The processor then services the interrupt by branching to a

special service routine written to handle that particular interrupt. Upon servicing the

device, the processor is then instructed to continue with what is was doing previously by

use of the "return from interrupt" instruction.

The status of the program being executed must first be saved. The processors registers

will be saved on the stack, or, at very least, the program counter will be saved. Preserving

those registers which are not saved will be the responsibility of the interrupt service

routine. Once the program counter has been saved, the processor will branch to the

address of the service routine.

Edge or Level sensitive Interrupts

Edge level interrupts are recognized on the falling or rising edge of the input signal. They

are generally used for high priority interrupts and are latched internally inside the

processor. If this latching was not done, the processor could easily miss the falling edge

(due to its short duration) and thus not respond to the interrupt request.

Level sensitive interrupts overcome the problem of latching, in that the requesting device

holds the interrupt line at a specified logic state (normally logic zero) till the processor

acknowledges the interrupt. This type of interrupt can be shared by other devices in a

wired 'OR' configuration, which is commonly used to support daisy chaining and other

techniques.

Maskable Interrupts

The processor can inhibit certain types of interrupts by use of a special interrupt mask bit.

This mask bit is part of the flags/condition code register, or a special interrupt register. In

49

the 8086 microprocessor if this bit is clear, and an interrupt request occurs on the

Interrupt Request input, it is ignored.

Non-Maskable Interrupts

There are some interrupts which cannot be masked out or ignored by the processor. These

are associated with high priority tasks which cannot be ignored (like memory parity or

bus faults). In general, most processors support the Non-Maskable Interrupt (NMI). This

interrupt has absolute priority, and when it occurs, the processor will finish the current

memory cycle, then branch to a special routine written to handle the interrupt request.

Advantages of Interrupts

Interrupts are used to ensure adequate service response times by the processing.

Sometimes, with software polling routines, service times by the processor cannot be

guaranteed, and data may be lost. The use of interrupts guarantees that the processor will

service the request within a specified time period, reducing the likelihood of lost data.

Interrupt Latency

The time interval from when the interrupt is first asserted to the time the CPU recognises

it. This will depend much upon whether interrupts are disabled, prioritized and what the

processor is currently executing. At times, a processor might ignore requests whilst

executing some indivisible instruction stream (read-write-modify cycle). The figure that

matters most is the longest possible interrupt latency time.

Interrupt Response Time

The time interval between the CPU recognising the interrupt to the time when the first

instruction of the interrupt service routine is executed. This is determined by the

processor architecture and clock speed.

The Operation of an Interrupt sequence on the 8086 Microprocessor:

1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an

internal interrupt occurs.

2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt

Acknowledge (INTA) to hardware interface.

3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from

the hardware interface.

50

4. The contents of the flag registers are pushed onto the stack.

5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the

trap or single-step feature.

6. The contents of the code segment register (CS) are pushed onto the Stack.

7. The contents of the instruction pointer (IP) are pushed onto the Stack.

8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP

and from (4 x N +2) into the CS so that the next instruction executes at the interrupt

service procedure addressed by the interrupt vector.

9. While returning from the interrupt-service routine by the Interrupt Return (IRET)

instruction, the IP, CS and Flag registers are popped from the Stack and return to their

state prior to the interrupt.

Basic Definitions

Interrupt request: a signal that needed immediate attention

Interrupt processing: what CPU does in response to request

Interrupt service: what is done in software as a result

• 2 General Types of Interrupts:

External - generated outside CPU by other hardware

Internal - generated within CPU as a result of instruction or operation

• 8086 Terminology for Interrupts:

1) Hardware Interrupt – External, uses INTR and NMI control bus lines

2) Software Interrupt – Internal, from int or into

3) Processor Interrupt – traps, exceptions

51

8086 External Interrupt Connections

Interrupt Vector Table

• x86 has 256 interrupts, specified by Type Number or Vector

• 1 byte of data must accompany each interrupt; specifies Type

• Vector is a pointer (address) into Interrupt Vector Table, IVT

– IVT is stored in memory from 0000:0000 to 0000:03ffh

• IVT contains 256 far pointer values (addresses)

– Far pointer is CS:IP values

• Each far pointer is address of Interrupt Service Routine, ISR

– Also referred to as Interrupt Handler

52

INTERRUPT VECTOR ASSIGNMENT

Type Function Comment

0 Divide Error Processor - zero or overflow

1 Single Step (DEBUG) Processor - TF=1

2 Nonmaskable Interrupt Pin Processor - NMI Signal

3 Breakpoint Processor - Similar to Sing Step

4 Arithmetic Overflow Processor - into

5 Print Screen Key BIOS - Key Depressed

6 Invalid Opcode Processor - Invalid Opcode

7 Coprocessor Not Present Processor - no FPU

8 Time Signal BIOS - From RT Chip (AT - IRQ0)

9 Keyboard Service BIOS - Gen Service (AT - IRQ1)

A - F Originally Bus Ops (IBM PC) BIOS - (AT - IRQ2-7)

10 Video Service Request BIOS - Accesses Video Driver

11 Equipment Check BIOS - Diagnostic

53

12 Memory Size BIOS - DOS Memory

13 Disk Service Request BIOS - Accesses Disk Driver

14 Serial Port Service Request BIOS - Accesses Serial Port Drvr

15 Miscellaneous BIOS - Cassette, etc.

16 Keyboard Service Request BIOS - Accesses KB Driver

Software Interrupts

The 8086 has five predefined interrupts.

Type 0 - Divide error

Type 1 - Single step (Trap flag TF set)

Type 2 - NMI (non-maskable interrupt)

Type 3 - One byte software interrupt for breakpoints

Type 4 - Interrupt on Overflow

Except for type 1, these interrupts can not be disabled, although only type 2 can

occur without specific action by the programmer.

The type 2 interrupt is caused by a low to high transition on the NMI pin of the

8086. This is usually used for emergencies such as a power failure.

External interrupts are maskable by setting the IF flag to zero. These interrupts are

activated by the INTR input pin on the 8086 being asserted while IF = 1.

With external interrupts, the interrupt type is put on the data bus by the

external interrupt controller and read in by the 8086. This occurs during the

second of two interrupt acknowledge cycles.

Interrupt Instructions

The following instructions deal with interrupts.

STI - set IF

CLI - clear IF

INT n - software interrupt, execute interrupt service routine n.

Note n = 3 is the single byte opcode used for breakpoints.

MS-DOS uses this instruction, rather than procedure calls, for

operating system functions.

INTO - interrupt on overflow.

HLT - halt, i.e., wait for interrupt.

IRET - interrupt return (pops IP, CS, and Flags).

The IRET instruction pops the flag register off the stack with IF=1. If IF was

not set, the interrupt could not have occurred in the first place.

54

Note that the Flag register is sometimes referred to as the processor status word or

PSW.

External Interrupts

Assume that IF = 1 and INTR goes high. The following operations occur.

• The current instruction finishes executing.

• The Flags are pushed onto the stack.

• IF is cleared disabling further interrupts. TF is cleared if single stepping.

• CS and IP is pushed onto the stack.

• The first INTA’ is sent to the external interrupt control logic.

• The second INTA’ pulse signals the interrupt control logic to put the vector

number (or type) on the data bus.

• The cpu reads the vector number and multiplies it by four to get the vector

location.

• The CS and IP (vector) of the interrupt service routine (ISR) are loaded.

• The ISR begins executing.

Interrupt Priorities

When several external devices can request interrupts, you often need to assign

priorities as certain interrupts may be more important than others.

This can be done in several ways.

1. Polling - The interrupt requests are all ORed together and the interrupt

service routine reads the status of the devices that could cause an interrupt. The

order of polling sets the priority, i.e., if two devices are requesting an interrupt at

the same time, the first one polled is handled.

2. Daisy Chain - The cable from the computer goes to the most important device,

then from that device to the next most important device, etc. The interrupt

acknowledge is passed from device to device until the device requesting the

interrupt is reached.

3. Priority Management Hardware - Logic prioritizes a number of interrupt

requests and generates one interrupt request to the processor. The standard device

for this purpose is the 8259A Priority Interrupt Controller (PIC). This device can

handle 8 interrupt requests. It can also operate in a master/slave mode where up to

8 slave 8259A’s can be connected to the eight request lines of the master so that up

to 64 external interrupt requests can be handled. The PC-XT has one 8259A and 8

hardware interrupts. The PC-AT has a master and one slave so it can handle 15

hardware interrupts.

55

INTERRUPT PRIORITY

Divide Error, INT n, INTO

Highest

NMI ↓

INTR ↓

Single stepping Lowest

8259A Priority Interrupt Controller

56

Functionality of 8259A

Basic Functions of the 8259A PIC

1. Resolve the priority of the interrupt requests.

2. Issue a single interrupt request to the CPU.

3. Send the interrupt vector number to the CPU.

Status

Can read three registers

1. The Interrupt Request Register (IRR) stores all requests.

2. The In-Service Register (ISR) stores all interrupt levels being serviced.

3. The Interrupt Mask Register (IMR) stores the interrupt request lines being

masked.

The status can be read by writing a suitable command word and then reading.

Nested Interrupts

57

An Example of Actions Taken When Using Fully Nested Interrupts

IR0 is the highest priority interrupt and IR7 is the lowest.

1. Interrupt Flag (IF) is set but no interrupts are in progress.

2. IR2 and IR4 arrive and IR2 is acknowledged as it has the higher priority. In-

service register

bit 2 (ISR2) is set.

3. The IR2 interrupt service routine sets IF. IR1 arrives and interrupts IR2 since

IR1 has a higher

priority and IF=1. ISR1 is now set.

4. IR1 service routine clears ISR1 by sending end-of-interrupt (EOI) command but

further

interrupts can not occur until IF is set. IF is set but nothing happens since no new

high priority

interrupt requests have arrived. The interrupt return takes us back to the IR2

service routine.

5. The IR2 routine sends EOI command clearing ISR2. IR4 is pending, no ISR bits

are set, and

IF=1 so interrupt 4 occurs. ISR4 is set.

6. IR3 arrives but nothing happens since IF is still zero.

7. IF is set and interrupt 3 occurs since it has higher priority than 4. ISR3 and ISR4

are set.

8. The IR3 service routine clears ISR3, sets IF, nothing happens since no new

interrupts are

pending, and the IRET instruction takes us back to the IR4 routine.

9. The EOI command in the IR4 routine clears ISR4. The IRET takes us back to

the IR2 routine.

10. The IRET in the IR2 routine takes us back to the main routine.

58

CHAPTER – 7

Numeric Data Processor- 8087

1. 8087 NDP (numerical data processor) is also known as math co-processor which is

used in parallel with the main processor for number crunching applications, which

would otherwise require complex programming.

2. It is also faster than 8086/8088 processor in performing mathematical computation.

3. It has its own specialized instruction sets to handle mathematical programs.

4. Instruction for 8087 are written in the main program interspersed with the 8086

instructions.

5. All the 8087 instruction codes have 11011 as the most significant bits of their first

code byte.

Internal Architecture of 8087

It is divided into two sections internally Control Unit(CU) & Numeric Execution

Unit (NEU).

NEU execute all the numeric processor instructions

CU receives, read & write memory operands & executes the 8087 control

instructions

These two units works asynchronously with each other

59

CU responsible for communication b/w CPU & Memory also co-coordinating the

Internal Coprocessor execution.

CU internally maintains a parallel queue, identical to status queue of main CPU

CU automatically monitors BHE/S7 line to detect CPU type

8087 uses QS0 & QS1 pins to obtain & identify the instruction fetched by the host

CPU

Identifies coprocessor instructions using ESCAPE code bits

Once CPU recognize ESCAPE code, it triggers the execution of the numeric

processor instruction in 8087

While executing ESCAPE code identifies the coprocessor instruction that requires

memory operand & also one does not require any memory operands

If instruction requires memory operand to be fetched from memory, then the

physical address of the operand is calculated using any one of the addressing modes

allowed in 8086 & a dummy read cycle is initiated by CPU

If the CPU does not require any memory operand , it directly executed.

8087 is ready with execution results, CU gets the control of bus from 8086 &executes

a write cycle to write the results in the memory at the prespecialised address

NEU execute all instructions including arithmetic, logical 68 bit fraction 15 bit

exponent & a sign bit

When NEU begins by it , the CPU recognize that the instruction execution not yet

complete .This make 8086 wait till the busy pin of 8087.

TEST input pin of 8086 goes low.

Microcode control unit generate control signals required for execution of the

instruction

Programmable shifter responsible for shifting the operands during the execution of

instructions like FMUL & FDIV.

60

8087 PIN Diagram

How 8087 uses its registers

61

8087 Data Types

• Binary Integers

• Packed Decimal Numbers

• Real Numbers

• Short Real

• Long Real

• Temporary Real Format

Basically 8087 is used for computation of Real number which can be further

classified as

1. Short Real – 32 bit

2. Long Real – 64 bit

3. Temporary Real – 80 bit

Where S =Sign bit (0 = +ve , 1 = -ve)

Exponent bias (Normalized value)

62

Short Real = 127 (7FH)

Long Real = 1023 (3FF)

Temporary Real = 16383 (3FFFH)

General Formula for Real Number is

Real Number = Sign.2exponent

* Mantissa

Examples:

1. Convert -3F25H in Short real, long real & temporary real format

Solution:

Step 1: Convert to binary

0011 1111 0010 0101

Step 2: Normalize the number

1.1 1111 0010 0101 x 213

Step 3:

Sign = 1

Exponent = 13

Mantissa = 11111 0010 0101

Step 4: Calculate biased exponent

Short Real = 13 + 127 =140 = (10001100)2

Long Real = 13 + 1023 =1036 = (10000001100)2

Temporary Real = 13 + 16383 =16396 = (100000000001100)2

Step 5:

Short Real = 0 10001100 1111100100101…………….0000 (total 32 bits)

Long Real = 0 1000 0001100 1111100100101…………..…….0000 (total 64 bits)

Temporary Real = 0 1000 000 0000 1100 1111100100101 ..……….0000 (total 80 bits)

*****************************************

63

2. Convert (2005.525)10 to short real, long real & temporary real data format.

Solution:


(2005.525)10 = (1111 1010 101. 1000)2


1.111 1010 101 1000 x 210

Step 3:

Sign = 0

Exponent = 10

Mantissa = 111 1010 101 1000


Short Real: 10 + 127 = 137 = (10001001)2

Long Real: 10 + 1023 = 1033 = (1000 0001 001)2

Temporary Real: 10 + 16383 = 16393 = (1000 000 0000 1001)2

Step 5:

Short Real = 0 10001001 11110101011000………….0000 (total 32 bits)

Long Real = 0 1000 0001 001 11110101011000………….0000 (total 64 bits)

Temporary Real = 0 1000 000 0000 1001 11110101011000………….0000 (total 80 bits)

***************************************************************

3. Convert (1231.525)10 to short real, long real & temporary real data format

Answer:


(1231.525)10 = (1001 1001 111. 1000)2


1.001 1001 111 1000 x 210

Step 3:

64

Sign = 0

Exponent = 10

Mantissa = 001 1001 111 1000


Short Real: 10 + 127 = 137 = (10001001)2

Long Real: 10 + 1023 = 1033 = (1000 0001 001)2

Temporary Real: 10 + 16383 = 16393 = (1000 000 0000 1001)2

Step 5:

Short Real = 0 10001001 00110011111000………….0000 (total 32 bits)

Long Real = 0 1000 0001 001 00110011111000………….0000 (total 64 bits)

Temporary Real = 0 1000 000 0000 1001 00110011111000………….0000 (total 80 bits)

********************************************

Example 3

65

Example 4

Example 5

66

Assignment:

1. Convert (ABCD)16 to short real, long real & temporary real data format.

2. Convert (307.1875) to short real, long real & temporary real data format.

3. Convert (178.628) to short real, long real & temporary real data format.

8087 Instructions

It has 68 instruction distributed in six groups

1. Data Transfer Instruction

2. Arithmetic Instruction

3. Compare Instruction

4. Transcendental Instruction

5. Constant load Instruction

6. Coprocessor control Instruction

8087 Example Programs

All Instructions of 8087 are started with F, that means Float, like FADD, FSUB, FMUL, FDIV

e.t.c

1. Write a Program in TASM to calculate Area of Circle. (8087)

DATA SEGMENT

RADIUS DD 5.0

PIE DD 3.14

AREA DD ?

DATA ENDS

CODE SEGMENT


START: MOV AX,DATA

MOV DS,AX

FINIT

FLD RADIUS

FMUL RADIUS

FMUL PIE

FST AREA

INT 03

CODE ENDS

END START

67

2. Write a Program in TASM to calculate Hypotenuse of a triangle using Pythagoras

theorem. (8087)

DATA SEGMENT

SIDE1 DD 5.0

SIDE2 DD 12.0

HYPO DD ?

DATA ENDS

CODE SEGMENT


START: MOV AX,DATA

MOV DS,AX

FINIT

FLD SIDE1

FMUL SIDE1

FLD SIDE2

FMUL SIDE2

FADD

FSQRT

FST HYPO

INT 03

CODE ENDS

END START

68

3. Write a Program in TASM to calculate Roots of quadratic equation. (8087)

DATA SEGMENT

A DD 1.0

B DD 5.0

C DD 6.0

K DD 2.0

X DD ?

X1 DD ?

X2 DD ?

DATA ENDS

CODE SEGMENT

ASSUME CS:CODE, DS:DATA

START: MOV AX,DATA

MOV DS,AX

FINIT

FLD A

FLD C

FMUL ST(0),ST(1)

FADD ST(0),ST(0)

FADD ST(0),ST(0)

FLD B

FMUL ST(0),ST(0)

FSUB ST(0),ST(1)

FSQRT

FST X

FLD K

FLD B

FSUBR ST(0),ST(2)

FDIV ST(0),ST(1)

FST X1

FLD B

FCHS

FSUB ST(0),ST(3)

FDIV ST(0),ST(2)

FST X2

INT 03

CODE ENDS

END START

69

4. Write a Program in TASM to calculate resonant frequency. (8087)

DATA SEGMENT

RES DD 7.0

CAP DD 7.0

C1 DD 1.0

C2 DD 2.0

FREQ DD ?

DATA ENDS

CODE SEGMENT


START: MOV AX,DATA

MOV DS,AX

FINIT

FLD RES

FMUL CAP

FLDPI

FMUL

FMUL C2

FSQRT

FDIVR C1

FST FREQ

INT 03

CODE ENDS

END START

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