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Department of Electrical and Computer Engineering

 © Vishal Saxena -1-IEEE MWSCAS Aug 5, 2012

Delta-Sigma Analog-to-DigitalConvertersRecent Advances 

Vishal Saxena, Boise State University(vishalsaxena@boisestate.edu)

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 © Vishal Saxena -2-IEEE MWSCAS Aug 5, 2012

Employ Loop Delay > 1 Clock Cycle

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-50

-40

-30

-20

-10

0

10

20

Order = 4

OSR = 10OBG

orig= 3

OBGnew = 7

ω / π

   M  a  g  n

   i   t  u   d  e  r  e  s  p  o  n  s  e   (   d   B   )

 

ELD < 1

ELD = 1.5

S/H

R1

C1

Vin

R2

C2

-1

-1

R3

R4

C3

To

Quantizer 

V1

-1

-1

V2

V1

V2

C4

aC4

  k2C4

k3C4

k1C4

DAC   V0

k0C4

V3

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 © Vishal Saxena -3-IEEE MWSCAS Aug 5, 2012

High-Performance CT-∆Σ

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 © Vishal Saxena -4-IEEE MWSCAS Aug 5, 2012

4 GHz Multi-bit CT-∆Σ without DEM

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 © Vishal Saxena -5-IEEE MWSCAS Aug 5, 2012

3.6 GHz Single-bit CT-∆Σ with FIR DAC

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 © Vishal Saxena -6-IEEE MWSCAS Aug 5, 2012

Phase-Domain Integrator and Quantizer

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 © Vishal Saxena -7-IEEE MWSCAS Aug 5, 2012

VCO Quantizer-based All-Digital ∆Σ

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 © Vishal Saxena -8-IEEE MWSCAS Aug 5, 2012

Assisted Opamp for Linearity Improvement

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 © Vishal Saxena -9-IEEE MWSCAS Aug 5, 2012

Assisted Opamp for SCR DAC CT-∆Σ

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 © Vishal Saxena -10-IEEE MWSCAS Aug 5, 2012

DC-RF Tunable ∆Σ ADC

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 © Vishal Saxena -11-IEEE MWSCAS Aug 5, 2012

Future Looking Ideas in CT-∆Σ ADCs

CT-∆Σ ADCs are in their infancy, and scope for innovationis great

Direct RF-Digital Conversion

Multi-band, Multi-Standard, Reconfigurable ADCs Cognitive Radios Cascaded (MASH) DSM: LP, BP and Quadrature

Digital Calibration of Circuit Errors

Parallel∆Σ

ADC (Frequency Band Decomposition) VCO Quantizers and Time/Phase domain signal

processing