Del ay ti me sensitivity a n a lysis of m u It i -g en era t i o n BiCMOS digital circuits

S.S. RofaiI Y. K. Se ng S.Y.Seng

Abstract: The speed sensitivity of BiCMOS circuits to changes in the key MOSiBJT device parameters is analysed. The study takes into account the changes in the forward transit time. the knee current, the collector resistance, the base resistance, and the current gain of the bipolar transistor and the channel length and width, threshold voltage, and oxide thickness of the MOS transistor. The relationships between the key process parameters and the overall speed sensitivity are reported. The analysis also covers the effects of the output load capacitance, scaling the technology, and the quality of the bipolar device on the delay sensitivity. Sensitivity coefficients are defined and generated for the conventional BiCMOS circuit as well as two recently reported circuits designed for low-voltage operation. A method to calculate the worst case speed degradation for a given set of device and process parameters' tolerances is described, HSPICE is used to generate the numerical results for the three technologies ( 5 V, 0.8pm) , (3.3V. 0.5pm), and (2.2V, 0 . 2 ~ ) .

1 Introduction

The performance of BiCMOS circuits as related to its device parameters has been the subject of many studies [1-5]. Accurate models for the BiCMOS gate delay have been sought to study the effects of device scaling [6, 71 and optimise the circuit performance [2, 81. A common observation in almost all the previously reported work is the strong dependency of the BiC- MOS circuit speed on quite a few MOSiBJT device parameters. This, together with the tolerance associated with each device and process parameter, could cause the circuit speed to change in either direction.

The main objective of this work is to find out what tends to occur to the BiCMOS circuit delay if the key device and technology parameters deviate from their nominal values. This is particularly important for scaled technologies and high performance BiCMOS

0 IEE, 1997 IEE Proceedings online no. 19970730 Paper received 22nd January 1996 The authors are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798

where the circuit speed is vulnerable to adverse effects caused by the reduced feature size accompanied by increased tolerances.

2 device/circuit parameters

This Section is aimed at establishing a link between the bipolar process parameters and the key device/circuit parameters affecting the BiCMOS delay time. The process parameters include emitter doping concentra- tion (NE), emitter depth (WE), emitter length (LE), emitter width (BE), emitter area (AE), peak base doping (NB) , base width ( WB), collector doping concentration (Nc). and collector width ( Wc). The following relations will be adopted [11]:

Relationships between the BJT process and

( 3 )

where DIiB and DpE are the diffusion constants of elec- trons in the base and holes in the emitter, respectively. ppB and are the mobilities of holes in the base and electrons in the collector, respectively, vm,, is the maxi- mum carrier velocity, V,, is the base collector voltage, and is the permittivity of silicon. Table 1 shows the percentage change in the key bipolar device/circuit parameters, defined as ai, based on a 215% change in the process parameters' values. The upper values are for a 15?4 increase in the process parameters' values. The results can be used to identify, hence modify if needed, the key process parameters affecting the delay sensitivity.

3 BiCMOS circuit

Sensitivity analysis of the conventional

The delay sensitivity of the conventional BiCMOS circuit, shown in Fig. 1, is analysed and numerically evaluated using HSPICE. The various sensitivity trends

IEE Pwc.-Ci ra i i ts Devices Syst , Vol. 144, No. 2, A p i d I997 60

Table 1: Percentage change in the key BJT device/circuit pararneters based on a 215% change in the process pararneters' values

+ 15.0

- 15.0

- 13.0

+ 17.7

- 0.98

+ 1.32

+ 15.0

- 15.0

+ 32.3 - 13.0

-27.8 + 17.7

- 1.83

+ 2.88

+ 15.0

- 15.0

- 13.0

+ 17.7

+ 15.0

- 15.0

- 13.0

+ 17.7

- 13.0

+ 17.7

- 13.0

+ 17.7

- 13.0

+ 17.7

+ 15.0

- 15.0

- 13.0

+ 17.7

- 13.0

+ 17.7

as related to the device parameters are verified by simple analytical expressions.

vcc

Qi I "0

I 1

Q2 -

Fig. 1 Cotzventioizul BiCMOS circuit

3. I parameters The BiCMOS circuit delay is given approximately by [61:

Delay sensitivity to the key device

IEE P r w -Cirmih Devices Sy.sl., Voi 144, No. 2, April 1597

where is the MOS drain saturation current, V, is the output voltage swing, CO is the output load capacitance, and C, is the sum of the MOS source/ drain parasitic capacitance, the output parasitic capacitance of the gate and the base collector capacitance at the base of bipolar transistor. In deriving eqn. 6, the input PMOS device P I is assumed to operate in the saturation region. This assumption is only valid for submicrometer MOSFETs which have small saturation voltage [13]. Further, at high level injection, the time required to turn on Ql is negligibly small compared to the other two terms in eqn. 6. Therefore, eqn. 6 predicts accurately the delay time for the output voltage to reach V,.,/2 at high level injection (a condition that has been evident in the numerical simulations for C,, 2 0.8pF).

3. I. I Forward transit t ime q: The transient response of the BiCMOS circuit has been shown to be influenced by the bipolar transit time [ 3 , 121. The gate delay is adversely affected by the increase in 3, espe- cially at high level injection, where z/ increases substan- tially with the collector current. The delay sensitivity to 9, based on eqn. 6, is given by:

(7)

3.1.2 Current gain pf : It is widely known that the delay time is inversely proportional to &. Based on eqn. 6, it can be shown that:

where:

Eqn. 8, as will be shown in Sections 3.2, 3.3, and 3.4, helps to show how the delay sensitivity to /jf varies with the load capacitance, scaling, and the quality of the BJT.

3.1.3 Knee current IC. The BiCMOS delay time decreases with ZK [l]. The delay sensitivity to I , can be shown to give a similar trend to that of pf according to:

where:

3.1.4 Base resistance Rb and collector resistance Rc: The base resistance has very little influence on the BiCMOS delay as long as its value is much less than the channel resistance of the PMOS. On

61

the other hand, the collector resistance can affect the delay especially at high collector currents. A large voltage drop across the collector resistance can drive the BJT into saturation thereby increasing the circuit delay. Therefore, it is expected that the delay sensitivity to Rc increases with any variable that causes the BJT to move from nonsaturation towards saturation.

3.1.5 MOS channel width W and length L, oxide thickness Tox, and threshold voltage V,: At low level injection, the BiCMOS delay rd is inversely proportional to W [6]. At high level injection, and as depicted from eqn. 6, t d is proportional to 1iW"'. Hence, the delay sensitivity to W can be affected by other device or circuit parameters according to their influence on the BJT injection level. A similar argu- ment is valid for the MOS oxide thickness, where the circuit delay is proportional to To, at low level injec- tion, and to at high level injection. The delay sensitivities to the MOS channel length and threshold voltage, in the low and high level injections, can be derived as [6, 131:

( I l b )

where VGs is the gate to source voltage and Ec is the critical electric field. It is evident from eqns. 10 and 11 that high level injection tends to reduce the delay sensi- tivity to V , and L.

0 8r

o . 2 ! /

O l T J

2 2.5 3 3.5 1 1 5 5

CO I PF

Fig.2, sets oj 9 and I, 3.3V. 0.5 .m technology

Yp, against CO of conventional BiCMOS circuit for two dlfyerent

3.2 Effects of the load capacitance on the circuit deia y sensitivity The load capacitance affects the BiCMOS delay sensitivity to the key device parameters. As predicted from eqn. 7a, an increase in CO at high level injection causes the delay sensitivity to zr to decrease. CO also affects the delay sensitivity to b' through the factor Yoj Fig. 2 shows Ypj against CO, based on eqn. 8, for two sets of values for 5 and IF As depicted from the Figure Y,!, hence the delay sensitivity to increases with Co. A similar trend is expected for YrK based on eqn. 9a. The delay sensitivity to R, increases with Co. This is attributed to the increased chances of driving the BJT into saturation. It can be shown that, the higher the load capacitance, the lower the collector resistance needed to saturate the transistor [4]. Fig. 3 shows the critical value of R, (defined as the collector resistance to cause Q, to move from nonsaturation to saturation) against the load capacitance for the 0.2pm and 0 . 8 p n technologies used in the analysis. The critical value of R, is obtained by using the analysis in [4, 131. Higher load capacitances also lead to high level injection, hence a lower delay sensitivity to V,, L, W and To, (as explained in Section 3.1.5).

O' 0; 115 2; 3'5 1 115 k CO ,PF

Fig. 3 R, (critical) against C , oj conventional BiCMOS circuit fbr v . 2 ~ and 0 .8 ,m technologies

5 OV. 0.8 urn 2.2v. 0 . 2 : m

0 500 1000 1500 time,ps

Fig.4 time jbr conventional BiCMOS circuit with higf und low qualily BJT C,, = 1 pF, 0 . 8 , m technology

~ high quality BJT - ~ .. low quality BJT

Collector current, normalised with res ect to knee current, aguinst

62 IEE Proc.-Circuits Devices Syst., Vol. 144, No. 2, April 1997

3.3 Effects of the quality of the BJT on the circuit delay sensitivity The forward transit time, the knee current, and the collector resistance are key parameters indicating the qualiliy of the bipolar device. From high quality to low quality: I , decreases between 15% and 2096, while zf and Re increase by factors of = 3 and --- 4, respectively. According to eqn. 7a, eqn. 8a, and eqn. 9u, it can be shown that low quality BJT would cause YTj to decrease slightly, and both Yoj and YIK to decrease sharply, especially at low load capacitances (as illustrated in Fig. 2). Because of the relatively high value of Re, the low quality BJT increases the chances of saturation, which in turn increases the delay sensitivity to R,. especially at high load capacitances. Fig. 4 shows the collector current obtained from HSPICE, normalised with respect to I,, against time for the high and low quality BJT in the 0 . 8 , m technology. It is clear from the Figure that the high quality BJT causes the device to operate deeper in the high level injection mode thereby increasing the delay sensitivities to both fif and IF

3.4 Effects of scaling the technology on the circuit delay sensitivity Scaling the BiCMOS structure affects the MOS and BJT parameters [6]. For example, scaling the technol- ogy from (5V, 0.8,m) to (2.2V, 0.2,m) reduces IK from 2.5 to 1.2mA, zf from 9 to 3.5ps, T,,, from 15 to 6nm, and V, from 0.8 to 0.25V. The decrease in ZJ decreases the factors A and A' in eqn. 8h and eyn. 9b, respectively, hence increases the delay sensitivities to flj and IK through YJpf and YIK.

5 5.2 5.L 5.6 5.8 6 6.2 6.4 6.6 6.8 7 time,ns

vcB( t j and I<.(i) of pull-up trunsient response of conventional ( S V , O.'Rpnj urzd (2.2 V, O . 2 p ~ ) teclinologies and

Fig.5 BiCMOS circuil change of d 5 % in R,

~ -15% in R,. +IS'%, in R ( .

The delay sensitivity to the changes in the value of R, is also affected by scaling. In general, an increase in Rc would result in a decrease of IcAR, in the collector base voltage VcB which, in turn, reduces the collector current IC thereby increasing the delay. Therefore, the lower values of I , that are prevailing in scaled technologies tend to reduce the delay sensitivity to R,. The effect of changing Re on the values of V,, and Z, are shown in Fig. 5, where both VcB and IC show a wider variation for the (5V, 0.8pm) technology than that of the (2.2V, 0 . 2 ~ ) . The higher slope of VcB with time for the 0 . 8 ~ case can be also depicted from the same Figure. This leads to driving the BJT, beyond certain time, deeper into saturation, hence increasing the delay sensitivity to R, even further. The slope

IEE Proc.-Ciriuifs Deviccs Syst., Vol. 144, No. 2, April 1997

6 VC,l& is analytically described by:

where R,,* is the channel resistance of the PMOS and R,, is the base resistance. In deriving eqn. 12, SR,,IGt has been assumed to be negligibly small compared to the other terms. The numerical results have shown that the first term in eqn. 12 is the dominant. Rch (= USd5) has been calculated using the model in [13] to give = 9000 Q and = 3000 Q for the 0 . 8 , m and 0 . 2 ~ tech- nologies, respectively. This, together with the higher valuc of SIBISt for the 0 . 8 , m case explain the steeper slope 6VcB16t for the 0 . 8 ~ technology than that of the 0 .2pn .

3.5 HSPICE simulations Extensive numerical simulations, using HSPICE, have been performed on the conventional BiCMOS circuit to evaluate its delay time sensitivity to the key device parameters. The results have been obtained for the three technologies (5V, 0 . 8 , m ) , (3.3V, 0.5,um), and (2.2V, 0 . 2 p " . For each technology, high and low quality bipolar devices and three different load capaci- tances (O.lpF, IpF, and 5pF) have been considered. Fig. 6 shows the percentage change in Tplh (defined as the propagation delay during which the output voltage changes from low-to-high) for the (5V, 0.8 ,m) technol- ogy, based on a 215%) change in the device parameter's value, togcther with the effects of the load capacitance. Fig. 7 shows a similar set of data, but for the low qual- ity bipolar device. As depicted from the Figures, the results confirm the validity of the analytical description and verify the physical justifications, cited in Sections 3.1 to 3.4 above, for the major trends characterising the delay sensitivity. The results also show that higher load capacitances, in general, yield higher delay sensitivities to Pf, Z,, and Rc. While the BiCMOS employing a low quality BJT gives a relatively poor transient perform- ance, its delay sensitivity to key device parameters, except R,, has been shown to decrease (Section 3.3). The complete set of sensitivity coefficients for the vari- ous BiCMOS technologies is shown in Table 2, where hi is defined to be the ratio between the normalised change in the delay time and the normalised change in the device parameter's value:

where D, is the device parameter under consideration. In Table 2, the letters H and L refer to high and low quality BJT, respectively. The HSPICE model files used in the simulation for the BJT and MOS devices, shown in Tables 3 and 4, respectively, are scaled according to [7] and, apart from the 0 . 2 ~ data, have been verified and extracted from the measurements of a few wafers.

4 voltage, low-power BiCMOS circuits

Sensitivity evaluation and comparison of low-

Scaling the technology has been shown to influence the delay sensitivity (Section 3.4). More specifically, scaling tends to accentuate the sensitivity trends in general and that to /3, and I , in particular. It is widely known, how- ever, that the transient performance offered by the largely scaled conventional BiCMOS structures is rather poor [14, 151 thereby generating a strong need to

63

15

Bf IK RC Rb w L To, "T

0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF 0.lpF 5pF ''1 IpF IPF IPF 1PF 1 PF IPF 1 PF 'PF IPF

Fig. 6 high quality BJT (i) increase of 15'% in device parameters' value

Delay sensitivities, hnseil on 215% ciziirzge 117 clerice paririiierei.s. rqyerher wirli eflects of loud capacitance for ( S V, 0.8,m) technology ,for

(11) decrease ol' I 5 ~ X 111 device parameters' \slue

OlpF 5pF 0.lpF 5pF 0.lpF 5pF OlpF 5pF OlpF 5pF OlpF 5pF OlpF 5pF OlpF 5pF OlpF 5pF IpF IPF 1PF IPF IPF IPF IPF 1PF

-15 ' 1

Fig. 7 loiv quality BJT (i) increase of 15% in device parameter's value

Delay sensitivities, hosed oil d 5 % chuizge in c1evic.c. i~circmerer~, rogetlier with ejects oJIonc1 ccpcitance j b r (S V, 0 .H4m) technology ,for

(i i) decrease of' 15% in de\ice parameter's value

Table 2: Delay sensitivity factors, hi, for conventional BiCMOS circuit

MOS/BJT device parameters 4 Pi I, R, 4 V T L w Tox

5.0V, 0.8pm H CO = 0. lpF 0.161 0.013 0.032 0.027 0.018 0.094 0.288 0.630 0.431

5.0V, 0.8p.m H CO = l .0pF 0.213 0.063 0.062 0,090 0.008 0.084 0.219 0.535 0.432

5.OV,0.8pm H Co=5.0pF 0.179 0.187 0.165 0.131 0.010 0.078 0.189 0.507 0.427

5.OV,0.8pm L C,=O.lpF 0.154 0.005 0.028 0.042 0.026 0.096 0.277 0.756 0.438

5.0V, 0.8pm L CO= l.0pF 0.223 0.019 0.049 0.229 0.023 0.086 0.195 0.519 0.431

5.0V, 0.8pm L CO = 5.0pF 0.107 0.022 0.030 0.488 0.015 0.063 0.145 0.359 0.298

3.3V,0.5pm H C,=O.lpF 0.178 0.016 0.047 0.025 0.023 0.123 0.161 0.634 0.474

3.3V, 0.5pm H C O = l.0pF 0.237 0.081 0.090 0.076 0.014 0.110 0.134 0.565 0.459

3.3V. 0.5" H C O = 5.0pF 0.166 0.230 0 197 0.084 0.010 0.098 0.122 0.523 0.442 3.3V, 0.5pm L CO =O.lpF 0.159 0.006 0.034 0.035 0.033 0.125 0.207 0.602 0.451 3.3V, 0.5w.m L CO = l .0pF 0.269 0.027 0.045 0.188 0.021 0.097 0.132 0.541 0.431 3.3V, 0.5pm L CO = 5.0pF 0.176 0.047 0.057 0.349 0.012 0.067 0.091 0.391 0.325

2.2V,0.2pm H C,=O.lpF 0.158 0.021 0.053 0.020 0.028 0.042 0.052 0.759 0.456

2.2V, 0.2u.m H C O = l.OpF 0.240 0.153 0.148 0.030 0.022 0.038 0.028 0.592 0.453

22V, 0.2pm H C O = 5.0pF 0.081 0.346 0.290 0.057 0.013 0.036 0.019 0.571 0.448

22V, 0.2ym L CO= 0.1pF 0.162 0.009 0.034 0.031 0.062 0.037 0.029 0.490 0.491

2 2 V , 0.2pm L CO= l.OpF 0.200 0.044 0.050 0.123 0.028 0.028 0.018 0.450 0.396

2.2V. 0.2um L C,= 5.0pF 0.137 0.097 0.087 0.385 0.012 0.025 0.007 0.395 0.310 ~~ ~ ~~

64 IEE Proc.-Circuits Devices Sysf., Vol. 144, No. 2, April I997

Table 3: Model files for the MOS device

MOSFET

parameters

(2.2V, 0 . 2 ~ m )

units NMOS PMOS

V 0.2594 -0.270

n m 6.0000 6.0000

Q/sq 47.540 90.000

pF/m 200.00 245.00

pF/m2 580.00 678.70

- 1.0882 0.1416

- 1.0893 0.4831

pF/m 208.00 208.00

pF/m 208.00 208.00

pF/m 819.00 819.00

(3.3V, 0 . 5 ~ ~ m )

NMOS PMOS

(5.0V, 0.8pm)

NMOS PMOS

0.6358 -0.643

12.000 12.000

55.540 100.00

180.00 220.00

500.00 618.70

1.0882 0.1416

1.0893 0.4831

208.00 208.00

208.00 208.00

819.00 819.00

0.8235 -0.818

15.000 15.000

75.540 121.00

150.00 171.70

400.00 498.70

1.0882 0.1416

1.0893 0.4831

208.00 208.00

208.00 208.00

819.88 819.88

Table 4: Model files for the BJT device

High Quality BJT (2.2V, 0 . 2 ~ m ) (3.3V, 0.5pm) (5.0V, 0.8v.m)

Parameters Units NPN PN P N PN PNP NPN PNP

- 80.000 50.000 100.00 60.000 100.00 60.000

1, m A 1.2000 0.6660 1.8000 0.9990 2.5000 1.3880

a ps 3.5000 8.1960 6.0000 14.050 9.0000 21.080

Rc ohm 150.00 150.00 150.00 150.00 150.00 150.00

Re ohm 30.000 60.000 30.000 60.000 30.000 60.000

Rb ohm 500.00 111.10 600.00 133.30 500.00 111.10

c,e fF 5.5000 4.3180 9.0000 7.0660 12.100 9.5000

CIC fF 5.0000 10.000 7.5000 15.000 9.6000 19.200

CIS fF 12.000 23.810 18.200 36.110 25.200 50.000 - 7.2000 3.4900 7.2000 3.4900 7.2000 3.4900 - 1.3000 0.0000 1.3000 0.0000 1.3000 0,0000

I tf m A 1.5000 0.9600 2.0000 1.2800 3.0000 1.9200

I Irr m A 6.0000 3.3600 6.0000 3.3600 9.0000 5.0400

Pf

x tf Vtf

Table 5 : Delay sensitivity factors, hi, for Cct 1 and Cct 2 (3.3 V, 0.5 pm)

MOS/BJT Device Parameters z, Pf IK RC Rb vT W To,

Cct 1 H CO = 0.1pF 0.042 0.003 0.002 0.005 0.033 0.054 0.128 0.289 0.470

Cct 1 H CO= l.0pF

Cct 1 H CO = 5.0pF

Cct 1 L CO = 0.1 pF

Cct 1 L CO = l.0pF

Cct 1 L CO = 5.0pF

Cct 2 H C,=O.lpF

Cct 2 H CO = l.OpF

Cct 2 H CO = 5.0pF

Cct 2 L CO = 0.1pF

Cct 2 L CO= l.0pF

Cct2 L C, = 5 . 0 ~ F

0.157 0.033 0.019 0.058 0.024 0.040 0.099 0.238 0.418

0.084 0.124 0.098 0.192 0.020 0.028 0.048 0.124 0.265

0.042 0.001 0.005 0.008 0.050 0.051 0.121 0.274 0.513

0.128 0.006 0.004 0.108 0.049 0.040 0.062 0.204 0.406

0.084 0.006 0.001 0.310 0.039 0.023 0.048 0.120 0.310

0.175 0.017 0.043 0.024 0.045 0.186 0.392 0.825 0.424

0.275 0.093 0.094 0.076 0.037 0.139 0.252 0.771 0.400

0.145 0.276 0.239 0.064 0.031 0.112 0.218 0.733 0.368

0.171 0.007 0.034 0.036 0.056 0.125 0.254 0.686 0.433

0.222 0.027 0.052 0.096 0.040 0.106 0.185 0.599 0.388

0.199 0.075 0.073 0.224 0.028 0.104 0.171 0.590 0.378

develop new BiCMOS circuits for low-voltage, low- power environments [9, 10, 16, 171. The main objective of this Section is to evaluate and compare the delay sensitivities of the circuits reported in [9, 101 and to find out whether the high performance achieved by these circuits has compromised the delay sensitivity to key device parameters.

Based on the BiCMOS (3.3V, 0.5,um) technology, circuits (1) and (2), reported in [9, lo], respectively, have been simulated using HSPICE, and their delay sensitivities based on a *15'i/o change in the key device

parameters' values are obtained. The comparative evaluation of the delay sensitivity is illustrated in Figs. 8 and 9. The results show that, except for the delay sensitivity to R, at high load capacitances, circuit (1) is less sensitive to changes in the device parameters than both circuit (2) and the conventional BiCMOS circuit. The improved sensitivity of circuit (1) is attributed, in part, to the BiFET effect and the fact that 1, is a fraction of the base current driving the BJT [15]. The detailed sensitivity evaluation and comparison is shown in Table 5 .

IRE /'roc.-Circuits Devims S ~ S I . , Vol. 144, No. 2, April 1997 68

Fig. 8 (3.3 V, 0.5pni) technology: z/. /+ IK, R, uiid RI> a Conventional BiCMOS h Circuit ( I ) c Circuit ( 2 ) (i) incrcase of 15% in device parameter's value

Delay .sensitivities coinparison of coizventioiziil BiCiMOS circuit, circuit ( 1 j and circuit 121, bused on 215% change in device paranleter's value, for

(ii) deci-eaie of 15'%, in dc\ice parameter's value

20

15

-15 a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c i 0.lpF IpF 5pF OlpF IpF 5pF OlpF IpF 5pF 0.lpF IpF 5pF -L "

Fig. 9 (3.3 V, OS1pn) technology: V , L, To, and W

nelav sensitivities coinparison of coiiventioncrl RiCMOS circuit, circuif ( 1 1 cum' circuit (2 ) . based on t15% change in device parwneterk value, j&

Conventional BiCMOS h Circuit (1) < Circuit ( 2 ) (I) increase of. 15%) in device parameter's value (ii) decrea\e of 15% in device parameter's value

5 worst case scenario

Delay sensitivity upper and lower bounds: a

This Section describes a method to predict the maxi- mum possible changes (positive and negative) in the delay time as related to its sensitivity to the process and device parameters and the associated tolerances. The calculation is based on the product of a, shown in Table 1 and a set of sensitivity coefficients A,, defined in eqn. 13, as shown in Tables 2 and 5 . The increase in the delay time resulting from a 2 15%) change in a proc- ess parameter P, is given by:

where A,+ is the relative increase in td normalised with respect to the relative change in the device parameter's value. The positive index in Al indicates that the change in the value of the device parameter has taken place in the direction that causes an increase in tCi- To calculate an upper bound for the delay sensitivity a worst case scenario is adopted. If one process parameter is to be considered, it is taken to be the one causing the maxi- mum increase in tfi. The influence of more than one

process parameter can then be incorporated in eqn. 14 according to their a and A values, with the highest (ah) taken first. Hence, the upper bound for the relative increase in the delay time can be written as:

(%) = U 2=1

where n is the number of process parameters. A similar approach is used to calculate the lower bound for (Atd/ t,J. Fig. 10 shows both the upper and lower bounds for the delay sensitivity of circuits (1) and (2) against the number of process parameters. The results are based on a 21 5% tolerance for all the process parameters. Fig. 10 also shows that the upper bounds for the delay sensitivity are 5 - 12%) and 10 - 22%, while the lower bounds are -5 ~ -10%) and -8 ~ -19%1, for circuits (1) and ( 2 ) , respectively.

6 Conclusions

This paper describes a detailed sensitivity analysis of the BiCMOS circuit delay time. The delay sensitivity to the collector resistance increases with any variable that causes the BJT to move from nonsaturation towards

66 I E E Pwc. -Circuit.r Devices Syst., Vol. 144, No. 2, April 1997

saturation. Such sensitivity to the MOS channel width and length, threshold voltage and oxide thickness is affected by other device or circuit parameters according to their influence on the BJT injection level. It is also concluded that high load capacitances and low quality BJT lead, in general, to increased delay sensitivities to the current gain Pf and the knee current IK. Moreover, scaling the technology tends to accentuate sensitivity trends, especially with respect to changes in Pf and I,. The delay sensitivity performance of two low-voltage BiCMOS circuits have shown to be affected by the cir- cuit (design. A method has been described to calculate, based on a worst case scenario, the upper and lower bounds for the sensitivity as a function of numerically generated coefficients together with the process param- eters’ tolerances. For a *15% tolerance, an upper bound of 5% to 22% for the delay sensitivity could result depending on the kind of BiCMOS circuit used. The presented methodology could be used, in general, to evaluate the delay sensitivities of technologies for comparison purposes.

6 BELLAOUAR, A., EMBABI, S.H.K., and ELMASRY, M.I.: ‘Scaling of digital BiCMOS circuits’, IEEE J. Solid-Stute Circuits, 1990. 25. (4). nn. 932-941 , ~ , , _ I

7

8

ROSSEEL, G.P., and DUTTON, R.W.: ‘Scaling rules for bipolar transistors in BiCMOS circuits’, ZEDM, 1989, pp. 795-798 KURODA, T., SAKATA, Y., and MATSUO, K.: ‘Analysis and optimization of BiCMOS gate circuits’, IEEE J. Solid-Siute Cir- cuits, 1994, 29, (5), pp. 564571

9 YEO, K.S., and ROFAIL, S.S.: ‘Full-swing high speed CBiC- MOS digital circuit for low-voltage applications’, IEE Proc., Cir- cuits, Devices Syst., 1995, 142, (I) , pp. 8-14

10 SHIN, H.J.: ‘Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits’, ZEEE J. Solid-State Circuits, 1990, 25, (3) , pp. 863-865

1 1 EMBABI, S.H.K., BELLAOUR, A., and ELMASRY, M.I.: ‘Digital BiCMOS integrated circuit design’ (Kluwer Academic Publishers, 1993)

12 ZHANG, S., KALKUR, T.S., LEE, S., and CHEN, D.: ‘Analy- sis of the switching speed of BiCMOS buffer under high current’, IEEE J . Solid-State Circuits, 1994, 29, (7), pp, 787-796

13 TOH, K.Y., KO, P.K., and MEYER, R.G.: ‘An engineering model for short-channel MOS devices’, ZEEE J. Solid-Stute Cir- cuits, 1988, 23, (4), pp. 950-958

14 FUJISHIMA, M., ASADA, K., and SUGANO, T.: ‘Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling’, ZEEE J. Solid-Stute Cir- cuits, 1991, 26, (I), pp. 25-31

15 ROFAIL. S.S.: ‘Low-voltaee low-nower BiCMOS dieital circuits’. IEEE J Solid-State C i ~ c u i ~ , 1994: 29, (5) , pp 572-59

16 YANO, K , HTRAKI, M , SHUKURI, S , ONOSE, Y , HIRAO, M , OHKI, N , HISHIDA, T , SEKI, K . and SHIMO- HIGASHI, K ‘Quasi-complementary BiCMOS for sub-3V dig- ital circuits’, ZEEE J Solid-State Circuity, 1991, 26, ( I l ) , pp. 1708-1718

number of process parameters Fig. 10 12) aguinst number of process parameters ut loud of IpF

~ Cct I , 3.3V, 0 S ~ m ~~~ Cct 2, 3.3V, 0 . 5 ~ CO = IpF

Upper and lower bound~s,for deluy sensitivity of circuits (1) and

IReferences

ROSSEEL, G.P., and DUTTON, R.W.: ‘Influence of device parameters on the switching speed of BiCMOS buffers’, ZEEE J. So/id-State Circuits, 1989, 24, ( l ) , pp. 90-99 EMBABI, S.H.K., BELLAOUAR, A., and ELMASRY, M.I.: ‘Analysis and optimization of BiCMOS digital circuit structures’, IE,EE J. Solid-State Circuits, 1991, 26, (4), pp. 676-679 RAJE. P.A.. SARASWAT. K.C.. and CHAM. K.M.: ‘Accurate delay models for digital BiCMOS’, IEEE Tranr Electron Devices, 1902, 39, (6), pp 1456-1464 FANG. W.. BRUNNSCHWEILER. A . and ASHBURN, P ‘An accurate analytical BiCMOS delay expression and its applica- tion to ontimizinc high-meed BiCMOS circuits’. IEEE .I Solid- Stote Cirtuits, 1992, fi, @), pp. 191-202 ROFAIL, S.S., and ELMASRY, M.I.: ‘Analytical and numerical analysis of the delay time of BiCMOS circuits’, IEEE J. Solid-

17 RITTS, R.B., RAJE, P.A., PLUMMER, J.D., SARAS- WAT, K.C., and CHAM, K.M.: ‘Merged BiCMOS logic to extend the CMOSiBiCMOS Derformance crossover below 2.5V supply’, ZEEE J. Solid-State ^Circuits, 1991, 26, (1 l), pp. 1606- 1613

8 Appendix

In this Appendix, the derivation of the delay sensitivity to zf is given. Similarly, the delay sensitivity to P, and IK could be derived.

State Circuits, 1992,-27, (3, pp. 834-839

IEE Proc.-Circuits Devices Syst., Vol. 144, No. 2, April 1997 61