A. Rivetti Villa Olmo, 7/10/2009 Lepix: monolithic detectors for particle tracking in standard very deep submicron CMOS technologies. A. RIVETTI I.N.F.N

A. Rivetti Villa Olmo, 7/10/2009

Lepix: monolithic detectors for particle tracking in standard

very deep submicron CMOS technologies.

A. RIVETTII.N.F.N. sezione di Torino, via P. Giuria 1

Torino, 10125, Italy

W. SNOEYS, M. CASELLE, K. KLOUKINAS

CERN CH-1211, Geneva 23, Switzerland

A. DOROKHOVInstitut de Recherches Subatomiques

23 rue du Loes - BP28- F6703, Strasbourg, FranceP. CHALMET, H. MUGNIER, J. ROUSSET

MIND-MicroTechnologies-Bât. Le Mont Blanc74160, Archamps, France


Motivations

Sensor design

Front-end electronics

Prototyping strategy and R&D timeline.

Conclusions.

Outline


High resolution silicon detectors: state of the art

• Hybrid pixels: detectors and electronics fabricated on different substrates.• Charge collection by drift, good radiation hardness.• Pixel size: 50 m x 50 m to 50 m x 400 m.• Complex front-end electronics, high read-out speed.•Typical power density: 250 mW/cm2.

• MAPS: detector and electronics on the same substrate.• Only commercial CMOS technologies.• Pixel size: 20 m x 20 m or lower.• Slower read-out speed.• Charge collected by diffusion, more sensitive to bulk damage.• Power density for fast options: 100 mW/cm2.• Silicon strips: detector and front-end electronics on different substrates.• Suitable to cover large areas at low particle densities.• Power density: 20mW/cm2.


Exploiting the features of very deep submicron CMOS processes to combine most of the advantages of the previous technologies:

Good radiation hardness (charge collection by drift).

High speed: parallel signal processing for every pixel.

Low power consumption: target 20 mW/cm2.

Monolithic integration.

Use of CMOS technologies with high production rate (20 m2 per day…)

Lepix is a collaboration between CERN, IReS in Strasbourg and INFN.Interest also from Imperial College

Within INFN it is a project funded by the R&D scientific committee.

Lepix goal


First feedback from the foundry that standard deep submicron CMOS processes can be reliably implemented with wafer of higher resistivity (> 100 · cm).

Standard CMOS on lightly doped substrates

Digital groundAnalog ground

Aggressor node

Junction capacitance

Sensitive node

Substrate contactSubstrate contact

Lightly doped substrate


Aggressor node


Sensitive node




Aggressor node


Sensitive node

Substrate contact

Highly doped substrate

Epi-layer


Aggressor node


Sensitive node

Substrate contact


Epi-layer

a) b)


Aggressor node


Sensitive node




Aggressor node


Sensitive node




Aggressor node


Sensitive node

Substrate contact


Epi-layer


Aggressor node


Sensitive node

Substrate contact


Epi-layer

a) b)

Higher substrate resistivity enhances the separation between different circuit blocks (better insulation between digital and analogue).

A resistivity of 200 · cm should allow a uniform depletion layer of 30 m – 40 m with a reverse bias voltage of 100 V.

Collection by drift + moderate resistivity: good radiation hardness (adequate for LHC upgrades).


First sensor concepts

nwell collection diode

Pmos input device.

Charge to voltage conversion on the sensor capacitance For 30 m depletion and 10fF capacitance: 38 mV for 1 mip.

Bias circuit

Processing electronics

Only one PMOS transistor in the pixel. Each pixel is permanently connected to its front-end electronics located at the border of the matrix. Each pixel has one or two dedicated lines: need of ultra fine pitch lithography => 90 nm CMOS.


Issues in sensor design

Challenge is in obtaining a uniform depletion layer.

Optimal geometry and segmentation of the read-out electrode.

Effective charge resetting scheme.

Pattern density rules in very deep submicron technologies are very restrictive.

Insulation of the low-voltage transistors from the high voltage substrate.

Sensor is designed in close contact with the foundry!


Sensor segmentation (1)

Signal is proportional to: ecapacitanc electrodecharge collected

CQ

Noise is proportional to:I m1

gm

1

m=1/2 in weak inversion

m=1/4 in strong inversion

Signal to noise ratio is proportional to: I mCQ m≤1/2

If C and I are reduced by the same factor SNR improves.

The game pays till charge sharing and inter-pixel capacitance come into play

Strategy: have (reasonably) small pixels at the very front-end and group them afterwards according to the required space resolution.


Sensor segmentation (2)

For a full parallel read-out sensor size is also limited by the pitch of the metal lines.

The technology allows for at least five very dense metal layers, possible to have full reticle chips with LHC-grade pixels.


Pmos input device.


Pmos input device.

nwellcollection diode

Pmosinput device.

nwellcollection diode

Pmosinput device.

In practice, to minimize the electrode capacitance and maximize the signal the electrode size will be much smaller than the pixel pitch.

One or two metal lines are needed for every pixel Metal routing and sensor layout must obey the pattern density rules.


Options for resetting the input transistor

Bias circuit


Continuous reset with diodes

Bias circuit


Vref

Continuous reset with transistor

Bias circuit


Vref

Pulsed reset

Vref

Vctrl


Sensor simulations

Pixel used in this simulation was 50 m x 50 m.

With the highest resistivity substrate available 80 m depletion with 100 V


Sensor read-out: source follower configuration

bias

VTH

Only one external line per pixel.

The rise time of the signal, but not its final amplitude sensitive to the parasitic capacitance of the line.

The current signal is converted to a voltage step by integration on the input parasitic capacitance (~ 10 fF). The voltage step is sensed at the source and fed to a preamplifier-shaper-discriminator chain .

Stack of only two transistors.

Margin to operate the sensor at low power supply (0.6 V).

Enough headroom for leakage induced DC variations.


Voltage-mode read-out simulations

Power constrained to 1 W per channel, (sensor, amplifier discriminator).

10 mW/cm2 for 100 m x 100 m pixels

10 fF input capacitance and 1200 electrons signal assumed.

Line capacitance 2 pF.

Peak about 60 mV.

ENC 40 electrons


Possible analogue measurement with ToT

Minimum signal to have response within 25 ns is about 2500 electrons.

Time over threshold can be explored to recover the timing. Trade-off between digital and analogue power consumption

ENC 40 electrons rms.

SNR of 15 for 600 electron signal.

Response delay of 50 ns for 600 electrons.

Time over threshold

Time walk


Current-mode read-out

The current signal is converted to a voltage step by integration on the input parasitic capacitance (~ 10 fF).

Stack of up to six transistors, possible because of weak inversion operation.

Two lines per pixel.

Current read-out allows for very compact current comparator and a more compact front-end cell.

bias

ITHbias

The voltage signal is converted back to a current by the in-pixel transistor.

Both line capacitances play an important role in the shaping of the signal.


Current-mode readout simulations

With current mode 25 ns timing is achieved for 600 electrons and 2 W of power

Time over threshold works also for the current mode approach.

Time over threshold

Time walk


Jitter performance


Matrix readout

Signals are sent in analog form towards the periphery of the matrix.

The clock is distributed only in the periphery.

All NMOS device must be in triple well to insulate them from the “hot” substrate. Custom digital library is needed.

Particular care to manage SEE given the small feature size of the technology.


Matrix readout issues

Analog power basically determined by SNR required. Easily predicted once the analog blocks are defined.

Digital power dependent on the switching activity, so it can be quite different even for the same architecture working under different occupancy conditions.

Area and power must be minimized Data storage is a critical item. Only storage of valid hits.

High pixel granularity is dictated by the optimization of the analog power. Grouping of pixels after the very front-end if space resolution and occupancy requirements allow it.

If the detector has to contribute to trigger primitives also data transmission becomes a very critical issue.

The power of a standard high-speed LVDS transmitter is already a few milli-watts, with a few links the digital power consumption will exceed the analog one.


Prototyping plans

A first submission is in preparation before the end of the year.

Several matrices with different sensor optimization will be implemented.

Sensors will be read-out with a maps-like architecture.

A few simplified front-ends with preamp-shaper and current readout will be also implemented

The design will be already use higher resistivity wafers.

A prototype with more elaborated front.-end and first digital readout schemes will be developed within next year.


Conclusions

A cooperative research effort being established between CERN, INFN and IReS to investigate new type of monolithic sensors.

Technique: commercial very deep submicron CMOS implemented on lightly doped substrates.

Sensors simulation are very encouraging.

A first submission to the foundry scheduled very soon.

First experimental results expected early in 2010.

Documents

A. Rivetti Villa Olmo, 7/10/2009 Lepix: monolithic detectors for particle tracking in standard very deep submicron CMOS technologies. A. RIVETTI I.N.F.N