Decimation 2

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558 IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 1, NO. 4, OCTOBER 2002

On Design and Implementation of a Decimation Filter forMultistandard Wireless Transceivers

Adel Ghazel, Senior Member, IEEE, Lirida Naviner, Member, IEEE, and Khaled Grati, Student Member, IEEE

AbstractIn this work, we deal with the design and implemen-tationof a decimation filter to be used in wideband radio-frequencyreceiver. The paper outlines architecture considerations for multi-standard wireless transceivers. Also, it describes the design stepsand the tradeoffs concerning the hardware implementation. GSMand DECT standards specifications are met by the proposed fil-tering cascade structure. The filter processes six-bits data streaminput from a fourth-order sigmadelta modulator and has beenprototyped in a field-programmable gate array device.

Index TermsDecimation filtering, hardware implementation,sigmadelta conversion, wireless communications.

I. INTRODUCTION

THE development of single-chip receivers became abso-lutely necessary in the last years. In fact, an expanding

growth of wireless communications systems accomplished ofa multitude of standards has been observed [1][3]. Moreover,the competitive market imposes low-cost and low-power de-vices working with several standards. In order to assure theadaptability to different standards, digital processing is moreadvisable than analog processing. In reception process, whenanalog-to-digital conversion is performed before channel selec-tion, it covers severe specifications due to the presence of strongadjacent channel blockers along with the desired signal.

Because of the high in-band signal-to-noise ratio (SNR)proposed by sigmadelta converter, this kind of converter is

currently included in transceivers schemes [4], [5]. Sigmadeltaconverters are designed to shape the noise away from the bandof interest [6]. This oversampling based technique supposesthe use of a digital filter to prevent quantization noise aliasingduring sampling rate decreasing. This decimator filter needsto perform both filtering of the out of band quantization noiseand the adjacent channel blockers. It means that is requiredfrom the filter design to exhibit a high-dynamic range, a pro-grammable bandwidth to accommodate different standards, andprecise tuning to select the desired channel within a standard.Decimation filters must be very efficient computationally sincethe filtering is usually performed at a high rate. Moreover,compactness and cost constraints impose low power and a

small chip area.

Manuscript received October 24, 2001; revised December 8, 2001; acceptedApril 25, 2002. Theeditor coordinatingthe reviewof this paper andapprovingitforpublication is S.S. Lawson. This workwas supportedin part bythe Tunisian-French Technical Collaboration Program.

A. Ghazel and K. Grati are with the UTIC, Ecole Suprieure desCommunications de Tunis (SUPCOM), 2088 Tunis, Tunisia (e-mail:[email protected]; [email protected].).

L. Naviner is with the ComElec, Ecole Nationale Suprieure des Tlcom-munications de Paris (ENST-Paris), 75634, Paris Cedex 13, France (e-mail:[email protected]).

Digital Object Identifier 10.1109/TWC.2002.805093

Several design and implementations of decimation filters forsigmadelta converters are presented in recent papers. Whiteand Elmasry have proposed low-power design techniques formultimode multistage decimation filter adapted to both Mo-bitex and Ardix wireless networks specifications [7]. In theirpaper, a third order comb filter and a first-stage finite-impulseresponse (FIR) filter are common to the two standards and onlya second-stage FIR filter has coefficients and frequencies de-pending on the mode. In [8], authors proposed filter structurewith decimation and sampling rates adapted to global systemformobile communications (GSM) and digital european cordlesstelephone (DECT) applications, they described a low power im-plementation architecture by using nonrecursive architecture for

the comb filter and by simplifying FIR filter multiplications toshifts and adds operations. Implementations based on scalabilityand on the use of the DECOR transformation to reduce powerand area of decimation filters are respectively found in [9] and[10]. By considering GSM and DECT standards requirements,FIR and infinite impulse response (IIR) structures of digital fil-ters have been studied, by authors in [11], then, compared interms of performances and computational complexity. IIR filtersolution with almost linear phase is designed and gives goodresults with less order than FIR filters. But analysis of com-putational complexity shows that, for a decimation factor lessor equal to four, half-band polyphase FIR filters require lessnumber of multiplications since their coefficients are symmetric

and odd ones are equal to zero [11].This paper deals with the design and implementation of a

decimation filter to be used in wideband radio-frequency wire-less systems. A decimation filter cascade structure is designedto meet the GSM and DECT standards specifications [1], [2]and to be very efficient computationally. Since the computationpower depends on the filter order and this one depends on thefilter specifications, the authors propose a practical method tolook for relaxed filter specifications that take into considerationmultistage structure.

This paper is organized as follows. Section II deals with thereceiver architecture choice. Considerations on filter design andits performance analysis are seen in Section III. Hardware im-

plementation is presented in Section IV. Finally, some conclu-sions and future work are outlined in Section V.

II. RECEIVER ARCHITECTURE CONSIDERATIONS

A multistandard wireless system must meet the performancerequirements for each standard and adjust to the differentchannel bandwidths and carrier frequencies. Many receiversarchitectures have been proposed: the conventional super-het-erodyne architecture [12][15], the low intermediate frequency(Low-IF) architecture [4], the wideband intermediate frequency

1536-1276/02$17.00 2002 IEEE
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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 1, NO. 4, OCTOBER 2002 559

Fig. 1. Direct conversion homodyne receiver.

with double conversion (WIF) architecture [5] and directhomodyne conversion [16], [17].

In this work, we consider the direct homodyne conversion re-ceiver because it eliminates many off-chip components. In ho-modyne architecture, all of the channels are frequency translatedto baseband before any channel filtering is performed [16][19].Channel selection can be performed in the analog domain or indigital domain. Analog domain channel selection imposes anR-C high dynamic range, highly linear channel select filter and adifficult programmability, but a relatively easy analog-to-digitalconversion [20], [21]. Inversely, digital channel selection im-poses a high dynamic range of the analog-to-digital converter,but easier possibility of on-chip programmable filter structures

to accommodate the variable channel bandwidth [22]. So, dig-ital channel selectionhas been retained forthis work (see Fig. 1).A fourth-order sigmadelta analog-to-digital converter with a6-b data stream output is considered, with oversampling ratios(OSR) given by 64 (for GSM) and 32 (for DECT). With theseoversampling rates, dynamic range requirement of 98 dB forGSM and 85 dB for DECT can be achieved [23].

III. FILTER STRUCTURE AND DESIGN

Specification of the filter consists on specification of sam-

pling frequency , passband frequency , stopband fre-

quency , transition band , passband ripples

, stopband ripples and phase linearity.The stopband frequency is the half of the Nyquist rate. The

passband is as large as possible (ideally ). Knowledge

of the transmission processing allows efficient design by perti-

nently limit the passband. In fact, filters in the transmitter re-

duce effective information band. Passband ripples is dependent

of the modulation scheme used in the transmission. Supple-

ness is obtained if the information is not on the signal ampli-

tude (but on the frequency/phase). Stopband ripples is in report

with the total noise present in the stopband (quantization noise

and blockers/interferers channels). Many bands may be defined

in order to optimize the stopband requirements, each one com-

posed by blockers/interferers channels and quantization noise.

If only one stopband is considered, the attenuation must to beenough to reduce the worst case blocker noise power according

to carrier-to-noise radio (CNR) requirements [24].

The performance of a decimation filter depends on the type,

the order, and the architecture of the filter. The filter order

depends on the ratio between width of transition band and

sampling frequency of the filter (see [25, eq. (1)])

(1)

where

function depending on and

Fig. 2. Multistage decimation filter structure.

Because sigmadelta converters are oversampled,

carries to high order filters and so too high power computation.

To overcome this problem, the filter can be implemented ina multistage approach [23]. Each stage implements a part of

the filtering and is followed by a down sampling. The filters

running at higher sampling rates have larger transition bands

and filters presenting narrower transition bands run at lower

sampling rates, carrying to lower overall computation needs.

Both output noise power and decimation filter passband ripples

can be calculated at the end of each stage using an equivalent

low-pass transfer function and classic techniques of digital

filtering processing [25].

Comb filters are very interesting for first-stage of decimation

process because they need no multiplier (see [26, eq. (2)]). Un-

fortunately, they present two drawbacks: an insufficient attenua-

tion in stopband and distortion in passband. Insufficient attenu-ation in stop band can be overcome by cascading several filters.

Using a corrector filter can compensate distortion in passband.

(2)

The comb filter is an efficient way to decimate the converter

outputto four times theNyquist rate [26]. For the remainingfour

times of decimation, previous works used a cascade composed

of two half-band filters and a corrector FIR filter [8], [11], [27],

[28]. After analyzing other possible filtering structures a low

computation complexity for required specifications is obtained

with a cascade structure composed of Comb filter followed by

one half band filter and a FIR filter (Fig. 2).

Because we consider a sigmadelta modulator with order

, a cascade of comb filters is necessary

[23]. This comb cascade performs a decimation

factor for the GSM and for the DECT. For

remaining stages the following method is defined to determine

filters specifications.

For half-band filter passband frequency is chosen equal

to channel bandwidth. The stopband frequency is de-

fined by considering the symmetry to . According

to blockers profiles the stopband attenuation is calcu-

lated to obtain an attenuation of out-of-band noise 10 dB

below noise present in transition band. According to inter-ferers profiles the stopband attenuation is calculated

to obtain an attenuation of in band aliased noise 10 dB

below signal level. The worst case is considered for filter

attenuation.

For last stage FIR filter passband frequency is chosen

equal to 82% channel bandwidth. The transition band

is from 82% to 100% channel bandwidth. According to

blockers and interferes profiles the stopband attenuation

is calculated in order to obtain required CNR by

considering in-band signal power and power of noise

components aliased into Nyquist band. The worst case is

considered for filter attenuation.
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Fig. 3. GSM and DECT blockers and interferers specifications at receiver antenna input.

Fig. 4. Comb filter implementation architecture.

By applying this method for decimation filters design to meet

the carrier to noise requirement for the worst case blocking pro-

file and adjacent channel interferers for GSM and DECT stan-dards (Fig. 3) the following specifications are obtained for each

filter.

Half-band filter stage: For GSM standard, a transition

band of 100 kHz and a stopband rejection of dB

are considered. For DECT standard, a transition band

of 700 kHz and a stopband rejection of dB are

considered.

FIR filter stage: For GSM standard, a transition band of

18kHzanda stopbandrejectionof dBareconsidered.

For DECT standard, a transition band of 126 kHz and a

stopband rejection of dB are considered.

IV. FILTER IMPLEMENTATION CONSIDERATIONS

Comb filter can be efficiently implemented by separating its

magnitude response into numerator and denominator sec-

tions and by moving the numerator section after the down-sam-

pling operation (Fig. 4). The denominator is a cascade of ac-

cumulators and the numerator is a cascade of subtractors. A

2s complement wrap-around arithmetic is used to avoid over-

flow problem as long as the register width is greater or equal to

value given by (3)

(3)

Fig. 5. FIR filter implementation architecture.

Half-band and FIR filters can be efficiently implemented with

a polyphase direct-form filter, which allows the filter to run at

the decimated rate instead of the input rate, reducing the com-

putation complexity by approximately one-half. For FIR filters,

which are based on multiplying operations, three hardware im-plementations have been envisaged [28]. In the first solution,

a generic multiplier is in charge of all data-coefficient prod-

ucts. The second solution uses generic adders for multiplication.

The third solution is based on wired adders for each coefficient.

The differences among these solutions concern granularity (par-

allel multiplying for one and serial multiplying for two) and

specificity (generality for onetwo and dedicated coefficients

for three) of the processing.

The filter has been prototyped in a field-programmable

gate array (FPGA). FPGAs are composed of basic logic cells

(LCELLs) and provide reconfigurable hardware, flexible

interconnect, and field-programmable ability. Nevertheless,
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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 1, NO. 4, OCTOBER 2002 561

Fig. 6. Experimental performances of decimation filter.

TABLE IFILTERS COMPUTATIONAL RESULTS

when implementing functions with FPGAs, we need to take

into account two important factors: operative granularity and

routing resources. Basic logic cells input width determinates

the optimal granularity for the input functions to be imple-

mented. Also, limited routing resources can carry to congestion

problems, which increases propagation delay and degrades

area efficiency. Both these limitations were taken into account

in our oriented VHDL modeling [28]. The hardware-optimized

implementation has obtained with the following approach. First

of all, we have evaluated the necessary computation power for

the processing. After this, we have developed an FPGA-adapted

model for the corresponding operators with VHDL. The chosen

solution is those satisfying the demanded computation power

and carrying to the lowest number of LCELLs.

According to experimental results of this study the best com-

promise between cells number and propagation time, for GSM

and DECT filters, is obtained with the generic multiplier-based

implementation solution (Fig. 5) (Table I). Fig. 6 presents signal

spectrum at the decimation filter input and at the decimation

filter output. A 10-bit resolution for filter coefficients digital

format representation is considered to represent coefficients

variation range (0.05 to 0.451).

V. CONCLUSION

In this paper, we have describedthe architecture, the synthesis

and the hardware implementation of a decimation filter designed

for 6-bit data stream input, from a fourth-order sigmadelta

modulator adapted for multistandard wireless receiver. The pro-

totyped filter is based on fifth-order comb filter, one half-bandfilter stages and a FIR correction filter. Obtained results show

that the use of carry ripple adders allows minimizing LCELL

amount for comb filter implementation. For half-band and FIR

correction filters, which are based on multiplying operations, a

single generic multiplier based architecture is the more suitable

solution. Almost all of decimation filters for radio communica-

tions related in literature areusing FIR filters because of theease

with which exactly linear phase could be achieved. However,

linear phase over the entire band is not often required. Future

works include looking for a simplified new method to design an

almost linear phase IIR filters for a given specification of the

allowed phase.
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