1

IPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

tab

12

3

DPAK

DrainPin 2, Tab

GatePin 1

SourcePin 3

MOSFETOptiMOSª3Power-Transistor,30V

Features•FastswitchingMOSFETforSMPS•OptimizedtechnologyforDC/DCconverters•QualifiedaccordingtoJEDEC1)fortargetapplications•N-channel,logiclevel•ExcellentgatechargexRDS(on)product(FOM)•Verylowon-resistanceRDS(on)•Avalancherated•Pb-freeplating•Halogen-freeaccordingtoIEC61249-2-21•Avalancherated•Pb-freeplating;RoHScompliant

Table1KeyPerformanceParametersParameter Value UnitVDS 30 V

RDS(on),max 6 mΩ

ID 50 A

Type/OrderingCode Package Marking RelatedLinksIPD060N03L G PG-TO252-3 060N03L -

1) J-STD20 and JESD22

2

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

TableofContentsDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

1MaximumratingsatTA=25°C,unlessotherwisespecified

Table2MaximumratingsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Continuous drain current ID

----

----

50505043

A

VGS=10V,TC=25°CVGS=10V,TC=100°CVGS=4.5V,TC=25°CVGS=4.5V,TC=100°C

Pulsed drain current1) ID,pulse - - 350 A TC=25°CAvalanche current, single pulse2) IAS - - 50 A TC=25°CAvalanche energy, single pulse EAS - - 60 mJ ID=20A,RGS=25Ω

Reversediodedv/dt dv/dt - - 6 kV/µs ID=50A,VDS=24V,di/dt=200A/µs,Tj,max=175°C

Gate source voltage VGS -20 - 20 V -

Power dissipation Ptot - - 56 W TC=25°C

Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category;DIN IEC 68-1: 55/175/56

2Thermalcharacteristics

Table3ThermalcharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Thermal resistance, junction - case RthJC - - 2.7 K/W -

SMD version, device on PCB,minimal footprint RthJA - - 75 K/W -

SMD version, device on PCB,6 cm² cooling area3) RthJA - - 50 K/W -

1) See figure 3 for more detailed information2) See figure 13 for more detailed information3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.PCB is vertical in still air.

4

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

3ElectricalcharacteristicsatTj=25°C,unlessotherwisespecified

Table4StaticcharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Drain-source breakdown voltage V(BR)DSS 30 - - V VGS=0V,ID=1mAGate threshold voltage VGS(th) 1 - 2.2 V VDS=VGS,ID=250µA

Zero gate voltage drain current IDSS --

0.110

1100 µA VDS=30V,VGS=0V,Tj=25°C

VDS=30V,VGS=0V,Tj=125°C

Gate-source leakage current IGSS - 10 100 nA VGS=20V,VDS=0V

Drain-source on-state resistance1) RDS(on)--

7.25

96 mΩ VGS=4.5V,ID=30A

VGS=10V,ID=30A

Gate resistance RG - 1.4 - Ω -

Transconductance gfs 34 67 - S |VDS|>2|ID|RDS(on)max,ID=30A

Table5DynamiccharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Input capacitance2) Ciss - 1700 2300 pF VGS=0V,VDS=15V,f=1MHzOutput capacitance2) Coss - 640 850 pF VGS=0V,VDS=15V,f=1MHzReverse transfer capacitance2) Crss - 35 52 pF VGS=0V,VDS=15V,f=1MHz

Turn-on delay time td(on) - 5 - ns VDD=15V,VGS=10V,ID=30A,RG=1.6Ω

Rise time tr - 3 - ns VDD=15V,VGS=10V,ID=30A,RG=1.6Ω

Turn-off delay time td(off) - 20 - ns VDD=15V,VGS=10V,ID=30A,RG=1.6Ω

Fall time tf - 3 - ns VDD=15V,VGS=10V,ID=30A,RG=1.6Ω

Table6Gatechargecharacteristics3)Values

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Gate to source charge Qgs - 5.6 - nC VDD=15V,ID=30A,VGS=0to4.5VGate charge at threshold Qg(th) - 2.8 - nC VDD=15V,ID=30A,VGS=0to4.5VGate to drain charge Qgd - 2.5 - nC VDD=15V,ID=30A,VGS=0to4.5VSwitching charge Qsw - 5.3 - nC VDD=15V,ID=30A,VGS=0to4.5VGate charge total2) Qg - 10.8 14.4 nC VDD=15V,ID=30A,VGS=0to4.5VGate plateau voltage Vplateau - 3.2 - V VDD=15V,ID=30A,VGS=0to4.5VGate charge total2) Qg - 22 30 - VDD=15V,ID=30A,VGS=0to10VGate charge total, sync. FET Qg(sync) - 9.4 - nC VDS=0.1V,VGS=0to4.5VOutput charge Qoss - 17 - - VDD=15V,VGS=0V

1) Measured from drain tab to source pin2) Defined by design. Not subject to production test3) See ″Gate charge waveforms″ for parameter definition

5

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

Table7ReversediodeValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Diode continuous forward current IS - - 50 A TC=25°CDiode pulse current IS,pulse - - 350 A TC=25°CDiode forward voltage VSD - 0.88 1.1 V VGS=0V,IF=30A,Tj=25°CReverse recovery charge1) Qrr - - 10 nC VR=15V,IF=IS,diF/dt=400A/µs

1) Defined by design. Not subject to production test

6

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

4Electricalcharacteristicsdiagrams

Diagram1:Powerdissipation

TC[°C]

Ptot[W

]

0 50 100 150 2000

10

20

30

40

50

60

Ptot=f(TC)

Diagram2:Draincurrent

TC[°C]

ID[A

]

0 50 100 150 2000

10

20

30

40

50

60

ID=f(TC);VGS≥10V

Diagram3:Safeoperatingarea

VDS[V]

ID[A

]

10-1 100 101 10210-1

100

101

102

103

1 µs

10 µs

100 µs

1 ms

10 ms

DC

ID=f(VDS);TC=25°C;D=0;parameter:tp

Diagram4:Max.transientthermalimpedance

tp[s]

ZthJC[K

/W]

10-6 10-5 10-4 10-3 10-2 10-1 10010-2

10-1

100

101

0.5

0.2

0.1

0.05

0.02

0.01

single pulse

ZthJC=f(tp);parameter:D=tp/T

7

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

Diagram5:Typ.outputcharacteristics

VDS[V]

ID[A

]

0 1 2 30

20

40

60

80

100

120

4.5 V

5 V

10 V

4 V

3.5 V

3.2 V

3 V

2.8 V

ID=f(VDS);Tj=25°C;parameter:VGS

Diagram6:Typ.drain-sourceonresistance

ID[A]

RDS(on

) [m

Ω]

0 20 40 60 80 1000

4

8

12

16

20

3 V

3.2 V3.5 V

4 V

4.5 V

5 V10 V

11.5 V

RDS(on)=f(ID);Tj=25°C;parameter:VGS

Diagram7:Typ.transfercharacteristics

VGS[V]

ID[A

]

0 1 2 3 4 50

20

40

60

80

100

175 °C

25 °C

ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj

Diagram8:Typ.forwardtransconductance

ID[A]

gfs [S]

0 20 40 60 80 1000

20

40

60

80

100

gfs=f(ID);Tj=25°C

8

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

Diagram9:Drain-sourceon-stateresistance

Tj[°C]

RDS(on

) [m

Ω]

-60 -20 20 60 100 140 1800

2

4

6

8

10

12

98 %

typ

RDS(on)=f(Tj);ID=30A;VGS=10V

Diagram10:Typ.gatethresholdvoltage

Tj[°C]

VGS(th) [V]

-60 -20 20 60 100 140 1800.0

0.5

1.0

1.5

2.0

2.5

VGS(th)=f(Tj);VGS=VDS;ID=250µA

Diagram11:Typ.capacitances

VDS[V]

C[p

F]

0 10 20 30101

102

103

104

Ciss

Coss

Crss

C=f(VDS);VGS=0V;f=1MHz

Diagram12:Forwardcharacteristicsofreversediode

VSD[V]

IF [A]

0.0 0.5 1.0 1.5 2.0100

101

102

103

25 °C175 °C25 °C, 98%175 °C, 98%

IF=f(VSD);parameter:Tj

9

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

Diagram13:Avalanchecharacteristics

tAV[µs]

IAV [A]

10-1 100 101 102 103100

101

102

25 °C100 °C150 °C

IAS=f(tAV);RGS=25Ω;parameter:Tj(start)

Diagram14:Typ.gatecharge

Qgate[nC]

VGS [V]

0 5 10 15 20 25 300

2

4

6

8

10

12

24 V

15 V

6 V

VGS=f(Qgate);ID=30Apulsed;parameter:VDD

Diagram15:Drain-sourcebreakdownvoltage

Tj[°C]

VBR(DSS

) [V]

-60 -20 20 60 100 140 18020

22

24

26

28

30

32

34

VBR(DSS)=f(Tj);ID=1mA

Diagram Gate charge waveforms

10

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

5PackageOutlines

1

REVISION

07

01.04.2020

ISSUE DATE

EUROPEAN PROJECTION

0

SCALE:

2mm

DOCUMENT NO.

Z8B00003328

MILLIMETERS

4.57

2.29

L4

D

N

H

E1

e1

e

E

D1

L3

1.18

0.51

0.89

5.02

9.40

6.35

4.32

5.97

3

b3

A

DIMENSION

b2

c

b

c2

A1

4,95

MIN.

2.16

0.64

0.46

0.65

0.40

0.00

1.78

1.02

5.50

5.84

6.22

6.73

1.27

10.48

5.50

MAX.

2.41

0.15

1.15

0.61

0.89

0.98

L

10:1

Figure1OutlinePG-TO252-3,dimensionsinmm

11

OptiMOSª3Power-Transistor,30VIPD060N03LG

Rev.2.2,2020-09-14Final Data Sheet

RevisionHistoryIPD060N03L G

Revision:2020-09-14,Rev.2.2

Previous Revision

Revision Date Subjects (major changes since last revision)

2.2 2020-09-14 Update POD

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