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Data Conversion Designs forScaled CMOS Technology
Benjamin FroemmingStanford University
6/12/2001EE487 2
Outline
n Quick Data Conversion Tutorialn CMOS Design Challengesn Previous Low-Voltage Techniquesn Possible Low-Voltage Solutionsn Conclusion
6/12/2001EE487 3
Why Data Conversion?
n We live in an Analog world!n BUT, digital processing gives us greater freedom
and performancen Must move between Analog & Digital domains
Analog Domain
Digital Domain
DSP
..01001101..A/D D/A
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Applications
n Consumer Electronicsn Video/Audion Control (Appliances, Automotive)
n Communicationsn Wireless transceiversn Modems
n Instrumentationn Industrial & Scientific Test Equipment
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A/D Conversion
DigitalFilter
Anti-aliasFiltering
Sampling Quantization DigitalCoding
AnalogIn
DigitalOut
DigitalFilter
D àà A
DigitalDecoding
DAC AnalogHold
ReconstructionFiltering
DigitalIn
AnalogOut
D/A Conversion
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ADC Architectures - Nyquist Rate
n Seriesn Integratingn Successive Approximationn Cyclic (Algorithmic)
n Series-Paralleln Pipelinedn Subranging
n Paralleln Flash
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Example: Pipelined ADC
n Trades speed for latencyn Interstage Sample-and-Hold Amplifiersn Size increases linearly with resolution
S/H 2n
A/D D/A
n bits
OutInPipeline Stage
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ADC Architectures - Oversampling
n Predictiven Delta Modulationn DPCM
n Noise Shapingn Sigma-Delta Modulation (Σ∆)n Cascaded Σ∆n Multi-level Σ∆n Interpolating
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Example: Σ∆Σ∆ Modulation
n Trades time resolution for amplitude resolutionn Integrator accumulates difference between
input and quantization signaln Requires digital filtering of results
�
D/A
OutIn1st Order Modulator
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DAC Architectures
n Resistor-Stringn Current-Switched & Voltage-Switched
n Segmentedn Non-segmented
n Charge Redistributionn Segmentedn Non-Segmented
n Interpolating
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Example: Segmented Current-Switch
n Uses equal unitcurrents for MSBs andbinary-weightedcurrents for LSBs.
n Provides monotonicitywith lower area
n Requires asegmented decoder
I/2 I/4 I/8 I/16
I I I I
LSB
MSB
Iout
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Data Conversion Circuit Blocks
n Operational Amplifiersn Sample & Hold Circuitsn Comparatorsn Switched-Capacitor Amplifiers, Integrators, &
Filtersn Current Sourcesn Voltage-Switched & Current-Switched DACsn Reference Circuits
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Switched-Capacitor (SC) Circuits
n Basic building block formany architectures likePipelined & Σ∆
n Clocked CMOS passgates charge/ dis-charge capacitors
n Uses “floating” switches
Simple Integrator
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Why Use Standard CMOS?
n Lower cost & higher reliability of a high-volume process
n Lower power consumption due to scalingsupply voltages
n Integration with high-performance digitalcircuitry
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Continued Scaling of CMOS
n Technology Roadmap for Semiconductorspredicts CMOS will continue to scale pastthe 0.1 micron level.
n Supply voltages also continue todecreasen Great for low power digital designsn Creates challenges for analog design
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CMOS Design Challenges
n Continued technology scaling poses low voltageproblems for analog designsn Thinner gate oxides lower maximum voltage
constraintsn Smaller signal swings result in lower signal-to-noise
ratiosn Transistor thresholds have not scaled with supply
voltages
n Must match analog speed to digital performance
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CMOS Design Challenges 2
Low Headroomn Reduced gate overdrive
results in poor linearity
No Headroomn Floating switches no longer
operaten Switches connected to a
virtual GND are fine
VDD
GND
VTP
VTN
VDD
GND
VTP
VTN
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Previous Low-Voltage Techniques
n Low Threshold Transistorsn Internal Voltage Boostingn Bootstrapped Clocks
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Low Threshold Technologies
n Increases headroom by lowering Vtn Advantagen Allows standard SC circuits to work at lower
voltages
n Disadvantagesn Requires a special processn May cause leakage problems
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Internal Voltage Boosting
n Internal clock signals are typicallyboosted to ~2Vdd to up gate overdrive
n Advantagen Widely used for medium-voltage SC designs
n Disadvantagen Will not work for sub-micron technologies
with tighter voltage constraints
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Bootstrapped Clocks
n Switches are bootstrapped to see a fixedoverdrive
n Advantagen Allows lower voltages on other components
n Disadvantagen Glitches >Vdd may occurn Added Complexity
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Previous Techniques: Conclusion
n Not “true” low-power solutionsn Low-threshold technology not practicaln Boosting/Bootstrappingn Work well for older technologies run at less
than maximum voltagesn Will exceed maximum voltages for sub-
micron processes
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Possible Low-Voltage Solutions
n Switched Op-Ampn Modified Switched-Capacitorn Biased Op-Ampn Multi-Input Floating Gate MOSFETs
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Switched Op-Amp (SO)
n Problem: In regular SC circuits, floatingswitches at input fail under low voltages
n Solution: Replace floating switches withan op-amp that is switched on/offinstead.
n Added op-amp will function where theswitch would not.
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Switch Op-Amp - Continued
n Advantagen Similar to standard SC designsn Additional op-amp doesn’t add to power
n Disadvantagesn On/Off switching of op-amp increases delay
and may introduce transientsn Added complexity and internal loading of
additional op-amp
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Example: 1-V, 9-bit SO ADC
n Architecturen 1.5-bits/stage Pipelined
n Reported Performance
50 dBSNDR:0.5 umProcess:
0.60LSBDNL:1.6 mWPower:
0.90LSBINL:5MS/sRate:
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Modified Switched-Capacitor
n Grounding/Reseting switches areremoved and op-amp is connected inunity-gain feedback
Integrator Gain Stage
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Modified SC - Continued
n Advantagesn Similar to standard SC designsn Switched op-amps not required
n Disadvantagen Requires added complexity to prevent
forward-biasing of junctions in switches(options are shifted-clock, master-slave, orfloating reference).
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Example: 1.5-V, 10-bit SC ADC
n Architecturen 1.5-bits/stage Pipelined
n Reported Performance (Simulated)n 0.25um CMOS Processn 20 MS/sn SNDR of 65-70 dB
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Biased Op-Amps
n Uses non-SC circuitsn S/H or T/H circuits
with a biased op-ampn Current-mode
switching andcomparators
Biased S/H
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Biased Op-Amps - Continued
n Advantagesn No SC floating switchesn Only added complexity is bias generator
n Disadvantagen Resistor Matchingn Only useful for medium accuracy applications
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Example: 1-V, 8-bit ADC & 10-bit DAC
n Architecturen (ADC) Successive Approximationn (DAC) R-2R Resistor String
n Reported Performance
3.00LSBD/A INL:1 MS/sD/A Rate:
1.70LSBD/A DNL:350 uWD/A Power:
1.2 umProcess:
0.47LSBA/D DNL:340 uWA/D Power:
1.14LSBA/D INL:50 kS/sA/D Rate:
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Multi-Input Floating Gate MOSFETs
n Dual gate MOSFET with asecond floating gateperforms as both a currentsource and current switch
n Removes a level ofswitches from DACdesigns
n Minimum supply voltage isonly slightly higher than Vt
P+P+ N-Well
S D
Vb VsFloatingGate
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Floating Gate MOSFETS - Continued
n Advantagesn Realizable in standard CMOS processes with
two poly layersn Can be used with DGMOS for low voltage
operation in older technologies
n Disadvantagen Useful only for DACs (or DAC portion of an
ADC)
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Example: 1-V , 8-bit DAC
n Architecturen Segmented Current-Switch with 31 equal cells and 3
binary cells
n Reported Performance
0.15LSBOffset:1.2 umProcess:
0.80LSBDNL:850 uWPower:
1.09LSBINL:5MS/sRate:
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Possible Solutions: Wrap-up
n The possible solutions are reported to workunder low-voltage conditions in currentprocesses
n These solutions should also scale for newertechnologies
n For DACs, the Floating Gate MOSFETs seem areasonable idea for 2-poly processes
6/12/2001EE487 37
Possible Solutions: ADCs
n Biased Op-amp technique has limited use inhigher accuracy applications because ofresistors
n Modified Switched-Capacitor designs have toomuch added complexity
n I predict that Switched Op-amps will standoutbecause of their close similarity to current SCdesigns
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Conclusion
n Continued scaling of CMOS technologies hascreated design challenges for ADC and DACdesign
n Several solutions for low-voltage ADCs andDACs have been proposed
n Switched Op-amps is the method most likely tosee extensive future use
6/12/2001EE487 39
Referencesn B. Wooley, “EE315 Lecture Notes”, Spring 2001,
www.stanford.edu/class/ee315n U. Moon, et. al., “Switched-Capacitor Circuit Techniques in
Sub-micron Low-Voltage CMOS”, IEEE, 1999n M. Waltari, “1-V 9-Bit Pipelined Switched Op-amp ADC”, IEEE
JSSC, January 2001n M. Steyaert, et. al., “Custom Analog Low Power Design: The
problem of low voltage and mismatch”, IEEE CICC, 1997n S. Karthikeyan, “Low-Voltage Analog Circuit Design Based on
Biased Inverting Opamp Configuration”, IEEE TCS, 2000n S. Mortezapour, et. al. “A 1-V, 8-bit Successive Approximation
ADC in Standard CMOS Process”, IEEE JSSC, April 2000n L. S. Y. Wong, et. al., “A 1-V CMOS D/A Converter with Multi-
Input Floating-Gate MOSFET”, IEEE JSSC, October 1999