DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to …€¢ Fs/2 and ± Fs/4 Coarse Mixer The DAC3283 allows either a complex or real output. • Digital Quadrature Modulator Correction

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DAC3283SLAS693C –MARCH 2010–REVISED MARCH 2015

DAC3283 Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)1 Features 3 Description

The DAC3283 is a dual-channel 16-bit 800 MSPS1• Dual, 16-Bit, 800 MSPS DACs

digital-to-analog converter (DAC) with an 8-bit LVDS• 8-Bit Input LVDS Data Bus input data bus with on-chip termination, optional 2x-– Byte-Wide Interleaved Data Load 4x interpolation filters, digital IQ compensation and

internal voltage reference. The DAC3283 offers– 8 Sample Input FIFOsuperior linearity, noise and crosstalk performance.– Optional Data Pattern CheckerInput data can be interpolated by 2x or 4x through• Multi-DAC Synchronizationon-chip interpolating FIR filters with over 85 dB of• Selectable 2x-4x Interpolation Filters stop-band attenuation. Multiple DAC3283 devices can

– Stop-Band Attenuation > 85 dB be fully synchronized.• Fs/2 and ± Fs/4 Coarse Mixer The DAC3283 allows either a complex or real output.• Digital Quadrature Modulator Correction An optional coarse mixer in complex mode provides

frequency upconversion and the dual DAC output– Gain, Phase and Offset Correctionproduces a complex Hilbert Transform pair. The• Temperature Sensor digital IQ compensation feature allows optimization of

• 3- or 4-Wire Serial Control Interface phase, gain and offset to maximize sideband rejectionand minimize LO feed-through of an external• On-Chip 1.2-V Referencequadrature modulator performing the final single• Differential Scalable Output: 2 to 20 mAsideband RF up-conversion.

• Single-Carrier TM1 WCDMA ACLR: 82 dBc atThe DAC3283 is characterized for operation over thefOUT = 122.88 MHzentire industrial temperature range of –40°C to 85°C• Low Power: 1.3 W at 800 MSPS and is available in a 48-pin 7×7mm QFN package.

• Space Saving Package: 48-pin 7×7mm QFNDevice Information(1)

2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)DAC3283 VQFN (48) 7.00 mm × 7.00 mm• Cellular Base Stations

• Diversity Transmit (1) For all available packages, see the orderable addendum atthe end of the data sheet.• Wideband Communications

• Digital Synthesis

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents8.2 Functional Block Diagram ....................................... 161 Features .................................................................. 18.3 Feature Description................................................. 162 Applications ........................................................... 18.4 Device Functional Modes........................................ 173 Description ............................................................. 18.5 Register Maps ........................................................ 404 Simplified Schematic............................................. 1

9 Application and Implementation ........................ 535 Revision History..................................................... 29.1 Application Information............................................ 536 Pin Configuration and Functions ......................... 49.2 Typical Application ................................................. 537 Specifications......................................................... 6 10 Power Supply Recommendations ..................... 567.1 Absolute Maximum Ratings ...................................... 610.1 Power-up Sequence.............................................. 567.2 ESD Ratings.............................................................. 6

11 Layout................................................................... 577.3 Recommended Operating Conditions....................... 611.1 Layout Guidelines ................................................. 577.4 Thermal Information ................................................. 611.2 Layout Example .................................................... 587.5 Electrical Characteristics – DC Specifications .......... 7

12 Device and Documentation Support ................. 597.6 Electrical Characteristics – AC Specifications .......... 812.1 Documentation Support ....................................... 597.7 Electrical Characteristics – Digital Specifications ..... 912.2 Trademarks ........................................................... 597.8 Timing Requirements ............................................. 1012.3 Electrostatic Discharge Caution............................ 597.9 Typical Characteristics ............................................ 1112.4 Glossary ................................................................ 598 Detailed Description ............................................ 16

13 Mechanical, Packaging, and Orderable8.1 Overview ................................................................. 16Information ........................................................... 59

5 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (June 2012) to Revision C Page

• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section. ................................................................................................ 1

• Moved WCDMA plots from Typical Characteristics to Application Performance Plots ....................................................... 55

Changes from Revision A (April 2010) to Revision B Page

• Changed SDIO description in Terminal Functions Table: SDIO is bidirectional for both 3-pin mode and 4-pin mode.......... 5• Changed Serial Interface section for SDIO operation: first paragraph, "data in only" to "bidirectional"............................... 17• Changed Serial Interface section for SDIO operation: paragraph following Figure 26, "ALARM_SDO is " to "both

ALARM_SDO and SDIO are" ............................................................................................................................................... 19• Changed Figure 29............................................................................................................................................................... 20• Added text to the Input FIFO section beginning at 4th paragraph after Figure 29 .............................................................. 20• Changed Figure 30............................................................................................................................................................... 21• Added config19 - multi_sync_sel to FIFO Modes of Operation section. .............................................................................. 22• Changed Table 3 .................................................................................................................................................................. 22• Added Dual Sync Souces Mode and Single Sync Source Mode sections........................................................................... 22• Changed the Data Pattern Checker section......................................................................................................................... 24• Changed Figure 35............................................................................................................................................................... 25• Changed the DATACLK Monitor section.............................................................................................................................. 25• Changed –3.75 to +3.75 degrees to –7.125 to +7.125 degrees in Quadrature Modulation Correction (QMC) section ...... 31• Changed CONFIG31 default from 0x52 to 0x12 .................................................................................................................. 40• Changed Register CONFIG0 Bit 7 to Reserved, also changed Bit 5 function to Allows the FRAME input to reset the

FIFO write pointer when asserted. Changed Bit 4 function first sentence to Allows the FRAME or OSTR signal toreset the FIFO read pointer when asserted. ....................................................................................................................... 41

• Changed in Register CONFIG2 Bit 4, Function description from Normal FIFO_ISTR to Normal FRAME .......................... 42

2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: DAC3283


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DAC3283www.ti.com SLAS693C –MARCH 2010–REVISED MARCH 2015

• Changed Register CONFIG7 Bit 6 Function and deleted Bit 4 Function ............................................................................. 44• Changed Register CONFIG8 IO Test Function from "word" failed to "byte-wide LVDS bus" failed .................................... 44• Changed Register CONFIG18 Bit 1 Function ...................................................................................................................... 47• Changed Power-up Sequence section ................................................................................................................................. 56

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6 Pin Configuration and Functions

RGZ (VQFN) Package(Top View)

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

37, 40, 42,AVDD33 I Analog supply voltage. (3.3 V)45, 481.8V CMOS output for ALARM condition. The ALARM output functionality is defined through theCONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0ALARM_SDO 34 O alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serialinterface mode (CONFIG 23 sif4_ena = '1').

BIASJ 43 O Full-scale output current bias. For 20mA full-scale output current, connect a 960Ω resistor to GND.Internal clock buffer supply voltage. (1.8 V) It is recommended to isolate this supply from DACVDD18CLKVDD18 1, 35 I and DIGVDD18.LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ωtermination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with twodata transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this

9, 11, 13, single 8-bit data bus using FRAMEP/N as a frame strobe indicator.D[7..0]P 15, 21, 23, I

D7P is most significant data bit (MSB) – pin 925, 27D0P is least significant data bit (LSB) – pin 27

The order of the bus can be reversed via CONFIG19 rev bit.LVDS negative input data bits 0 through 15. (See D[7:0]P description above)10, 12, 14,

D[7..0]N 16, 22, 24, I D7N is most significant data bit (MSB) – pin 1026, 28 D0N is least significant data bit (LSB) – pin 28

DACCLKP 3 I Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.DACCLKN 4 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)

DAC core supply voltage. (1.8 V) It is recommended to isolate this supply from CLKVDD18 andDACVDD18 2, 36 I DIGVDD18.




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Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.

LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor.DATACLKP 17 I Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data

transfers input per DATACLKP/N clock cycle.DATACLKN 18 I LVDS negative input data clock. (See DATACLKP description)DIGVDD18 8, 29 I Digital supply voltage. (1.8V) It is recommended to isolate this supply from CLKVDD18 and DACVDD18.

Used as external reference input when internal reference is disabled through CONFIG25 extref_ena =EXTIO 44 I/O '1'. Used as internal reference output when CONFIG25 extref_ena = '0' (default). Requires a 0.1µF

decoupling capacitor to AGND when used as reference output.LVDS frame indicator positive input. This positive/negative pair has an internal 100Ω terminationresistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the beginningFRAMEP 19 I of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should be edge-aligned with D[7:0]P/N.

FRAMEN 20 I LVDS frame indicator negative input. (See the FRAMEN description)5, ThermalGND I Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies.Pad

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a fullIOUTA1 38 O scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input

results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin.A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1

IOUTA2 39 O described above. An input data value of 0x0000 results in a 0 mA sink and the most positive voltage onthe IOUTA2 pin.

IOUTB1 47 O B-Channel DAC current output. Refer to IOUTA1 description above.IOUTB2 46 O B-Channel DAC complementary current output. Refer to IOUTA2 description above.

LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge ofOSTRP 6 I DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can

be left floating.OSTRN 7 I LVPECL output strobe negative input. (See the OSTRP description)SCLK 32 I 1.8V CMOS serial interface clock. Internal pull-down.SDENB 33 I 1.8V CMOS active low serial data enable, always an input to the DAC3283. Internal pull-up.

1.8V CMOS serial interface data. Bi-directional in both 3-pin mode (default) and 4-pin mode. InternalSDIO 31 I/O pull-down.1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled. When

TXENABLE 30 I TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal pull-down.Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect toVFUSE 41 I DACVDD18 pins for normal operation.




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7 Specifications

7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITDACDVDD18 (2) –0.5 2.3 VDIGVDD18 (2) –0.5 2.3 V

Supply voltage CLKVDD18 (2) –0.5 2.3 VrangeVFUSE (2) –0.5 2.3 VAVDD33 (2) –0.5 4 VCLKVDD18 to DIGDVDD18 –0.5 0.5 VDACVDD18 TO DIGVDD18 –0.5 0.5 VD[7..0]P ,D[7..0]N, DATACLKP, DATACLKN, FRAMEP, FRAMEN (2) –0.5 DIGVDD18 + 0.5 V

Terminal voltage DACCLKP, DACCLKN, OSTRP, OSTRN (2) –0.5 CLKVDD18 + 0.5 VrangeALARM_SDO, SDIO, SCLK, SDENB, TXENABLE (2) –0.5 DIGCLKVDD18 + 0.5 VIOUTA1/B1, IOUTA2/B2 (2) –1.0 AVDD33 + 0.5 VEXTIO, BIASJ (2) –0.5 AVDD33 + 0.5 V

Peak input current (any input) 20 mAPeak total input current (all inputs) –30 mAOperating free-air temperature range, TA: DAC3283 –40 85 °CStorage temperature range, TSTG –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

7.2 ESD RatingsVALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT1.8-V DAC core supply voltage, DACDVDD18 1.7 1.8 1.9 V1.8-V digital supply voltage, DIGVDD18 1.7 1.8 1.9 V

Voltage1.8-V internal clock buffer supply voltage, CLKVDD18 1.7 1.8 1.9 V3.3-V analog supply voltage, AVDD33 3.0 3.3 3.6 V

7.4 Thermal InformationRGZ (VQFN)

THERMAL METRIC (1) UNIT48 PINS

RθJA Junction-to-ambient thermal resistance 26.3RθJC(top) Junction-to-case (top) thermal resistance 12.2RθJB Junction-to-board thermal resistance 3.7

°C/WψJT Junction-to-top characterization parameter 0.2ψJB Junction-to-board characterization parameter 3.6RθJC(bot) Junction-to-case (bottom) thermal resistance 0.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.




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7.5 Electrical Characteristics – DC Specificationsover operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RESOLUTION 16 Bits

DC ACCURACY

DNL Differential nonlinearity ±2LSB1 LSB = IOUTFS/216

INL Integral nonlinearity ±4

ANALOG OUTPUT

Coarse gain linearity ±0.04 LSB

Offset error Mid code offset ±0.01 %FSR

With external reference ±2 %FSRGain error

With internal reference ±2 %FSR

Gain mismatch With internal reference –2 2 %FSR

Minimum full scale output current 2 mANominal full-scale current, IOUTFS = 16 x IBIAScurrent.Maximum full scale output current 20 mA

Output compliance range (1) IOUTFS = 20 mA AVDD –0.5V AVDD +0.5V V

Output resistance 300 kΩ

Output capacitance 5 pF

REFERENCE OUTPUT

Vref Reference output voltage 1.14 1.2 1.26 V

Reference output current (2) 100 nA

REFERENCE INPUT

VEXTIO Input voltage range 0.1 1.2 1.25 VExternal reference mode

Input resistance 1 MΩ

Small signal bandwidth 472 kHz

Input capacitance 100 pF

TEMPERATURE COEFFICIENTS

ppm ofOffset drift With external reference ±1 FSR/°C

±15 ppm ofGain drift With internal reference FSR/°C±30

Reference voltage drift ±8 ppm/°C

POWER SUPPLY

AVDD33 3.0 3.3 3.6 V

DACVDD18, DIGVDD18, CLKVDD18 1.7 1.8 1.9 V

I(AVDD33) Analog supply current 149 mA

I(DIGDVDD) Digital supply current 340 mAMode 1 (below)

I(DACVDD18) DAC supply current 55 mA

I(CLKVDD18) Clock supply current 37 mA

Mode 1: fDAC = 800MSPS, 1300 1450 mW4x interpolation, Fs/4 mixer on, QMC on

Mode 2: fDAC = 491.52MSPS, 1000 mW2x interpolation, Mixer off, QMC on

Mode 3: Sleep modeP Power dissipation fDAC = 800MSPS, 4x interpolation, Fs/4 mixer on, 750 mW

CONFIG24 sleepa, sleepb set = 1

Mode 4: Power-Down modeNo clock, static data pattern, 7 18 mWCONFIG23 clkpath_sleep_a, clkpath_sleepb set = 1CONFIG24 clkrecv_sleep, sleepa, sleepb set = 1

PSRR Power supply rejection ratio DC tested ±0.2 %FSR/V

T Operating range –40 25 85 °C

(1) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,resulting in reduced reliability of the DAC3283 device. The upper limit of the output compliance is determined by the load resistors andfull-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(2) Use an external buffer amplifier with high impedance input to drive any external load.




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7.6 Electrical Characteristics – AC Specificationsover operating free-air temperature range (unless otherwise noted)


ANALOG OUTPUT (1)

1x Interpolation 312.5

fDAC Maximum DAC output update rate 2x Interpolation 625 MSPS

4x Interpolation 800

ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns

tpd Output propagation delay DAC outputs are updated on the falling edge of DAC clock. 2 nsDoes not include digital latency (see below).

tr(IOUT) Output rise time 10% to 90% 220 ps

tf(IOUT) Output fall time 90% to 10% 220 ps

IOUT current settling to 1% of IOUTFS. Measured fromDAC wake-up time SDENB rising edge; Register CONFIG24, toggle sleepa 90

from 1 to 0.Power-up µstime IOUT current settling to less than 1% of IOUTFS. MeasuredDAC sleep time from SDENB rising edge; Register CONFIG24, toggle 90

sleepa from 0 to 1.

1x Interpolation 59DAC2x Interpolation 139

Digital latency clock4x Interpolation 290 cyclesQMC 24

AC PERFORMANCE (2)

fDAC = 800 MSPS, fOUT = 20.1 MHz 85Spurious free dynamic range (0 toSFDR fDAC = 800 MSPS, fOUT = 50.1 MHz 76 dBcfDAC/2)Tone at 0 dBFS

fDAC = 800 MSPS, fOUT = 70.1 MHz 72

fDAC = 800 MSPS, fOUT = 30 ± 0.5 MHz 93Third-order two-tone intermodulationdistortionIMD3 fDAC = 800 MSPS, fOUT = 50 ± 0.5 MHz 90 dBcEach tone at –12 dBFS fDAC = 800 MSPS, fOUT = 100 ± 0.5 MHz 86

fDAC = 800 MSPS, fOUT = 10.1 MHz 162NSD Noise spectral density tone at 0dBFS dBc/Hz

fDAC = 800 MSPS, fOUT = 80.1 MHz 160

fDAC = 737.28 MSPS, fOUT = 30.72MHz 85Adjacent channel leakage ratio, single dBccarrier fDAC = 737.28 MSPS, fOUT = 153.6MHz 81WCDMA (3)

fDAC = 737.28 MSPS, fOUT = 30.72MHz 91Alternate channel leakage ratio, single dBccarrier fDAC = 737.28 MSPS, fOUT = 153.6MHz 85

Channel isolation fDAC = 800 MSPS, fOUT = 10MHz 84 dBc

(1) Measured single-ended into 50Ω load.(2) 4:1 transformer output termination, 50Ω doubly terminated load(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at fOUT, PAR = 12dB. TESTMODEL 1, 10 ms




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7.7 Electrical Characteristics – Digital Specificationsover operating free-air temperature range (unless otherwise noted)


LVDS INTERFACE:D[7:0]P/N, DATACLKP/N, FRAMEP/N (1)

Byte-wide DDR formatfDATA Input data rate 312.5 MSPSDATACLK frequency = 625 MHz

fBUS Byte-wide LVDS data transfer rate 1250 MSPS

VA,B+ Logic high differential input voltage threshold 150 400 mV

VA,B– Logic low differential input voltage threshold –150 –400 mV

VCOM Input common mode 0.9 1.2 1.5 V

ZT Internal termination 85 110 135 Ω

CL LVDS Input capacitance 2 pF

TIMING LVDS INPUTS: DATACLKP/N DOUBLE EDGE LATCHING – See Figure 40

Setup time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge ofts(DATA) –25 psto either edge of DATACLKP/N DATACLKP/N only

Hold time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge ofth(DATA) 375 psafter either edge of DATACLKP/N DATACLKP/N only

t(FRAME) FRAMEP/N pulse width fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns

Maximum offset between DATACLKP/N and FIFO bypass mode only fDACCLK is 1/2fDACCLKt_align nsDACCLKP/N rising edges DACCLK frequency in MHz –0.55

CLOCK INPUT (DACCLKP/N)

Duty cycle 40% 60%

Differential voltage (2) 0.4 1.0 V

DACCLKP/N Input Frequency 800 MHz

OUTPUT STROBE (OSTRP/N)

fOSTR = fDACCLK / (n × 8 × Interp) where n is fDACCLK / (8fOSTR Frequency any positive integer fDACCLK is DACCLK x interp)frequency in MHz

Duty cycle 40% 60%

Differential voltage 0.4 1.0 V

TIMING OSTRP/N INPUT: DACCLKP/N RISING EDGE LATCHING

Setup time, OSTRP/N valid to rising edge ofts(OSTR) 200 psDACCLKP/N

Hold time, OSTRP/N valid after rising edgeth(OSTR) 200 psof DACCLKP/N

CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE

VIH High-level input voltage 1.25 V

VIL Low-level input voltage 0.54 V

IIH High-level input current –40 40 μA

IIL Low-level input current –40 40 μA

CI CMOS input capacitance 2 pF

DIGVDD18Iload = –100 μA V–0.2VOH ALARM_SDO, SDIO

0.8 xIload = –2mA VDIGVDD18

Iload = 100 μA 0.2 VVOL ALARM_SDO, SDIO

Iload = 2 mA 0.5 V

(1) See LVDS INPUTS section for terminology.(2) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.




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7.8 Timing RequirementsMIN NOM MAX UNIT

SERIAL PORT TIMING – See Figure 26 and Figure 27Setup time, SDENB to rising edgets(SDENB) 20 nsof SCLKSetup time, SDIO valid to risingts(SDIO) 10 nsedge of SCLKHold time, SDIO valid to risingth(SDIO) 5 nsedge of SCLK

Register CONFIG5 read (temperature sensor read) 1 µst(SCLK) Period of SCLK

All other registers 100 nsRegister CONFIG5 read (temperature sensor read) 0.4 µs

t(SCLKH) High time of SCLKAll other registers 40 nsRegister CONFIG5 read (temperature sensor read) 0.4 µs

t(SCLKL) Low time of SCLKAll other registers 40 ns

Data output delay after falling edgetd(Data) 10 nsof SCLK




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7.9 Typical Characteristics

Figure 2. Differential Non-LinearityFigure 1. Integral Non-Linearity

Figure 4. Second Harmonic vs Input ScaleFigure 3. Spurious Free Dynamic Range vs Input Scale

Figure 6. Spurious Free Dynamic Range vs InterpolationFigure 5. Third Harmonic vs Input Scale




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-10

0

10

Po

we

r -

dB

m

f - Frequency - MHz

4x Interpolation, 0 dBFSf = 800 MSPS,

f = 150 MHzDAC

OUT

50

55

60

65

70

75

80

85

90

95

100

IMD

3 -

dB

c

0 50 100 150 200 250 300 350

f - MHzOUT

0 dBFS-6 dBFS

-12 dBFS


Tones at f ±0.5 MHz,

IOUTFS = 20 mA

DAC

OUT

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Po

we

r -

dB

m

10 60 110 160 210f - Frequency - MHz

2x Interpolation,f = 500 MSPS,

f = 50 MHzDAC

OUT

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Po

we

r -

dB

m

10 60 110 160 210f - Frequency - MHz

2x Interpolation,f = 500 MSPS,

f = 100 MHzDAC

OUT

f = 200 MSPSDAC

f = 400 MSPSDAC

f = 800 MSPSDAC

50

55

60

65

70

75

80

85

90

95

100S

FD

R -

Sp

uri

ou

s F

ree

Dy

na

mic

Ra

ng

e -

dB

c

0 50 100 150 200 250 300 350f - MHzOUT

4x Interpolation, 0 dBFSIOUTFS = 20 mA

20 mA

10 mA

2 mA

50

55

60

65

70

75

80

85

90

95

100

SF

DR

- S

pu

rio

us

Fre

e D

yn

am

ic R

an

ge

- d

Bc

0 50 100 150 200 250 300 350f - MHzOUT


0 dBFSDAC


Typical Characteristics (continued)

Figure 8. Spurious Free Dynamic Range vs IOUTFSFigure 7. Spurious Free Dynamic Range vs fDAC

Figure 9. Single Tone Spectral Plot Figure 10. Single Tone Spectral Plot

Figure 12. IMD3 vs Input ScaleFigure 11. Single Tone Spectral Plot




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140

145

150

155

160

165

170

0 20 40 60 80 100 120 140 160f - MHzOUT

1x interpolation

2x interpolation

4x interpolation

NS

D -

dB

c/H

z

f = 312.5 MSPS, 0 dBFS,

IOUTFS = 20 mADAC

130

135

140

145

150

155

160

165

170

f = 200 MSPSDAC

f = 400 MSPSDAC

f = 800 MSPSDAC

0 50 100 150 200 250 300 350

f - MHzOUT

NS

D -

dB

c/H

z

4x interpolation, 0 dBFS,IOUTFS = 20 mA

50

55

60

65

70

75

80

85

90

95

100

105

20 mA10 mA

2 mA

0 50 100 150 200 250 300 350

f - MHzOUT

IMD

3 -

dB

c


Tones at f ±0.5 Mhz, 0 dBFSDAC

OUT

130

135

140

145

150

155

160

165

170

0 50 100 150 200 250 300 350

f - MHzOUT

NS

D -

dB

c/H

z0 dBFS

-6 dBFS

-12 dBFS


IOUTFS = 20 mADAC

f = 200 MSPSDAC

f = 400 MSPSDAC

f = 800 MSPSDAC

50

55

60

65

70

75

80

85

90

95

100

IMD

3 -

dB

c

0 50 100 150 200 250 300 350

f - MHzOUT

4x Interpolation,Tones at f ±0.5 MHz,

0 dBFS, IOUTFS = 20 mAOUT

65

70

75

80

85

90

95

100

0 20 40 60 80 100 120 140 160

1x interpolation

2x interpolation

4x interpolation

IMD

3 -

dB

c

f - MHzOUT

f = 312.5 MSPS,

Tones at f ±0.5 MHz,

0 dBFS, IOUTFS = 20 mA

DAC

OUT



Figure 13. IMD3 vs Interpolation Figure 14. IMD3 vs fDAC

Figure 16. NSD vs Input ScaleFigure 15. IMD3 vs IOUTFS

Figure 17. NSD vs Interpolation Figure 18. NSD vs fDAC




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0

5

10

15

20

25

30

35

40

0 100 200 300 400 500 600 700 800 900

CL

KV

DD

18

- m

A

f - MSPSDAC

0

10

20

30

40

50

60

70

80

0 100 200 300 400 500 600 700 800 900

DA

CV

DD

18

- m

A

f - MSPSDAC

Mixer On

Mixer Off

2x

1x

4x

QMCMixer

0

200

400

600

800

1000

1200

f - MSPSDAC

0 100 200 300 400 500 600 700 800 900

Po

we

r -

mW

0

50

100

150

200

250

300

350

2x

0 100 200 300 400 500 600 700 800 900

DV

DD

18

- m

A

f - MSPSDAC

1x

4x

QMC Mixer

65

70

75

80

85

90

95

100

0 50 100 150 200 250 300

Adjacent 0 dBFS

Adjacent -6 dBFS

Alternate 0 dBFS

Alternate -6 dBFS

f - MHzOUT

AC

LR

- d

Bc

f = 737.28 MSPS, 4x Interpolation,

IOUTFS = 20 mADAC

60

65

70

75

80

85

0 50 100 150 200 250 300

ACLR, 0 dBFS

ACLR -6 dBFS

Aternate, 0 dBFS

Alternate, -6 dBFS

f - MHzOUT

AC

LR

- d

Bc

f = 737.28 MSPS, 4x Interpolation,

IOUTFS = 20 mADAC



Figure 20. Four Carrier WCDMA ACLR vs Input ScaleFigure 19. Single Carrier WCDMA ACLR vs Input Scale

Figure 21. Power vs fDAC Figure 22. DVDD18 vs fDAC

Figure 23. DACVDD18 vs fDAC Figure 24. CLKVDD18 vs fDAC




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0

20

40

60

80

100

120

140

160

180

200

0 100 200 300 400 500 600 700 800 900

AV

DD

33

- m

A

f - MSPSDAC



Figure 25. AVDD33 vs fDAC




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100

100

Pa

ttern

Test

De-i

nte

rle

ave

8S

am

ple

FIF

O16

16

100

x2

x2

Coa

rse

Mix

er

Fs/4

,-F

s/4

,F

s/2

QM

C

Ph

ase

an

dG

ain

1.2 V

Reference

16-b

DAC

16-b

DAC

Control InterfaceTemp

Sensor

Clock Distribution

A

gain

B

gainFrame Strobe

EXTIO

BIASJ

IOUTA1

IOUTA2

IOUTB1

IOUTB2

DACCLKP

DACCLKN

DATACLKP

DATACLKN

D7P

D7N

D0P

D0N

FRAMEP

FRAMEN

OSTRP

OSTRN

QMC

A-offset

QMC

B-offset

AL

AR

M_

SD

O

SD

IO

SD

EN

B

SC

LK

TX

EN

AB

LE

AVDD33

CL

KV

DD

18

DIG

VD

D1

8

VF

US

E

DA

CV

DD

18

GN

D

LVPECL

LVDS

LVPECL

LVDS

LVDS

FIR1FIR0

59 taps 23 taps

100

LVDS

x2

x2

Pro

gra

mm

able

De

lay

(0-3

T)


8 Detailed Description

8.1 OverviewThe DAC3283 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with an 8-bit LVDS inputdata bus with on-chip termination, optional 2x-4x interpolation filters, digital IQ compensation and internal voltagereference. Input data can be interpolated by 2x or 4x through on-chip interpolating FIR filters with over 85 dB ofstop-band attenuation. Multiple DAC3283 devices can be fully synchronized. The DAC3283 allows either acomplex or real output. An optional coarse mixer in complex mode provides frequency upconversion and the dualDAC output produces a complex Hilbert Transform pair. The digital IQ compensation feature allows optimizationof phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an externalquadrature modulator performing the final single sideband RF up-conversion.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Definition Of Specifications

8.3.1.1 Adjacent Carrier Leakage Ratio (ACLR)Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset fromthe carrier with a 12dB peak-to-average ratio.

8.3.1.2 Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR)Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect tothe ideal IOUT current.

8.3.1.3 Differential Nonlinearity (DNL)Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code.




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Feature Description (continued)8.3.1.4 Gain DriftDefined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value atambient (25°C) to values over the full operating temperature range.

8.3.1.5 Gain ErrorDefined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and theideal full-scale output current.

8.3.1.6 Integral Nonlinearity (INL)Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight linedrawn from zero scale to full scale.

8.3.1.7 Intermodulation Distortion (IMD3, IMD)The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of the worst 3rd-order (or higher)intermodulation distortion product to either fundamental output tone.

8.3.1.8 Offset DriftDefined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value atambient (25°C) to values over the full operating temperature range.

8.3.1.9 Offset ErrorDefined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and theideal mid-scale output current.

8.3.1.10 Output Compliance RangeDefined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding thislimit may result reduced reliability of the device or adversely affecting distortion performance.

8.3.1.11 Reference Voltage DriftDefined as the maximum change of the reference voltage in ppm per degree Celsius from value at ambient(25°C) to values over the full operating temperature range.

8.3.1.12 Spurious Free Dynamic Range (SFDR)Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal.

8.3.1.13 Noise Spectral Density (NSD)Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal powerand the noise floor of 1Hz bandwidth within the first Nyquist zone.

8.4 Device Functional Modes

8.4.1 Serial InterfaceThe serial port of the DAC3283 is a flexible serial interface which communicates with industry standardmicroprocessors and microcontrollers. The interface provides read/write access to all registers used to define theoperating modes of DAC3283. It is compatible with most synchronous transfer formats and can be configured asa 3 or 4 pin interface by sif4_ena in register CONFIG23. In both configurations, SCLK is the serial interface inputclock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data inand data out. For 4 pin configuration, SDIO is bidirectional and ALARM_SDO is data out only. Data is input intothe device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.




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rwb N1 N0 - A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Instruction Cycle Data Transfer Cycle

tS(SDENB)

tS(SDIO) tH(SDIO)

tSCLK

tSCLKH tSCLKL

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO


Device Functional Modes (continued)Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle whichidentifies the following data transfer cycle as read or write, how many bytes to transfer, and what address totransfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detaileddescription of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 1. Instruction Byte of the Serial InterfaceMSB LSB

Bit 7 6 5 4 3 2 1 0Description R/W N1 N0 A4 A3 A2 A1 A0

R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a readoperation from DAC3283 and a low indicates a write operation to DAC3283.

[N1:N0] Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB first.

Table 2. Number of Transferred Bytes Within OneCommunication Frame

N1 N0 Description0 0 Transfer 1 Byte0 1 Transfer 2 Bytes1 0 Transfer 3 Bytes1 1 Transfer 4 Bytes

[A4:A0] Identifies the address of the register to be accessed during the read or write operation. For multi-byte transfers, this address is the starting address. Note that the address is written to theDAC3283 MSB first and counts down for each byte.

Figure 26 shows the serial interface timing diagram for a DAC3283 write operation. SCLK is the serial interfaceclock input to DAC3283. Serial data enable SDENB is an active low input to DAC3283. SDIO is serial data in.Input data to DAC3283 is clocked on the rising edges of SCLK.

Figure 26. Serial Interface Write Timing Diagram




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DATACLKP /N

(DDR)

FRAMEP/N

D[7:0]P/N

SAMPLE 0 SAMPLE 1

t(FRAME)

I0[15:8]

I0[7:0]

Q0

[15:8]

Q0

[7:0]

I1[15:8]

I1[7:0]

Q1

[15:8]

Q1

[7:0]

rwb N1 N0 - A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Instruction Cycle Data Transfer Cycle

td(Data)

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO or

ALARM_SDO

D7 D6 D5 D4 D3 D2 D1 D0ALARM_

SDO

Data n Data n-1

3-pin interface

4-pin interface


Figure 27 shows the serial interface timing diagram for a DAC3283 read operation. SCLK is the serial interfaceclock input to DAC3283. Serial data enable SDENB is an active low input to DAC3283. SDIO is serial data induring the instruction cycle. In 3 pin configuration, SDIO is data out from DAC3283 during the data transfercycle(s), while ALARM_SDO is in a high-impedance state. In 4 pin configuration, both ALARM_SDO and SDIOare data out from DAC3283 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO willoutput low on the final falling edge of SCLK until the rising edge of SDENB when it will 3-state.

Figure 27. Serial Interface Read Timing Diagram

8.4.2 Data InterfaceThe DAC3283 has a single 8-bit LVDS bus that accepts dual, 16-bit data input in byte-wide format. Data into theDAC3283 is formatted according to the diagram shown in Figure 28 where index 0 is the data LSB and index 15is the data MSB. The data is sampled by DATACLK, a double data rate (DDR) clock.

The FRAME signal is required to indicate the beginning of a frame. The frame signal can be either a pulse or aperiodic signal where the frame period corresponds to 8 samples. The pulse-width (t(FRAME)) needs to be at leastequal to ½ of the DATACLK period. FRAME is sampled by a rising edge in DATACLK.

The setup and hold requirements listed in the specifications tables must be met to ensure proper sampling.

Figure 28. Byte-Wide Data Transmission Format

8.4.3 Input FIFOThe DAC3283 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC datarate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 29 shows a simplified block diagram of the FIFO.




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Frame Align

0

1

2

3

4

5

6

7

FRAME

D[7:0]

0…

7

Wri

teP

oin

ter

FIFO I Output

FIFO Q Output

Clock Handoff

Input Side

Clocked by DATACLKOutput Side

Clocked by FIFO Out Clock

(DACCLK/Interpolation Factor)

FIFO:

2 x 16-bits wide

8-samples deep

0

1

2

3

4

5

6

7

Sample 0

I0 [15:0], Q0 [15:0]

Sample 2

I2 [15:0], Q2 [15:0]

Sample 3

I3 [15:0], Q3 [15:0]

Sample 4

I4 [15:0], Q4 [15:0]

Sample 5

I5 [15:0], Q5 [15:0]

Sample 6

I6 [15:0], Q6 [15:0]

Sample 7

I7 [15:0], Q7 [15:0]

Sample 1

I1 [15:0], Q1 [15:0]

Initial

Position0

…7

Re

ad

Poin

ter

Initial

Position

32-bit 32-bit

I-data, 16-bit

Q-data, 16-bit

16-bit

16-bit

Two DATACLK cycles to capture2x 16-bit of I-data and Q-data

Data[15:8] 8-bit

Data[7:0] 8-bit

Write Pointer Reset

OSTR

fifo_offset(2:0)

multi_sync_enaS M

Read Pointer Reset

fifo_reset_ena

0

S (Single Sync Source Mode). Reset handoff from input side to output side.M (Dual Sync Sources Mode). OSTR resets read pointer. Multi-DAC synchronization


Figure 29. DAC3283 FIFO Block Diagram

Data is written to the device 8-bits at a time on the rising and falling edges of DATACLK. In order to form acomplete 32-bit wide sample (16-bit I-data and 16-bit Q-data) two DATACLK periods are required as shown inFigure 30. Each 32-bit wide sample is written into the FIFO at the address indicated by the write pointer.Similarly, data from the FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by theread pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal toDACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the nextaddress.

The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown inFigure 29. This offset gives optimal margin within the FIFO. The default read pointer location can be set toanother value using fifo_offset(2:0) in register CONFIG3. Under normal conditions data is written-to and read-from the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the FIFOwrite and read rates are different, the corresponding pointers will be cycling at different speeds which could resultin pointer collision. Under this condition the FIFO attempts to read and write data from the same address at thesame time which will result in errors and thus must be avoided.

The FRAME signal besides acting as a frame indicator can also used to reset the FIFO pointers to their initiallocation. Unlike Data, the FRAME signal is latched only on the rising edges of DATACLK. When a rising edgeoccurs on FRAME, the pointers will return to their original position. The write pointer is always set back toposition 0 upon reset. The read pointer reset position is determined by fifo_offset (address 4 by default).

Similarly, the read pointer sync source is selected by multi_sync_sel (CONFIG19). Either the FRAME or OSTRsignal can be set to reset the read pointer. If FRAME is used to reset the read pointer, the FIFO Out Clock willrecapture the FRAME signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock)results in phase ambiguity of the reset signal. This limits the precise control of the output timing and makes fullsynchronization of multiple devices difficult.




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I4[15:8] I4[7:0] Q4[15:8] Q4[7:0]Q3[7:0] I5[7:0] Q5[15:8] Q5[7:0]I5[15:8] I6[7:0] Q6[15:8]I6[15:8] Q6[7:0] I7[15:8] I7[7:0] Q7[15:8]Q3[15:8]D[7:0]P/N

LV

DS

Pa

irs

(Data

So

urc

e) Write sample 4 to FIFO (32-bits)

DATACLKP /N

(DDR)

FRAMEP/NResets write pointer to position 0

Write I4[15:8] (8-bits) to

DAC on rising edge

Write I4[7:0] (8-bits) to

DAC on falling edge

Write Q4[15:8] (8-bits) to

DAC on rising edge

Write Q4[7:0] (8-bits) to

DAC on falling edgets(DATA)

th(DATA)

ts(DATA)

th(DATA)

ts(DATA)th(DATA)

DACCLKP/N

2 x interpolation

OSTRP/N

Resets read pointer to position

ts(OSTR) th(OSTR)

(optionally internalsync from write reset)

set by fifo_offset (4 by default)

LV

PE

CL

Pa

irs

(Clo

ck S

ou

rce

)


To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the writepointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timingrequirements in the specification table. In order to minimize the skew it is recommended to use the same clockdistribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all theDAC3283 devices in the system. Swapping the polarity of the DACCLK output with respect to the OSTR outputestablishes proper phase relationship.

The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointersautomatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it isnecessary to have FRAME and OSTR signals to repeat at multiple of 8 FIFO samples. To disable FIFO reset, setfifo_reset_ena and multi_sync_ena (CONFIG0) to 0.

The frequency limitation for the FRAME signal is the following:

fSYNC = fDATACLK/(n x 16) where n = 1, 2, ...

The frequency limitation for the OSTR signal is the following:

fOSTR = fDAC/(n x interpolation x 8) where n = 1, 2, ...

The frequencies above are at maximum when n = 1. This is when FRAME and OSTR have a rising edgetransition every 8 FIFO samples. The occurrence can be made less frequently by setting n > 1, for example,every n x 8 FIFO samples.

Figure 30. FIFO Write Description

8.4.4 FIFO AlarmsThe FIFO only operates correctly when the write and read pointers are positioned properly. If either pointer overor under runs the other, samples will be duplicated or skipped. To prevent this, register CONFIG7 can be used totrack three FIFO related alarms:• alarm_fifo_2away. Occurs when the pointers are within two addresses of each other.• alarm_fifo_1away. Occurs when the pointers are within one address of each other.• alarm_fifo_collision. Occurs when the pointers are equal to each other.

These three alarm events are generated asynchronously with respect to the clocks and can be accessed eitherthrough CONFIG7 or through the ALARM_SDO pin.




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8.4.5 FIFO Modes of OperationThe DAC3283 FIFO can be completely bypassed through registers config0 and config19. The registerconfiguration for each mode is described in Table 3.

Register Control Bitsconfig0 fifo_ena, fifo_reset_ena, multi_sync_enaconfig19 multi_sync_sel

Table 3. FIFO Operation ModesConfig1 FIFO Bits Config19

FIFO Mode fifo_ena fifo_reset_ena multi_sync_ena multi_sync_selDual Sync Sources 1 1 1 0Single Sync Source 1 1 1 1

Bypass 0 X X X

8.4.5.1 Dual Sync Souces ModeThis is the recommended mode of operation for those applications that require precise control of the outputtiming. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO writepointer is reset using the LVDS FRAME signal, and the FIFO read pointer is reset using the LVPECL OSTRsignal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or multiplechips. Multiple devices can be fully synchronized in this mode.

8.4.5.2 Single Sync Source ModeIn Single Sync Source mode, the FIFO write and read pointers are reset from the LVDS FRAME signal. Thismode has a possibility of up to 2 DAC clocks offset between the outputs of multiple devices (The DAC outputs ofthe same device maintain the same phase). Applications requiring exact output timing control will need DualSync Sources mode instead of Single Sync Source mode. A rising edge for FIFO and clock divider sync isrecommended. Periodic sync signal is not recommended due to non-deterministic latency of the sync signalthrough the clock domain transfer.

8.4.5.3 Bypass ModeIn FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK tothe DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK(t_align) is critical and used as a synchronizing mechanism for the internal logic. Due to the t_align constraint it ishighly recommended that a clock synchronizer device such as Texas Instruments’ CDCM7005 or CDCE62005 isused to provide both clock inputs. In bypass mode the pointers have no effect on the data path or handoff.

8.4.6 Multi-Device OperationIn various applications, such as multi antenna systems where the various transmit channels information iscorrelated, it is required that multiple DAC devices are completely synchronized such that their outputs arephase aligned. The DAC3283 architecture supports this mode of operation.

8.4.6.1 Multi-Device Synchronization: Dual Sync Sources ModeFor single or multi-device synchronization it is important that delay differences in the data are absorbed by thedevice so that latency through the device remains the same. Furthermore, to guarantee that the outputs fromeach DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. Inthe DAC3283 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this modethe additional OSTR signal is required by each DAC3283 to be synchronized.

Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into themultiple DAC devices can experience different delays due to variations in the digital source output paths or boardlevel wiring. These different delays can be effectively absorbed by the DAC3283 FIFO so that all outputs arephase aligned correctly.




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DACCLKP/N(2)

OSTRP/N(2)

LV

PE

CL

Pa

irs

(DA

C3

28

2/3

2)

ts(OSTR)

th(OSTR)

DACCLKP/N(1)

OSTRP/N(1)

LV

PE

CL

Pa

irs

(DA

C3

28

2/3

1)

ts(OSTR)

th(OSTR)

tSKEW ~ 0

Clock Generator

DATACLKP/N

FRAMEP/N

FPGAD[7:0]P/N

DATACLKP/N

FRAMEP/N

D[7:0]P/N

DACCLKP/N

LV

DS

Inte

rfa

ce

LVPECL Outputs

OSTRP/N

LVPECL Outputs

DACCLKP/N

OSTRP/N

PLL/DLL

DAC3282/3 DAC1

DAC3282/3 DAC2

delay 1

delay 2

Variable delays due to variations in theFPGA(s) output paths or board level wiringor temperature/voltage deltas

Outputs are

phase aligned


Figure 31. Synchronization System in Dual Sync Sources Mode

For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTRsignal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clockgenerator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity ofthe DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of theDACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.

Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed fromdevice to device with the lowest skew possible as this will affect the synchronization process. In order tominimize the skew across devices it is recommended to use the same clock distribution device to provide theDACCLK and OSTR signals to all the DAC devices in the system.

Figure 32. Timing Diagram for LVPECL Synchronization Signals

The following steps are required to ensure the devices are fully synchronized. The procedure assumes all theDAC3283 devices have a DACCLK and OSTR signal and the following steps must be carried out on eachdevice.• Start-up the device as described in the power-up sequence. Set the DAC3283 in Dual Sync Sources mode

and select OSTR as the FIFO output pointer sync source and clock divider sync source (multi_sync_sel inregister config19).

• Sync the clock divider and FIFO pointers.




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Clock Generator

DATACLKP/N

FRAMEP/N

FPGAD[7:0]P/N

DATACLKP/N

FRAMEP/N

D[7:0]P/N

DACCLKP/N

LV

DS

Inte

rfa

ce

LVPECL Output

LVPECL Output

DACCLKP/N

PLL/DLL

DAC3282/3 DAC1

DAC3282/3 DAC2

delay 1

delay 2

Variable delays due to variations in theFPGA(s) output paths or board level wiringor temperature/voltage deltas

0 to 2

DAC Clock cycles


• Verify there are no FIFO alarms either through register config7 or through the ALARM_SDO pin.

After these steps all the DAC3283 outputs will be synchronized.

8.4.6.2 Multi-Device Operation: Single Sync Source ModeIn Single Sync Source mode, the FIFO write and read pointers are reset from the same FRAME source.Although the FIFO in this mode can still absorb the data delay differences due to variations in the digital sourceoutput paths or board level wiring, it is impossible to guarantee data will be read from the FIFO of differentdevices simultaneously thus preventing exact phase alignment.

The FIFO read pointer reset is handoff between the two clock domains (DATACLK and FIFO OUT CLOCK) bysimply re-sampling the write pointer reset. Since the two clocks are asynchronous there is a small but distinctpossibility of a meta-stablility during the pointer handoff. This meta-stability can cause the outputs of the multipledevices to slip by up to 2 DAC clock cycles.

Figure 33. Multi-Device Operation in Single Sync Source Mode

8.4.7 Data Pattern CheckerThe DAC3283 incorporates a simple pattern checker test in order to determine errors in the data interface. Themain cause of failures is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in registerconfig1. In test mode the analog outputs are deactivated regardless of the state of TXENABLE.

The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] inregisters config9 through config16. The data pattern key can be modified by changing the contents of theseregisters.

The first word in the test frame is determined by a rising edge transition in FRAME. At this transition, the pattern0word should be input to the data pins. Patterns 1 through 7 should follow sequentially on each edge of DATACLK(rising and falling). The sequence should be repeated until the pattern checker test is disabled by settingiotest_ena back to “0”. It is not necessary to have a rising FRAME edge aligned with every pattern0 word, justthe first one to mark the beginning of the series.




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Pattern

0 ... 7

D[7:0]

8-Bit

8-Bit

8-Bit

DATACLK

iotest_results[7]

iotest_results[0]

alarm_from_iotestOnly oneedge needed

FRAMELVDS

Drivers

Go back to 0 after cycle or newrising edge on FRAME

Pattern 0Bit-by-Bit Compare








0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8-BitInput

8-BitInput

8-BitInput

Bit 7Results

Bit 0Results

•••

•••

•••

All BitsResults

iotest_pattern0

iotest_pattern1

iotest_pattern2

iotest_pattern3

iotest_pattern4

iotest_pattern5

iotest_pattern6

iotest_pattern7

DataFormat

D[7:0]P/N

FRAMEP/N

DATACLKP/N (DDR)

Pattern 0[7:0]

Pattern 1[7:0]

Pattern 2[7:0]

Pattern 3[7:0]

Pattern 4[7:0]

Pattern 5[7:0]

Pattern 6[7:0]

Pattern 7[7:0]

Start cycle again with optional rising edge of FRAME


Figure 34. IO Pattern Checker Data Transmission Format

The test mode determines if the 8-bit LVDS data D[7:0]P/N of all the patterns were received correctly bycomparing the received data against the data pattern key. If any of the 8-bit data D[7:0]P/N were receivedincorrectly, the corresponding bits in iotest_results(7:0) in register config8 will be set to “1” to indicate bit errorlocation. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config7 to indicate ageneral error in the data interface. When data pattern checker mode is enabled, this alarm in register config7, bit3 is the only valid alarm. Other alarms in register config7 are not valid and can be disregarded.

For instance, pattern0 is programmed to the default of 0x7A. If the received Pattern 0 is 0x7B, then bit 0 iniotest_results(7:0) will be set to “1” to indicate an error in bit 0 location. The alarm_from_iotest will also be set to“1” to report the data transfer error. The user can then narrow down the error from the bit location informationand implement the fix accordingly.

The alarms can be cleared by writing 0x00 to iotest_results(7:0) and "0" to alarm_from_iotest through the serialinterface. The serial interface will read back 0s if there are no errors or if the errors are cleared. Thecorresponding alarm bit will remain a "1" if the errors remain.

It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more completecycles before clearing the iotest_results(7:0) and alarm_from_iotest. This will eliminate the possibility of falsealarms generated during the setup sequence.

Figure 35. DAC3283 Pattern Check Block Diagram

8.4.8 DATACLK MonitorThe DAC3283 incorporates a clock monitor to determine if DATACLK is present. A missing DATACLK may resultin unexpected DAC outputs. As shown in Figure 36, the clock monitor circuit is a simple counter circuit. It is reseton each rising edge of DATACLK, and counts up with each rising edge of FIFOOUT_CLK. The output of thecounter has two latches: clk_alarm latch and tx_off latch. If the missing DATACLK is registered by the clockmonitor circuit after the counter reached the count of four, it will send a pulse to the two latches, which issue twoalarms, respectively.




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Q

QSET

CLR

DLogic HIGH

FIFOOUT_CLK

DATACLK

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

clk_alarm

tx_off


Figure 36. DATACLK Monitor Circuit

CIRCUIT FUNCTIONS REGISTER LOCATION STATE DESCRIPTIONmasks the alarm signal to the CMOS1 ALARM_SDO

clk_alarm_mask CONFIG17, bit4 read/writeunmasks the alarm signal to the CMOS0 ALARM_SDOclears the latch and enables the clock lossclk_alarm latch 1 monitoringclk_alarm_ena CONFIG17, bit1 read/write

0 holds the latch at reset at all times1 indicates clock loss event

clk_alarm VERSION31, bit7 read-only0 indicates normal operation

masks the alarm signal to the CMOS1 ALARM_SDOtx_off_mask CONFIG17, bit3 read/write

unmasks the alarm signal to the CMOS0 ALARM_SDOclears the latch and enables the clock losstx_off latch 1 monitoringtx_off_ena CONFIG17, bit0 read/write

0 holds the latch at reset at all times1 indicates output disabled event

tx_off VERSION31, bit6 read-only0 indicates normal operation

The purpose of the clk_alarm latch is to register the loss of DATACLK event. Upon the event, the latch will issuea read-only clk_alarm alarm. This latch can be held reset at all time by setting clk_alarm_ena = ‘0’ at all time.

The purpose of the tx_off latch is to disable the output when the DATACLK is lost. Upon the event, the latch willissue a read-only tx_off alarm. When this alarm is set, the DAC3283 outputs are automatically disabled by settingoutput data to mid-scale. This latch can be held reset at all time by setting tx_off_ena = ‘0’ at all time.

Both alarms are set by default to trigger the ALARM_SDO pin in 3-pin SPI mode. By writing clk_alarm_mask andtx_off_mask to ‘1’, the ALARM_SDO will ignore these two alarms. This may be useful if the ALARM_SDO isneeded to report other critical alarms in the interrupt routine.

These two latches can be held reset at all times, effectively ignoring any clock monitor output, by settingclk_alarm_ena and tx_off_ena to ‘0”. When a ‘0’ is written to either of these two register bits, it will force the latchoutput low. For the latches to report an error, the clk_monitor_ena and tx_off_ena must be written to a ‘0’ andthen a ‘1’.




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The clock monitoring function is implemented as follows:1. Power up the device using the recommended power-up sequence.

(a) Configure the device using the SPI bus.(b) Provide both the DATACLK and DACCLK.

2. Reset the clock monitor circuit and the latches by writing clk_alarm_ena and tx_off_ena a ‘0”, and then ‘1’ inCONFIG17.

3. Unmask the alarms by setting clk_alarm_mask and tx_off_mask to ‘0’ in CONFIG17.

If the DATACLK is interrupted, the ALARM_SDO pin will transition to indicate error. The interrupt service routinecan check the following:1. Read clk_alarm and tx_off in CONFIG31 and other alarms in CONFIG7 to determine the error that triggered

the alarm.2. If clk_alarm and tx_off alarms are set in CONFIG31, then DATACLK was interrupted and the DAC outputs

should be set to mid-scale.3. Implement system check to recover the DATACLK.4. Reset the clock monitor circuit and clk_alarm latch by writing clk_alarm_ena a ‘0”, and then ‘1’ in CONFIG17.5. Read clk_alarm in CONFIG31 to verify if the clock loss event has not re-triggered the alarm.6. Once the clock monitor indicates the DATACLK is stable, resynchronize the FIFO. See Power-Up Sequence

section for detail.7. Reset the transmit disable latch by writing tx_off_ena a ‘0”, and then ‘1’ in CONFIG17. This will re-enable the

DAC to output actual data.

NOTEThe ALARM_SDO pin in 4-pin SPI mode functions as SPI register data output. Thesystem will need to poll VERSION31 alarms frequently in order to detect the DATACLKinterruption errors.




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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

f/fDATA

-160

-140

-120

-100

-80

-60

-40

-20

0

20

Ma

gn

itu

de

- d

B

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1f/fDATA

-160

-140

-120

-100

-80

-60

-40

-20

0

20

Ma

gn

itu

de

- d

B

-160

-140

-120

-100

-80

-60

-40

-20

0

20

Ma

gn

itu

de

- d

B

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

f/fIN

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

f/fIN

-160

-140

-120

-100

-80

-60

-40

-20

0

20

Ma

gn

itu

de

- d

B


8.4.9 FIR FiltersFigure 37 and Figure 38 show the magnitude spectrum response for the FIR0 and FIR1 interpolating half-bandfilters where fIN is the input data rate to the FIR filter. Figure 39 and Figure 40 show the composite filter responsefor 2x and 4x interpolation. The transition band for all the interpolation settings is from 0.4 to 0.6 x fDATA (the inputdata rate to the device) with < 0.002dB of pass-band ripple and > 85dB stop-band attenuation.

The filter taps for all digital filters are listed in Table 4.

Figure 37. Magnitude Spectrum for FIR0 Figure 38. Magnitude Spectrum for FIR1

Figure 40. 4x Interpolation Composite ResponseFigure 39. 2x Interpolation Composite Response




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Table 4. FIR Filter CoefficientsFIR0 FIR1

2x Interpolating Half-band 2x InterpolatingFilter Half-Band Filter

59 Taps 23 Taps4 4 –20 0 0

–12 –12 170 0 028 28 –750 0 0

–58 –58 2380 0 0

108 108 –6600 0 0

–188 –188 25300 0 4096 (1)

308 308 25300 0 0

–483 –483 –6600 0 0

734 734 2380 0 0

–1091 –1091 –750 0 0

1607 1607 170 0 0

–2392 –2392 –20 0

3732 37320 0

–6681 –66810 0

20768 2076832768 (1)

(1) Center taps are highlighted in BOLD.

8.4.10 Coarse MixerThe DAC3283 has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixingfrequencies fS/2 or fS/4. The coarse mixing function is built into the interpolation filters and thus FIR0 (2xinterpolation) or FIR0 and FIR1 (4x interpolation) must be enabled to use it.

Treating channels A and B as a complex vector of the form I(t) + j Q(t), where I(t) = A(t) and Q(t) = B(t), theoutputs of the coarse mixer, AOUT(t) and BOUT(t) are equivalent to:

AOUT(t) = A(t)cos(2πfCMIXt) – B(t)sin(2πfCMIXt)BOUT(t) = A(t)sin(2πfCMIXt) + B(t)cos(2πfCMIXt)

where fCMIX is the fixed mixing frequency selected by mixer_func(1:0). For fS/2, +fS/4 and –fS/4 the aboveoperations result in the simple mixing sequences shown in Table 5.




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x2

x2

FIR

(x2 Bypass)

Co

ars

eM

ixe

rA Data In

B Data In

A Data Out

B Data Out

Block Diagram

0

1

0 1

1 -1

0

1

0 1

1 -1

Mix Sequencermixer_func(1:0)

A Mix In

B Mix In

A Mix Out

B Mix Out


Table 5. Coarse Mixer SequencesMode mixer_func(1:0) Mixing SequenceNormal (Low Pass, No Mixing) 00 AOUT = +A, +A , +A, +A

BOUT = +B, +B , +B, +B fS/2 01 AOUT = +A, –A , +A, –A

BOUT = +B, -B , +B, -B +fS/4 10 AOUT = +A, -B , –A, +B

BOUT = +B, +A , –B, –A –fS/4 11 AOUT = +A, +B , –A, –B

BOUT = +B, –A , –B, +A

Figure 41. Coarse Mixers Block Diagram

The coarse mixer in the DAC3283 treats the A and B inputs as complex input data and for most mixingfrequencies produces a complex output. Only when the mixing frequency is set to fS/2 the A and B channels canbe maintained isolated as shown in Table 5. In this case, the two channels are upconverted as independentsignals. By setting the mixer to fS/2 the interpolation filter outputs are inverted thus behaving as a high-pass filter.

Table 6. Dual-Channel Real Upconversion OptionsFIR MODE INPUT FREQUENCY (1) OUTPUT FREQUENCY (1) SIGNAL BANDWIDTH (1) SPECTRUM INVERTED?Low Pass 0.0 to 0.4 × fDATA 0.0 to 0.4 × fDATA 0.4 × fDATA NoHigh Pass 0.0 to 0.4 × fDATA 0.6 to 1.0 × fDATA 0.4 × fDATA Yes

(1) fDATA is the input data rate of each channel after de-interleaving.




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x

11

qmc_gaina (10:0)

A Data In S

11

qmc_gainb (10:0)

B Data In

A Data Out

B Data Out

16

16

16

16

x

x qmc_phase (9:0)10


8.4.11 Quadrature Modulation Correction (QMC)The Quadrature Modulator Correction (QMC) block provides a means for adjusting the gain and phase of thecomplex signal. At a quadrature modulator output, gain and phase imbalances result in an undesired sidebandsignal.

The block diagram for the QMC is shown in Figure 42. The QMC block contains 3 programmable parameters:qmc_gaina(10:0), qmc_gainb(10:0) and qmc_phase(9:0).

Registers qmc_gaina(10:0) and qmc_gainb(10:0) control the I and Q path gains and are 11 bit values with arange of 0 to approximately 2. This value is used to scale the signal range. Register qmc_phase(9:0) controls thephase imbalance between I and Q and is a 10-bit value that ranges from –1/8 to approximately +1/8. This valueis multiplied by each Q sample then summed into the I sample path. This operation is a simplified approximationof a true phase rotation and covers the range from –7.125 to +7.125 degrees in 1024 steps.

A write to register CONFIG27 is required to load the gain and phase values (CONFIG27-CONFIG30) into theQMC block simultaneously. When updating the gain and/or phase values CONFIG27 should be written last.Programming any of the other three registers will not affect the gain and phase settings.

Figure 42. QMC Block Diagram

8.4.12 Digital Offset ControlThe qmc_offseta(12:0) and qmc_offsetb(12:0) values in registers CONFIG20 through CONFIG23 can be used toindependently adjust the A and B path DC offsets. Both offset values are in represented in 2s-complement formatwith a range from –4096 to 4095.

Note that a write to register CONFIG20 is required to load the values of all four qmc_offset registers (CONFIG20-CONFIG23) into the offset block simultaneously. When updating the offset values CONFIG20 should be writtenlast. Programming any of the other three registers will not affect the offset setting.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset isadded directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offsetvalues are LSB aligned.




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S

13

qma_offset

-4096, -4095, … , 4095

A Data In

S

13qmb_offset

-4096, -4095, … , 4095

B Data In

A Data Out

B Data Out

16

16

16

16


Figure 43. Digital Offset Block Diagram

8.4.13 Temperature SensorThe DAC3283 incorporates a temperature sensor block which monitors the temperature by measuring thevoltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complementvalue representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled(tsense_ena = 1 in register CONFIG24) a conversion takes place each time the serial port is written or read. Thedata is only read and sent out by the digital block when the temperature sensor is read in register CONFIG5. Theconversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid onthe falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No otherclocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor isenabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from CONFIG5 must be donewith an SCLK period of at least 1µs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

8.4.14 Sleep ModesThe DAC3283 features independent sleep control of each DAC (sleepa and sleepb), their corresponding clockpath (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). Thesleep control of each of these components is done through the SIF interface and is enabled by setting a 1 to thecorresponding sleep register.

Complete power down of the device is set by setting all of these components to sleep. Under this mode thesupply power consumption is reduced to 15mW. Power-up time in this case will be in the milliseconds range.Alternatively for those applications were power-up and power-down times are critical it is recommended to onlyset the DACs to sleep through the sleepa and sleepb registers. In this case both the sleep and wake-up timesare only 90µs.

8.4.15 LVPECL InputsFigure 44 shows an equivalent circuit for the DAC input clock (DACCLP/N) and the output strobe clock(OSTRP/N).




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D[7:0]P,

DATACLKP ,

FRAMEP

50

D[7:0]N,

DATACLKN ,

FRAMEN

50

LVDS

Receiver

100 pF

Total

To Adjacent

LVDS Input

To Adjacent

LVDS Input

Ref Note (1)

Note (1): RCENTER node common

to the D[7:0]P/N, DATACLKP /N and

FRAMEP/N receiver inputs

0.1 mF

CLKIN

CLKINC

0.1 mF

CAC

Differential

ECL

or

(LV)PECL

source

+

-

RT150 W150 W

100 W

DACCLKP

OSTRP

DACCLKN

OSTRN

GND

500 W

2 kW

CLKVDD

Note: Input common mode level is

approximately 1/2*CLKVDD18,

or 0.9V nominal.

2 kW

500 W


Figure 44. DACCLKP/N and OSTRP/N Equivalent Input Circuit

Figure 45 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differentialECL/PECL source.

Figure 45. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source

8.4.16 LVDS INPUTSThe D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 46.Figure 47 shows the typical input levels and common-move voltage used to drive these inputs.

Figure 46. D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS Input Configuration




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SDIO

SCLK

TXENABLE

internal

digital in

DIGVDD18

GND

SDENBinternal

digital in

DIGVDD18

GND

D[7:0]P,

DATACLKP ,

FRAMEP

100 LVDS

Receiver

DAC3283

D[7:0]N,

DATACLKN ,

FRAMENGND

VCOM =

(VA+VB)/2VB

VA,B

VA

VA

VB

VA,B

Logical Bit

Equivalent

1.40 V

1.00 V

400 mV

0 V

-400 mV

1

0

Example


Figure 47. LVDS Data (D[7:0]P/N, DATACLKP/N, FRAMEP/N Pairs) Input Levels

Table 7. Example LVDS Data Input LevelsRESULTING RESULTING COMMON-APPLIED VOLTAGES DEFERENTIAL LOGICAL BIT BINARYMODE VOLTAGEVOLTAGE EQUIVALENT

VA VB VA,B VCOM

1.4 V 1.0 V 400 mV 1.2 V 11.0 V 1.4 V –400 mV 01.2 V 0.8 V 400 mV 1.0 V 10.8 V 1.2 V –400 mV 0

8.4.17 CMOS Digital InputsFigure 48 shows a schematic of the equivalent CMOS digital inputs of the DAC3283. SDIO, SCLK andTXENABLE have pull-down resistors while SDENB has a pull-up resistors internal to the DAC3283. See thespecification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.

Figure 48. CMOS/TTL Digital Equivalent Input

8.4.18 Reference OperationThe DAC3283 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS throughresistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scaleoutput current equals 16 times this bias current and can thus be expressed as:

IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS

Each DAC has a 4-bit coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the CONFIG4register. Using gain control, the IOUTFS can be expressed as::

IOUTAFS = (DACA_gain + 1) × IBIAS = (DACA_gain + 1) × VEXTIO / RBIASIOUTBFS = (DACB_gain + 1) x IBIAS = (DACB_gain + 1) x VEXTIO / RBIAS




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where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of1.2V. This reference is active when extref_ena = '0' in CONFIG25. An external decoupling capacitor CEXT of0.1µF should be connected externally to terminal EXTIO for compensation. The bandgap reference canadditionally be used for external reference operation. In that case, an external buffer with high impedance inputshould be applied in order to limit the bandgap load current to a maximum of 100nA. The internal reference canbe disabled and overridden by an external reference by setting the CONFIG25 extref_ena control bit. CapacitorCEXT may hence be omitted. Terminal EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 20mA down to 2mA by varying resistor RBIAS or changing theexternally applied reference voltage. The internal control amplifier has a wide input range, supporting the full-scale output current range of 20dB.

8.4.19 DAC Transfer FunctionThe CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale outputcurrent up to 20mA. Differential current switches direct the current to either one of the complementary outputnodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary outputcurrents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by afactor of two.

The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltagereference source (+1.2V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally toprovide a maximum full-scale output current equal to 16 times IBIAS.

The relation between IOUT1 and IOUT2 can be expressed as:IOUT1 = – IOUTFS – IOUT2

Current flowing into a node is denoted as – current and current flowing out of a node as + current. Since theoutput stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The outputcurrent flow in each pin driving a resistive load can be expressed as:

IOUT1 = IOUTFS × (65535 – CODE) / 65536IOUT2 = IOUTFS × CODE / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltagesat IOUT1 and IOUT2:

VOUT1 = AVDD – | IOUT1 | × RLVOUT2 = AVDD – | IOUT2 | × RL

Assuming that the data is full scale (65536 in offset binary notation) and the RL is 25 Ω, the differential voltagebetween pins IOUT1 and IOUT2 can be expressed as:

VOUT1 = AVDD – | –0 mA | × 25 Ω = 3.3 VVOUT2 = AVDD – | –20 mA | × 25 Ω = 2.8 VVDIFF = VOUT1 – VOUT2 = 0.5 V

Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which wouldlead to increased signal distortion.

8.4.20 Analog Current OutputsFigure 49 shows a simplified schematic of the current source array output with corresponding switches.Differential switches direct the current of each individual NMOS current source to either the positive output nodeIOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack ofthe current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5pF.




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IOUT1

1 : 1

IOUT2

50 W

RLOAD100 W

50 W

50 W

AVDD (3.3 V)

AVDD (3.3 V)

RLOADRLOAD

AVDD

S(1)

S(1)C

S(2)

S(2)C

S(N)

S(N)C...

IOUT1 IOUT2


The external output resistors are referenced to an external ground. The minimum output compliance at nodesIOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistorbreakdown may occur resulting in reduced reliability of the DAC3283 device. The maximum output compliancevoltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltageadversely affects distortion performance and integral non-linearity. The optimum distortion performance for asingle-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does notexceed 0.5 V.

Figure 49. Equivalent Analog Current Output

The DAC3283 can be easily configured to drive a doubly terminated 50Ω cable using a properly selected RFtransformer. Figure 50 and Figure 51 show the 50Ω doubly terminated transformer configuration with 1:1 and 4:1impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to beconnected to AVDD to enable a dc current flow. Applying a 20 mA full-scale output current would lead to a 0.5VPP for a 1:1 transformer, and a 1 VPP output for a 4:1 transformer. The low dc-impedance between IOUT1 orIOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 VPP output for the 4:1transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V.

Figure 50. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer




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IOUTA1

IOUTA2

IOUTB1

IOUTB2

S

RF

Sig

na

lC

on

dit

ion

ing

Quadrature modulator

Vout ~ 2.8 to 3.8 V Vin ~ Varies

I1

I2

Q1

Q2

IOUT1

4 :1

50 W

RLOAD

100 W

100 W

IOUT2

AVDD (3.3 V)

AVDD (3.3 V)


Figure 51. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer

8.4.21 Passive Interface to Analog Quadrature ModulatorsA common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703family of modulators from Texas Instruments. The input of the modulator is generally of high impedance andrequires a specific common-mode voltage. A simple resistive network can be used to maintain 50Ω loadimpedance for the DAC3283 and also provide the necessary common-mode voltages for both the DAC and themodulator.

Figure 52. DAC to Analog Quadrature Modulator Interface

The DAC3283 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. TheTRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.

Figure 53 shows the recommended passive network to interface the DAC3283 to the TRF3703-17 which has acommon mode voltage of 1.7V. The network generates the 3.3V common mode required by the DAC output and1.7V at the modulator input, while still maintaining 50Ω load for the DAC.




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I

/I

TRF3703-33

I

/I

V1

V1

R1

R1

R3

R3

V2DAC3283

I

/I

TRF3703-17

I

/I

V1

V1

R1

R1

R2

R2R3

R3

V2DAC3283


Figure 53. DAC3283 to TRF3703-17 Interface

If V1 is set to 5V and V2 is set to -5V, the corresponding resistor values are R1 = 57Ω, R2 = 80Ω, andR3 = 336Ω. The loss developed through R2 is about –1.86 dB. In the case where there is no –5V supplyavailable and V2 is set to 0V, the resistor values are R1 = 66Ω, R2 = 101Ω, and R3 = 107Ω. The loss with thesevalues is –5.76dB.

Figure 54 shows the recommended network for interfacing with the TRF3703-33 which requires a common modeof 3.3V. This is the simplest interface as there is no voltage shift. Because there is no voltage shift there is anyloss in the network. With V1 = 5V and V2 = 0V, the resistor values are R1 = 66Ω and R3 = 208Ω.

Figure 54. DAC3283 to TRF3703-33 Interface

In most applications, a baseband filter is required between the DAC and the modulator to eliminate the DACimages. This filter can be placed after the common-mode biasing network. For the DAC to modulator networkshown in Figure 55, R2 and the filter load R4 need to be considered into the DAC impedance. The filter has to bedesigned for the source impedance created by the resistor combination of R3 // (R2+R1). The effectiveimpedance seen by the DAC is affected by the filter termination resistor resulting in R1 // (R2+R3 // (R4/2)).




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DAC3283

I

/I

TRF3703

V1

R1

R1

R3

R3

Filter R4

V1

R2

R2

V2


Figure 55. DAC3283 to Modulator Interface with Filter

Factoring in R4 into the DAC load, a typical interface to the TRF3703-17 with V1 = 5V and V2 = 0V results in thefollowing values: R1 = 72Ω, R2 = 116Ω, R3 = 124Ω and R4 = 150Ω. This implies that the filter needs to bedesigned for 75Ω input and output impedance (single-ended impedance). The common mode levels for the DACand modulator are maintained at 3.3V and 1.7V and the DAC load is 50Ω. The added load of the filtertermination causes the signal to be attenuated by –10.8 dB.

A filter can be implemented in a similar manner to interface with the TRF3703-33. In this case it is much simplerto balance the loads and common mode voltages due to the absence of R2. An added benefit is that there is noloss in this network. With V1 = 5V and V2 = 0V the network can be designed such that R1 = 115Ω, R3 = 681Ω,and R4 = 200Ω. This results in a filter impedance of R1 // R2=100Ω, and a DAC load of R1 // R3 // (R4/2) whichis equal to 50Ω. R4 is a differential resistor and does not affect the common mode level created by R1 and R3.The common-mode voltage is set at 3.3 V for a full-scale current of 20mA.

For more information on how to interface the DAC3283 to an analog quadrature modulator please refer to theapplication reports Passive Terminations for Current Output DACs (SLAA399) and Design of Differential Filtersfor High-Speed Signal Chains (SLWA053).




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8.5 Register Maps

Table 8. Register Map(MSB) (LSB)Name Address Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1Bit 7 Bit 0

CONFIG0 0x00 0x70 reserved fifo_ena fifo_reset_ena multi_sync_ena alarm_out_ena alarm_pol mixer_func(1:0)

CONFIG1 0x01 0x11 qmc_offset_ena qmc_correct_ena fir0_ena fir1_ena unused iotest_ena unused twos

CONFIG2 0x02 0x00 unused unused sif_sync sif_sync_ena unused unused output_delay(1:0)

alarm_CONFIG3 0x03 0x10 64cnt_ena unused unused fifo_offset(2:0) alarm_ 1away_ena2away_ena

CONFIG4 0x04 0xFF coarse_daca(3:0) coarse_dacb(3:0)

CONFIG5 0x05 N/A tempdata(7:0)

CONFIG6 0x06 0x00 unused alarm_mask(6:0)

alarm_from_ alarm_fifo_ alarm_from_ alarm_fifo_CONFIG7 0x07 0x00 unused reserved unused alarm_fifo_ 1awayzerochk collision iotest 2away

CONFIG8 0x08 0x00 iotest_results(7:0)

CONFIG9 0x09 0x7A iotest_pattern0(7:0)

CONFIG10 0x0A 0xB6 iotest_pattern1(7:0)

CONFIG11 0x0B 0xEA iotest_pattern2(7:0)

CONFIG12 0x0C 0x45 iotest_pattern3(7:0)

CONFIG13 0x0D 0x1A iotest_pattern4(7:0)

CONFIG14 0x0E 0x16 iotest_pattern5(7:0)

CONFIG15 0x0F 0xAA iotest_pattern6(7:0)

CONFIG16 0x10 0xC6 iotest_pattern7(7:0)

CONFIG17 0x11 0x24 reserved reserved reserved clk_alarm_mask tx_off_mask reserved clk_alarm_ena tx_off_ena

daca_ dacb_CONFIG18 0x12 0x02 reserved reserved clkdiv_sync_ena unusedcomplement complement

CONFIG19 0x13 0x00 bequalsa aequalsb reserved unused unused unused multi_sync_sel rev

CONFIG20 0x14 0x00 qmc_offseta(7:0)

CONFIG21 0x15 0x00 qmc_offsetb(7:0)

CONFIG22 0x16 0x00 qmc_offseta(12:8) unused unused unused

CONFIG23 0x17 0x00 qmc_offsetb(12:8) sif4_ena clkpath_sleep_a clkpath_sleep_b

CONFIG24 0x18 0x83 tsense_ena clkrecv_sleep unused reserved sleepb sleepa reserved reserved

CONFIG25 0x19 0x00 reserved extref_ena reserved reserved

CONFIG26 0x1A 0x00 reserved reserved unused reserved

CONFIG27 0x1B 0x00 qmc_gaina(7:0)

CONFIG28 0x1C 0x00 qmc_gainb(7:0)

CONFIG29 0x1D 0x00 qmc_phase(7:0)

CONFIG30 0x1E 0x24 qmc_phase(9:8) qmc_gaina(10:8) qmc_gainb(10:8)

CONFIG31 0x1F 0x12 clk_alarm tx_off version(5:0)




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8.5.1 CONFIG0 (address = 0x00) [reset = 0x70]

Figure 56. CONFIG0

7 6 5 4 3 2 1 0Reserved fifo_ena fifo_reset_ena multi_sync_ena alarm_out_ena alarm_pol mixer_func(1:0)

R/W R/W R/W R/W R/W R/W R/W R/WLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. CONFIG0 Field DescriptionsBit Field Type Reset Description7 Reserved R/W 0 Reserved for factory use.6 fifo_ena R/W 1 When asserted the FIFO is enabled. When the FIFO is bypassed

DACCCLKP/N and DATACLKP/N must be aligned to within t_align.5 fifo_reset_ena R/W 1 Allows the FRAME input to reset the FIFO write pointer when asserted4 multi_sync_ena R/W 1 Allows the FRAME or OSTR signal to reset the FIFO read pointer when

asserted. This selection is determined by multi_sync_sel in register CONFIG19.3 alarm_out_ena R/W 0 When asserted the ALARM_SDO pin becomes an output. The functionality of

this pin is controlled by the CONFIG6 alarm_mask setting.2 alarm_pol R/W 0 This bit changes the polarity of the ALARM signal. (0=negative logic, 1=positive

logic)1:0 mixer_func(1:0) R/W 00 Controls the function of the mixer block.

Mode mixer_func(1:0)Normal 00

High Pass (Fs/2) 01Fs/4 10–Fs/4 11


Figure 57. CONFIG1

7 6 5 4 3 2 1 0qmc_offset_ena qmc_correct_ena fir0_ena fir1_ena Unused iotest_ena Unused twos


Table 10. CONFIG1 Field DescriptionsBit Field Type Reset Description7 qmc_offset_ena R/W 0 When asserted the QMC offset correction circuitry is enabled.6 qmc_correct_ena R/W 0 When asserted the QMC phase and gain correction circuitry is enabled.5 fir0_ena R/W 0 When asserted FIR0 is activated enabling 2x interpolation.4 fir1_ena R/W 1 When asserted FIR1 is activated enabling 4x interpolation. fir0_ena must be

set to '1' for 4x interpolation.3 Unused R/W 0 Reserved for factory use.2 iotest_ena R/W 0 When asserted enables the data pattern checker operation.1 Unused R/W 0 Reserved for factory use.0 twos R/W 1 When asserted the inputs are expected to be in 2's complement format. When

de-asserted the input format is expected to be offset-binary.




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Figure 58. CONFIG2

7 6 5 4 3 2 1 0Unused Unused sif_sync sif_sync_ena Unused Unused out_delay


Table 11. CONFIG2 Field DescriptionsBit Field Type Reset Description7 Unused R/W 0 Reserved for factory use.6 Unused R/W 0 Reserved for factory use.5 sif_sync R/W 0 Serial interface created sync signal. Set to '1' to cause a sync and then

clear to '0' to remove it.4 sif_sync_ena R/W 0 When asserted this bit allows the SIF sync to be used. Normal FRAME

signals are ignored.3 Unused R/W 0 Reserved for factory use.2 Unused R/W 0 Reserved for factory use.

1:0 output_delay(1:0) R/W 00 Delays the output to the DACs from 0 to 3 DAC clock cycles.


Figure 59. CONFIG3

7 6 5 4 3 2 1 064cnt_ena Unused Unused fifo_offset(2:0) alarm_2away_ena alarm_1away_ena


Table 12. CONFIG3 Field DescriptionsBit Field Type Reset Description7 64cnt_ena R/W 0 This enables resetting the alarms after 64 good samples with the

goal of removing unnecessary errors. For instance, when checkingsetup/hold through the pattern checker test, there may initially beerrors. Setting this bit removes the need for a SIF write to clear thealarm register.

6 Unused R/W 0 Reserved for factory use.5 Unused R/W 0 Reserved for factory use.

4:2 fifo_offset(2:0) R/W 100 This is the default FIFO read pointer position after the FIFO readpointer has been synced. With this value the initial differencebetween write and read pointers can be controlled. This may behelpful in controlling the delay through the device.

1 alarm_2away_ena R/W 0 When asserted alarms from the FIFO that represent the write andread pointers being 2 away are enabled.

0 alarm_1away_ena R/W 0 When asserted alarms from the FIFO that represent the write andread pointers being 1 away are enabled.




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EXTIOV(coarse_daca/b + 1)

Rbias´


8.5.5 CONFIG4 (address = 0x04) [reset = 0xFF]

Figure 60. CONFIG4

7 6 5 4 3 2 1 0coarse_daca(3:0) coarse_dach(3:0)


Table 13. CONFIG4 Field DescriptionsBit Field Type Reset Description7:4 coarse_daca(3:0) R/W 1111 Scales the DACA output current in 16 equal steps.

3:0 coarse_dach(3:0) R/W 1111 Scales the DACB output current in 16 equal steps.

8.5.6 CONFIG5 (address = 0x05) READ ONLY

Figure 61. CONFIG5

7 6 5 4 3 2 1 0tempdata

R R R R R R R RLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. CONFIG5 Field DescriptionsBit Field Type Reset Description7:0 tempdata R N/A This is the output from the chip temperature sensor. The value

of this register in two’s complement format represents thetemperature in degrees Celsius. This register must be readwith a minimum SCLK period of 1µs. (Read Only)

8.5.7 CONFIG6 (address =0x06) [reset = 0x00]

Figure 62. CONFIG6

7 6 5 4 3 2 1 0Unused alarm_mask


Table 15. CONFIG6 Field DescriptionsBit Field Type Reset Description7 Unused R/W 0 Reserved for factory use.

6:0 alarm_mask R/W 0000000 These bits control the masking of the alarm outputs. Thismeans that the ALARM_SDO pin will not be asserted if theappropriate bit is set. The alarm will still show up in theCONFIG7 bits. (0=not masked, 1= masked).

alarm_mask Masked Alarm6 alarm_from_zerochk5 alarm_fifo_collision4 reserved3 alarm_from_iotest2 not used (expansion)1 alarm_fifo_2away0 alarm_fifo_1away




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8.5.8 CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)

Figure 63. CONFIG7

7 6 5 4 3 2 1 0alarm_from_ alarm_fifo_ alarm_from_ alarm_fifo_ alarm_fifo_Unused Reserved Unusedzerochk collision iotest 2away 1away

W W W W W W W WLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. CONFIG7 Field DescriptionsBit Field Type Reset Description7 Unused W 0 Reserved for factory use.6 alarm_from_zerochk W 0 This alarm indicates the 8-bit FIFO write pointer address has an all

zeros patterns. Due to pointer address being a shift register, this isnot a valid address and will cause the write pointer to be stuck untilthe next sync. This error is typically caused by timing error orimproper power start-up sequence. If this alarm is asserted,resynchronization of FIFO is necessary. Refer to the Power-UpSequence section for more detail.

5 alarm_fifo_collision W 0 Alarm occurs when the FIFO pointers over/under run each other.4 Reserved W 0 Reserved for factory use.3 alarm_from_iotest W 0 This is asserted when the input data pattern does not match the

pattern in the iotest_pattern registers.2 Unused W 0 Reserved for factory use.1 alarm_fifo_2away W 0 Alarm occurs with the read and write pointers of the FIFO are within

2 addresses of each other.0 alarm_fifo_1away W 0 Alarm occurs with the read and write pointers of the FIFO are within

1 address of each other.

8.5.9 CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)

Figure 64. CONFIG8

7 6 5 4 3 2 1 0iotest_results


Table 17. CONFIG8 Field DescriptionsBit Field Type Reset Description7:0 iotest_results R/W 0x00 The values of these bits tell which bit in the byte-wide LVDS bus

failed during the pattern checker test.

8.5.10 CONFIG9 (address = 0x09) [reset = 0x7A]

Figure 65. CONFIG9

7 6 5 4 3 2 1 0iotest_pattern0


Table 18. CONFIG9 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern0 R/W 0x7A This is dataword0 in the IO test pattern. It is used with the seven

other words to test the input data.




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8.5.11 CONFIG10 (address = 0x0A) [reset = 0xB6]

Figure 66. CONFIG10



Table 19. CONFIG10 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern1 R/W 0xB6 This is dataword1 in the IO test pattern. It is used with the seven


8.5.12 CONFIG11 (address = 0x0B) [reset = 0xEA]

Figure 67. CONFIG11



Table 20. CONFIG11 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern2 R/W 0xB6 This is dataword2 in the IO test pattern. It is used with the seven


8.5.13 CONFIG12 (address =0x0C) [reset = 0x45]

Figure 68. CONFIG12



Table 21. CONFIG12 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern3 R/W 0x45 This is dataword3 in the IO test pattern. It is used with the seven


8.5.14 CONFIG13 (address =0x0D) [reset = 0x1A]

Figure 69. CONFIG13



Table 22. CONFIG13 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern4 R/W 0x1A This is dataword4 in the IO test pattern. It is used with the seven





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8.5.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]

Figure 70. CONFIG14



Table 23. CONFIG14 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern5 R/W 0x16 This is dataword5 in the IO test pattern. It is used with the seven


8.5.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]

Figure 71. CONFIG15



Table 24. CONFIG15 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern6 R/W 0xAA This is dataword6 in the IO test pattern. It is used with the seven


8.5.17 CONFIG16 (address = 0x10) [reset = 0xV6]

Figure 72. CONFIG16



Table 25. CONFIG16 Field DescriptionsBit Field Type Reset Description7:0 iotest_pattern7 R/W 0xC6 This is dataword7 in the IO test pattern. It is used with the seven





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Figure 73. CONFIG17

7 6 5 4 3 2 1 0Reserved Reserved Reserved clk_alarm_mask tx_off_mask Reserved clk_alarm_ena tx_off_ena


Table 26. CONFIG17 Field DescriptionsBit Field Type Reset Description7 Reserved R/W 0 Reserved for factory use.6 Reserved R/W 0 Reserved for factory use.5 Reserved R/W 1 Reserved for factory use.4 clk_alarm_mask R/W 0 This bit controls the masking of the clock monitor alarm. This

means that the ALARM_SDO pin will not be asserted. The alarmwill still show up in the clk_alarm bit. (0=not masked, 1=masked).

3 tx_off_mask R/W 0 This bit control the masking of the transmit enable alarm. Thismeans that the ALARM_SDO pin will not be asserted. The alarmwill still show up in the tx_off bit. (0=not masked, 1= masked).

2 Reserved R/W 1 Reserved for factory use.1 clk_alarm_ena R/W 0 When asserted the DATACLK monitor alarm is enabled.0 tx_off_ena R/W 0 When asserted a clk_alarm event will automatically disable the

DAC outputs by setting them to midscale.


Figure 74. CONFIG18

7 6 5 4 3 2 1 0Reserved daca_complement dacb_complement clkdiv_sync_ena Unused


Table 27. CONFIG18 Field DescriptionsBit Field Type Reset Description7:4 Reserved R/W 0000 Reserved for factory use.3 daca_complement R/W 0 When asserted the output to the DACA is complemented. This

allows to effectively change the + and – designations of theLVDS data lines.

2 dacb_complement R/W 0 When asserted the output to the DACB is complemented. Thisallows to effectively change the + and – designations of theLVDS data lines.

1 clkdiv_sync_ena R/W Enables the syncing of the clock divider using the OSTR signalor the FRAME signal passed through the FIFO. This selection isdetermined by multi_sync_sel in register CONFIG19. Theinternal divided-down clocks will be phase aligned after syncing.See Power-Up Sequence section for more detail.

0 Unused R/W 0 Reserved for factory use.




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Figure 75. CONFIG19

7 6 5 4 3 2 1 0bequalsa aequalsb Reserved Unused Unused Unused multi_sync_sel rev


Table 28. CONFIG19 Field DescriptionsBit Field Type Reset Description7 bequalsa R/W 0 When asserted the DACA data is driven onto DACB.6 aequalsb R/W 0 When asserted the DACB data is driven onto DACA.5 Reserved R/W 0 Reserved for factory use.4 Unused R/W 0 Reserved for factory use.3 Unused R/W 0 Reserved for factory use.2 Unused R/W 0 Reserved for factory use.1 multi_sync_sel R/W 0 Selects the signal source for multiple device and clock divider

synchronization.multi_sync_sel Sync Source

0 OSTR1 FRAME through FIFO handoff

0 rev R/W 0 Reverse the input bits for the data word. MSB becomes LSB.

8.5.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)

Figure 76. CONFIG20

7 6 5 4 3 2 1 0qmc_offseta


Table 29. CONFIG20 Field DescriptionsBit Field Type Reset Description7:0 qmc_offseta R/W 0x00 Lower 8 bits of the DAC A offset correction. The offset is

measured in DAC LSBs. Writing this register causes anautosync to be generated. This loads the values of all fourqmc_offset registers (CONFIG20-CONFIG23) into the offsetblock at the same time. When updating the offset valuesCONFIG20 should be written last. Programming any of theother three registers will not affect the offset setting.


Figure 77. CONFIG21

7 6 5 4 3 2 1 0qmc_offsetb


Table 30. CONFIG21 Field DescriptionsBit Field Type Reset Description7:0 qmc_offsetb R/W 0x00 Lower 8 bits of the DAC B offset correction. The offset is

measured in DAC LSBs.




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Figure 78. CONFIG22

7 6 5 4 3 2 1 0qmc_offseta Unused Unused Unused


Table 31. CONFIG22 Field DescriptionsBit Field Type Reset Description7:3 qmc_offseta R/W 00000 Upper 5 bits of the DAC A offset correction.2 Unused R/W 0 Reserved for factory use.1 Unused R/W 0 Reserved for factory use.0 Unused R/W 0 Reserved for factory use.


Figure 79. CONFIG23

7 6 5 4 3 2 1 0qmc_offsetb(12:8) sif4_ena clkpath_sleep_ clkpath_sleep_

a bR/W R/W R/W R/W R/W R/W R/W R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. CONFIG23 Field DescriptionsBit Field Type Reset Description7:3 qmc_offsetb(12:8) R/W 00000 Upper 5 bits of the DAC B offset correction.2 sif4_ena R/W 0 When asserted the SIF interface becomes a 4 pin interface. The

ALARM pin is turned into a dedicated output for the reading ofdata.

1 clkpath_sleep_a R/W 0 When asserted puts the clock path through DAC A to sleep. Thisis useful for sleeping individual DACs. Even if the DAC is asleepthe clock needs to pass through it for the logic to work.However, if the chip is being put into a power down mode, thenall parts of the DAC can be turned off.

0 clkpath_sleep_b R/W 0 When asserted puts the clock path through DAC B to sleep.




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Figure 80. CONFIG24

7 6 5 4 3 2 1 0tsense_ena clkrecv_sleep Unused Reserved sleepb sleepa Reserved Reserved


Table 33. CONFIG24 Field DescriptionsBit Field Type Reset Description7 tsense_ena R/W 1 Turns on the temperature sensor when asserted.6 clkrecv_sleep R/W 0 When asserted the clock input receiver gets put into sleep

mode. This also affects the OSTR receiver.5 Unused R/W 0 Reserved for factory use.4 Reserved R/W 0 Reserved for factory use.3 sleepb R/W 0 When asserted DACB is put into sleep mode.2 sleepa R/W 0 When asserted DACA is put into sleep mode.1 Reserved R/W 1 Reserved for factory use.0 Reserved R/W 1 Reserved for factory use.


Figure 81. CONFIG25

7 6 5 4 3 2 1 0Reserved extref_ena Reserved Reserved


Table 34. CONFIG25 Field DescriptionsBit Field Type Reset Description7:3 Reserved R/W 00000 Turns on the temperature sensor when asserted.2 extref_ena R/W 0 Allows the device to use an external reference or the internal

reference. (0=internal, 1=external)1 Reserved R/W 0 Reserved for factory use.0 Reserved R/W 0 Reserved for factory use.

8.5.27 CONFIG26 (address = 0x1a) [reset = 0x00]

Figure 82. CONFIG26

7 6 5 4 3 2 1 0Reserved Reserved Unused Reserved


Table 35. CONFIG26 Field DescriptionsBit Field Type Reset Description7:6 Reserved R/W 00 Reserved for factory use.5:4 Reserved R/W 00 Reserved for factory use.3 Unused R/W 0 Reserved for factory use.

2:0 Reserved R/W 000 Reserved for factory use.




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8.5.28 CONFIG27 (address =0x1b) [reset = 0x00] (CAUSES AUTOSYNC)

Figure 83. CONFIG27

7 6 5 4 3 2 1 0qmc_gaina


Table 36. CONFIG27 Field DescriptionsBit Field Type Reset Description7:0 qmc_gaina R/W 0x00 Lower 8 bits of the 11-bit DAC A QMC gain word. The upper 3

bits are located in the CONFIG30 register. The full 11-bitqmc_gaina(10:0) value is formatted as UNSIGNED with a rangeof 0 to 1.9990 and a default gain of 1. The implied decimal pointfor the multiplication is between bits 9 and 10. Writing thisregister causes an autosync to be generated. This loads thevalues of all four qmc_phase/gain registers (CONFIG27-CONFIG30) into the QMC block at the same time. Whenupdating the QMC phase and/or gain values CONFIG27should be written last. Programming any of the other threeregisters will not affect the QMC settings.

8.5.29 CONFIG28 (address = 0x1C) [reset = 0x00]

Figure 84. CONFIG28

7 6 5 4 3 2 1 0gmc_gainb


Table 37. CONFIG28 Field DescriptionsBit Field Type Reset Description7:0 gmc_gainb R/W 0x00 Lower 8 bits of the 11-bit DAC B QMC gain word. The upper 3

bits are located in the CONFIG30 register. Refer to CONFIG27for formatting.

8.5.30 CONFIG29 (address = 0x1D) [reset = 0x00]

Figure 85. CONFIG29

7 6 5 4 3 2 1 0qmc_phase


Table 38. CONFIG29 Field DescriptionsBit Field Type Reset Description7:0 qmc_phase R/W 0x00 Lower 8-bits of the 10-bit QMC phase word. The upper 2 bits are

in the CONFIG30 register. The full 10-bit qmc_phase(9:0) wordis formatted as two's complement and scaled to occupy a rangeof –0.125 to 0.12475 (note this value does not correspond todegrees) and a default phase correction of 0. To accomplishQMC phase correction, this value is multiplied by the current 'Q'sample, then summed into the ‘I’ sample.




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8.5.31 CONFIG30 (address = 0x1E) [reset = 0x24]

Figure 86. CONFIG30

7 6 5 4 3 2 1 0qmc_phase(9:8) qmc_gaina(10:8) qmc_gainb(10:8)


Table 39. CONFIG30 Field DescriptionsBit Field Type Reset Description7:6 qmc_phase(9:8) R/W 00 Upper 2 bits of qmc_phase. Defaults to zero.5:3 qmc_gaina(10:8) R/W 100 Upper 3 bits of qmc_gaina. Defaults to unity gain.2:0 qmc_gainb(10:8) R/W 100 Upper 3 bits of qmc_gainb. Defaults to unity gain.

8.5.32 VERSION31 (address = 0x1F) [reset = 0x12] (PARTIAL READ ONLY)

Figure 87. VERSION31

7 6 5 4 3 2 1 0clk_alarm tx_off version(5:0)

R R R R R R R RLEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. VERSION31 Field DescriptionsBit Field Type Reset Description7 clk_alarm R 0 This bit is set to '1' when DATACLK is stopped for 4 clock

cycles. Once set, the bit needs to be cleared by writing a '0'.6 tx_off R 0 This bit is set to '1' when the clk_alarm is triggered. When set

the DAC outputs are forced to mid-level. Once set, the bit needsto be cleared by writing a '0'.

5:0 version(5:0) R 010010 A hardwired register that contains the version of the chip. (ReadOnly)




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Div

DATACLKP /N

FRAMEP/N

DAC-A

Q-F

IR1

CM

IX

I-F

IR1

Q-F

IR0

I-F

IR0

DA

CC

LK

P/N

DAC3283 DACFPGA

PFD/CP

CDCE62005

Clock Generator with VCO

VCON-Divider

R-Div

PFD

CPOUT

VCTRL_IN

900

TRF3720

AQM with PLL/VCO

LoopFilter

Div2/4/8

RF OUT

Op

tio

nal

Fil

ter

Ne

two

rk

LV

DS

Data

Inte

rface

LoopFilter

5V

D0P/N

D7P/N

Byte-Wide

Data

100

100

100

100

DAC-B

10 MHzOSC

Clock Divider/

Distribution

/1

Div

10

0

FIF

O&

De

mux

100

PLL/DLL

/4


9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe DAC3283 is appropriate for a variety of transmitter applications including complex I/Q direct conversion, up-conversion using an intermediate frequency (IF) and diversity applications.

9.2 Typical Application

Figure 88. System Diagram of Direct Conversion Radio

9.2.1 Design RequirementsFor this design example of a direct conversion transmitter, use the parameters in Table 41.

Table 41. Design ParametersPARAMETER VALUE

4x W-CDMA Carriers, each with 3.84 MHz bandwidthChannel Type (20 MHz total bandwidth)Input Data Rate 184.32 MSPS

Interpolation 4NCO Frequency Bypassed

Output IF None (Complex baseband)DAC Conversion Rate (DACCLK frequency) 737.28 MSPS




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9.2.2 Detailed Design Procedure

9.2.2.1 Direct Conversion RadioRefer to Figure 88 for an example Direct Conversion Radio. The DAC3283 receives an interleaved complex I/Qbaseband input data stream and increases the sample rate through interpolation by a factor of 2 or 4. Byperforming digital interpolation on the input data, undesired images of the original signal can be push out of theband of interest and more easily suppressed with analog filters.

For a Zero IF (ZIF) frequency plan, complex mixing of the baseband signal is not required. Alternatively, for aComplex IF frequency plan the input data can be pre-placed at an IF within the bandwidth limitations of theinterpolation filters. In addition, complex mixing is available using the coarse mixer block to up-convert the signal.The output of both DAC channels is used to produce a Hilbert transform pair and can be expressed as:

AOUT(t) = A(t)cos(ωct) – B(t)sin(ωct) = m(t) (1)

BOUT(t) = A(t)sin(ωct) + B(t)cos(ωct) = mh(t) (2)

where m(t) and mh(t) connote a Hilbert transform pair and ωc is the mixer frequency. The complex output is inputto an analog quadrature modulator (AQM) such as the Texas Instruments TRF3720 for a single side-band (SSB)up conversion to RF. A passive (resistor only) interface to the AQM with an optional LC filter network isrecommended. The TRF3720 includes a VCO/PLL to generate the LO frequency. Upper single-sidebandupconversion is achieved at the output of the analog quadrature modulator, whose output is expressed as:

RF(t) = A(t)cos(ωc + ωLO)t – B(t)sin(ωc + ωLO)t (3)

Flexibility is provided to the user by allowing for the selection of negative mixing frequency to produce a lower-sideband upconversion. Note that the process of complex mixing translates the signal frequency from 0Hzmeans that the analog quadrature modulator IQ imbalance produces a sideband that falls outside the signal ofinterest. DC offset error in DAC and AQM signal path may produce LO feed-through at the RF output which mayfall in the band of interest. To suppress the LO feed-through, the DAC3283 provides a digital offset correctioncapability for both DAC-A and DAC-B paths. In addition phase and gain imbalances in the DAC and AQM resultin a lower-sideband product. The DAC3283 offers gain and phase correction capabilities to minimize thesideband product.

The complex IF architecture has several advantages over the real IF architecture:• Uncalibrated side-band suppression ~ 35dBc compared to 0dBc for real IF architecture.• Direct DAC to AQM interface – no amplifiers required• DAC 2nd Nyquist zone image is offset fDAC compared with fDAC– 2 x IF for a real IF architecture, reducing the

need for filtering at the DAC output.• Uncalibrated LO feed through for AQM is ~ 35 dBc and calibration can reduce or completely remove the LO

feed through.




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A

Ref -19.6 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 153.6 MHz Span 65 MHz6.5 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

Tx Channel W-CDMA 3GPP FWD

Bandwidth 20 MHz Power -8.02 dBm

Adjacent Channel

Bandwidth 20 MHz Lower -73.41 dBSpacing 20.5 MHz Upper -73.54 dB

2x Interpolation, 0 dBFSf = 492.52 MSPS,

f = 153.6 MHzDAC

OUT

A

Ref -19 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 70 MHz Span 65 MHz6.5 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30



Adjacent Channel



f = 70 MHzDAC

OUT

A

Ref -17.4 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 70 MHz Span 35 MHz3.5 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20


Bandwidth 10 MHzPower -8.50 dBm

Adjacent Channel



f = 70 MHzDAC

OUT

A

Ref -17.9 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 153.6 MHz Span 35 MHz3.5 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20



Adjacent Channel



f = 153.6 MHzDAC

OUT

A

Ref -12.8 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 153.6 MHz Span 25.5 MHz2.55 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20


Bandwidth 3.84 MHz Power -8.07 dBm

Adjacent Channel

Bandwidth 3.84 MHz Lower -80.69 dBSpacing 5 MHz Upper -81.00 dB

Alternate Channel



f = 153.6 MHzDAC

OUT

A

Ref -12.3 dBm

*

*

*

CLRWR

RBW 30 kHz

VBW 300 kHz

SWT 10 sAtt 10 dB*

1 RM

NOR

*

Center 70 MHz Span 25.5 MHz2.55 MHz/

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20


Bandwidth 3.84 MHz Power -7.71 dBm

Adjacent Channel


Alternate Channel



f = 70 MHzDAC

OUT


9.2.3 Application Performance Plots

Figure 89. Single Carrier W-CDMA Test Model 1 Figure 90. Single Carrier W-CDMA Test Model 1

Figure 92. 10 MHz Single Carrier LTEFigure 91. 10 MHz Single Carrier LTE

Figure 93. 20 MHz Single Carrier LTE Figure 94. 20 MHz Single Carrier LTE




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10 Power Supply Recommendations

10.1 Power-up SequenceThe following startup sequence is recommended to power-up the DAC3283:1. Set TXENABLE low.2. Supply all 1.8V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD). The

1.8V and 3.3V supplies can be powered up simultaneously or in any order. There are no specificrequirements on the ramp rate for the supplies.

3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided afterthe SIF register programming.

4. Program all the SIF registers. Also program default value to the registers not being used.5. FIFO configuration needed for synchronization:

(a) Program fifo_reset_ena (config0, bit<5>) to enable FRAMEP/N as the FIFO input pointer sync source.(b) Program multi_sync_ena (config0, bit<4>) to enable syncing of the FIFO output pointer.(c) Program multi_sync_sel (config19, bit<1>) to select the FIFO output pointer and clock divider sync

source6. Clock divider configuration needed for synchronization:

(a) Program clkdiv_sync_ena(config18, bit<1>) to "1" to enable clock divider sync.7. Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N, and FRAMEP/N) simultaneously. Synchronize the FIFO

and clock divider by providing the pulse or periodic signals needed.(a) For Single Sync Source Mode where FRAMEP/N is used to sync the FIFO, a single rising edge for FIFO,

FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommendeddue to the non-deterministic latency of the sync signal through the clock domain transfer.

(b) For Dual Sync Sources Mode, either single pulse or periodic sync signals can be used.8. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed

for synchronization:(a) For Single Sync Source Mode where the clock divider sync source is FRAMEP/N, clock divider syncing

may be disabled after DAC3283 initialization and before the data transmission by settingclkdiv_sync_ena (config18, bit<1>) to “0”. This is to prevent accidental syncing of the clock divider whensending FRAMEP/N pulse to other digital blocks.

(b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTRP/N, the clockdivider syncing may be enabled at all time.

(c) Optionally, to prevent accidental syncing of the FIFO, disable FIFO syncing by setting fifo_reset_ena andmulti_sync_ena to "0" after the FIFO input and output pointers are initialized. If the FIFO sync remainsenabled after initialization, the FRAMEP/N pulse must occur in ways to not disturb the FIFO operation.Refer to the INPUT FIFO section for detail.

9. Enable transmit of data by asserting the TXENABLE pin.10. At all times, if any of the clocks (i.e. DATACLK or DACCLK) is lost or FIFO collision alarm is detected, a

complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat step 5 through 9.Program the FIFO configuration and clock divider configuration per step 5 and 6 appropriately to accept thenew sync pulse or pulses for the synchronization.




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11 Layout

11.1 Layout GuidelinesThe design of the PCB is critical to achieve the full performance of the DAC3283 device. Defining the PCBstackup should be the first step in the board design. Experience has shown that at least 6 layers are required toadequately route all required signals to and from the device. Each signal routing layer must have an adjacentsolid ground plane to control signal return paths to have minimal loop areas and to achieve controlledimpedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes tocontrol supply return paths. Minimizing the spacing between supply and ground planes improves performance byincreasing the distributed decoupling.

Although the DAC3283 device consists of both analog and digital circuitry, TI highly recommends solid groundplanes that encompass the device and its input and output signal paths. TI does not recommend split groundplanes that divide the analog and digital portions of the device. Split ground planes may improve performance if anearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split groundplanes are employed, one must carefully control the supply return paths and keep the paths on top of theirrespective ground reference planes.

Quality analog output signals and input conversion clock signal path layout is required for full dynamicperformance. Symmetry of the differential signal paths and discrete components in the path is mandatory andsymmetrical shunt-oriented components should have a common grounding via. The high frequency requirementsof the analog output and clock signal paths necessitate using differential routing with controlled impedances andminimizing signal path stubs (including vias) when possible.

Coupling onto or between the clock and output signal paths should be avoided using any isolation techniquesavailable including distance isolation, orientation planning to prevent field coupling of components like inductorsand transformers, and providing well coupled reference planes. Via stitching around the clock signal path and theinput analog signal path provides a quiet ground reference for the critical signal paths and reduces noisecoupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing onadjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at90 ° angles to minimize crosstalk.

The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of thehigh speed serial lanes. Affordable and common FR4 varieties are adequate in most cases.

Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and bymaintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used invery noisy environments and high dynamic range applications to isolate the signal path.




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11.2 Layout Example

Figure 95. Layout




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12 Device and Documentation Support

12.1 Documentation Support

12.2 TrademarksAll trademarks are the property of their respective owners.

12.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

DAC3283IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3283I

DAC3283IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3283I

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DAC3283IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

DAC3283IRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC3283IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6

DAC3283IRGZT VQFN RGZ 48 250 213.0 191.0 55.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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