D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling

DANDE CDH PDR ECEN 4610 Capstone Laboratory

Drag and Atmospheric Neutral Density Explorer

(DANDE)

Command and Data Handling(CDH)

Critical Design ReviewOctober 11th, 2007

Brandon Gilles (EE)James Gorman (ECE)Eric McIntyre (ECE)

Gabriel Thatcher (EE)


System Architecture Review

2


Overview of Current Status

Completed ‘Meter-Stones’– 8-bit board ordered.– New Linux Kernel running.– I2C driver compiled, loaded, and O-scope tested.– 32-bit board up and running with new Kernel.– Software Use Cases and Software Requirements

(SRS) Specification • Fully defined • Approved by DANDE management.


Overview of Current Status

In the Works– 8-bit board assembly and test.– 8-bit software architecture.

• Library support package• Bus-messaging driver

– 32-bit software modeling • Architecture, Object, and Sequence Models

Needs Attention– Watchdog Circuitry


HardwareSubsystems


Subsystem Schematics

1 2

Y1 32.768K

GND

Optional SPI

I2C

A5 1A6 2A7 3A8 4A9 5A10 6

A117

A128

A139

A1410

I/O011

I/O112

I/O213

I/O315

I/O416

I/O517

I/O618

I/O719

CE 20

A021

OE 22

A123

A2 24A3 25A4 26

WE 27

GND14 VCC 28

U3

CY62256LL-70SNC

OE1

D12

D23

D34

D45

D56

D67

D78

D89

GND10

LE11

Q8 12Q7 13Q6 14Q5 15Q4 16Q3 17Q2 18Q1 19

VCC 20U4

SN74AHC573DW

~WR~RDALE

ALE

~RD

AD0AD1AD2AD3AD4

AD6AD5

AD7

AD0AD1AD2AD3AD4

AD6AD5

AD7

VCC

A0A1A2A3A4

A6A5

A7

A8A9A10A11A12A13A14A15

A0A1

A14A13A12A11

A2A3A4A5A6A7A8A9A10

GND

GND

~WR

Optional UART1

UART0

428-1083-NDGND

VCC

SCLSDA

1 23 45 6

ISP

ISP Header 3X2

GND

VCC

~RESET2

~RESET2SCKP_MISO

P_MOSI

SCK

P_MOSIP_MISO

MOSI

/CS

DANDE Subsystem Reference Design

1 1James Gorman

PEN1

PE0 (RXD0/PDI)2

PE1 (TXD0/PDO)3

PE2 (XCK0/AIN0)4

PE3 (OC3A/AIN1)5

PE4 (OC3B/INT4)6

PE5 (OC3C/INT5)7

PE6 (T3/INT6)8

PE7 (IC3/INT7)9

PB0 (SS)10

PB1 (SCK)11

PB2 (MOSI)12

PB3 (MISO)13

PB4 (OC0)14

PB5 (OC1A)15

PB6 (OC1B)16

PB7 (OC2/OC1C)17

TOSC2/PG318

TOSC1/1PG419

RESET20

VCC 21

GND 22

XTAL223

XTAL124

PD0 (SCL/INT0)25

PD1 (SDA/INT1)26

PD2 (RXD1/INT2)27

PD3 (TXD1/INT3)28

PD4 (IC1)29

PD5 (XCK1)30

PD6 (T1)31

PD7 (T2)32

PG0 (WR)33

PG1 (RD)34

PC0 (A8) 35

PC1 (A9) 36

PC2 (A10) 37

PC3 (A11) 38

PC4 (A12) 39

PC5 (A13) 40

PC6 (A14) 41

PC7 (A15) 42

PG2 (ALE)43

PA7 (AD7) 44PA6 (AD6) 45PA5 (AD5) 46PA4 (AD4) 47PA3 (AD3) 48PA2 (AD2) 49PA1 (AD1) 50PA0 (AD0) 51

VCC 52

GND 53

PF7 (ADC7/TDI) 54

PF6 (ADC6/TDO) 55

PF5 (ADC5/TMS) 56

PF4 (ADC4/TCK) 57

PF3 (ADC3) 58

PF2 (ADC2) 59

PF1 (ADC1) 60

PF0 (ADC0) 61

AREF 62

GND 63

AVCC 64

AVR

ATmega128-16AI

VCC

1 2

XTAL????

Optional External SRAM

MISO

AVR Decoupling Caps

GND GND GND

VCCVCCVCC

100nFC10

100nFC11

100nFC12

GND

VCC

100nFC17

GND

VCCSRAM

GND

VCC

100nFC18

100nFC19

573 Latch 7404

Decoupling Capacitors????

C21Cap

????

C22Cap

GNDGND

Optional Analog Inputs

12

P1

Header 2

GND

VCC

123456

P6

PORT E 2:7

1234

P5

PORT D 4:7

1234

P4

PORT B 4:7

Optional Digital I/O

Optional Digital I/O

1234

P7

SPI

GND

VCC

10uFC13

Board

I2C (TWI)

RX0TX0

RX1TX1

Reset

12345678

P8

PORT F 0:7

GND

VCC

SCLSDA

12

P15

I2C

12

P18

I2C

12

P17

I2C

12

P16

I2C

4.7KR4

4.7KR3

4.7KR2

4.7KR1

VCC VCC

123

P3

Sx 1Rx2

Tx3

GND 4Ty5 Ry6 Sy 7

Vcc 8

U6

GND

VCCP82B96

100nFC16

12345678

P21

A0:7

12345678

P22

A8:15

12345678

P23

AD0:7

AD0

AD2AD3AD4

AD6AD5

AD7

AD1A0A1A2A3A4

A6A5

A7

A8A9A10A11A12A13A14A15

1 2

U8A

SNJ54AHC04W


Subsystem Schematics

14

11

12

9

13

10

15

8

C1+2

C2+5

GND16

C1-4

VCC17

R1

T1

T2

R2

C2-6

V-7

V+3

NC1

SHDN18

U10

MAX222EWN

100nFC31

100nFC32

100nFC33

VCC

100nF

C34

GND

100nFC30

GND

VCCMAX222

IN1

2

OUT3

GND

4

VR1LM2937IMP-5

GND

VCC

100nFC1

D1

MBRA140T310uFC2

12

P10

Header 2

Optional Power Regulator

FOR FLAT SAT ONLY

TX0TX1

RX0

RX1

1

2

3

4

5

6

7

8

9

11

10

J12

D Connector 9

GND

123

P13

Header 3

123

P14

Header 3

1

2

3

4

5

6

7

8

9

11

10

J11

D Connector 9

GND

~RESET123

P12Header 3

123

P11Header 3

GND

100nFC40

S1Reset

~RESETReset

12345678

P20

LEDS

D11

1KR211KR221KR231KR241KR251KR261KR271KR28

GND

23

1

SW1

SW-SPDT

D12

D13

D14

D15

D16

D17

D18

D21

D22

D23

D24

D25

D26

D27

D28

VCCD2

VCC

1KR11

GND

3 4

U8B

SNJ54AHC04W

5 6

U8C

SNJ54AHC04W

89

U8D

SNJ54AHC04W

1011

U8E

SNJ54AHC04W

1213

U8F

SNJ54AHC04W

12

P24

Header 2

12

P25

Header 2

12

P26

Header 2

12

P27

Header 2

12

P28

Header 2


Subsystem Board Overview


Subsystem Board Overview


Subsystem Board Visualization


Subsystem Board Visualization


HardwareCentral Processor


32-bit Board

• Build or Buy Decision: Buy

Atmel NGW100 Reference Design ~ $80


Why?

• Software Development Schedule• Man-hours desperately needed• Already hard-pressed to finish software

• Cost-Benefit Analysis• NGW100 meets most requirements• Large development time and cost

• Atmel needed 8-layers to implement NGW100• 256-ping BGA package


Software


Software Development Cycle

• Use-cases• Requirements Definitions • Requirements Approval• Architectural Support• Object Model• Sequence Model• Buildable Stub• Iterative Testing• Final Implementation

Completed – 9/15Completed – 9/24Completed – 10/1~CompletedIn ProgressIn ProgressIn ProgressNot StartedNot Started


32-bit Software Architecture


Data Flows

Housekeeping DataScience Data


Subsystem Communication

• I2C link to subsystems• Standardized Transmission Format across all subsystems• Communication done through Bus Messenger via IPC


Boot-Up Sequence


Project Goals


Project Goals

Milestone 1 Goals• Subsystem board and support code complete• Software analysis complete

– Architecture Support– Object Model– Sequence Model

• Stub of 32-bit software compiledMilestone 2 Goals• 32-bit Software

– 80% functionality based on SRS– Test iteration 2 of 4 complete

• 8-bit to 32-bit integration complete


Project Goals

Open-Lab Expo• 32-bit software

– 100% functionality based on SRS– Test iteration 4 of 4 complete

• 8-bit to 32-bit communication at 100%• Demo of Mach Satellite Operation

– Central Processor– Two Subsystems– Intercommunication and Control


Current Division of Labor

• Brandon Gilles– Project Manager– REA - Linux Kernel– REA - 32-bit Hardware

• James Gorman– REA - 8-bit Hardware and Software

Reference Design– REA - Watch Dog and Long Dog

Circuitry

24

Across the board32-bit Software Analysis, Design and Implementation

• Eric McIntyre– REA - 32-bit Software

– Architecture– Analysis and Design– Implementation

• Gabriel Thatcher– REA - Memory Voting Logic– REA - Subsystem Hardware

Interfacing

REA - Responsible Engineering Authority

Time Permitting

De-Scope


Backup Slides


Parts List Overview

What we have• 3 NGW100s

– Central Processor Boards • 2 STK500s

– Subsystem Programming Boards

What we Need• 2 Subsystem Boards (arriving today)

– Reference Design for subsystem Developers


Detailed Parts List

Comment Description Designator Footprint LibRef Quantity

ATmega128-16AI 8-Bit AVR Microcontroller with 128K Bytes of In-System Programmable Flash Memory AVR 64A_L ATmega128-16AI 1

Cap Semi Capacitor (Semiconductor SIM Model) .1uF C1, C10, C11, C12, C16, C17, C18, C19, C30, C31, C32, C33, C34, C40 1608[0603] Cap Semi 14

Cap Semi Capacitor (Semiconductor SIM Model) 1uF C13 1608[0603] Cap Semi 1

Cap Pol1 Polarized Capacitor (Radial) 10 uF C2 A Cap Pol1 1

Cap Oscillator Capacitor C21, C22 VP32-3.2 Cap 2

MBRA140T3 Schottky Diode D1 SMA MBRA140T3 1

LED2 High Brightness Red LED D2, D11, D12, D13, D14, D15, D16, D17, D18 3216[1206] LED2 9

LED2 High Brightness Blue LED D21, D22, D23, D24, D25, D26, D27, D28 3216[1206] LED2 8

Diode 1N4001 1 Amp General Purpose Rectifier D33, D34, D35 DO-41 Diode 1N4001 3

D Connector 9 Receptacle Assembly, 9 Position, Right Angle J11, J 12 DSUB1.385-2H9 D Connector 9 2

Header 2 Header, 2-Pin P1, P10, P15, P16, P17, P18, P24, P25 HDR1X2 Header 2 8

Header 3 Header, 3-Pin P3, P11, P12, P13, P14 HDR1X3 Header 3 5

Header 4 Header, 4-Pin P4, P5, P7 HDR1X4 Header 4 3

Header 6 Header, 6-Pin P6 HDR1X6 Header 6 1

Header 8 Header, 8-Pin P23, P22, P21, P20, P8 HDR1X8 Header 8 5

Header 3X2 Header, 3-Pin, Dual row P26, ISP HDR2X3 Header 3X2 2

Res3 Resistor 4.7k R1, R2, R3, R4 J1-0603 Res3 4

Res3 Resistor 430ohm R11, R21, R22, R23, R24, R25, R26, R27, R28 J1-0603 Res3 9

Reset Switch S1 Pushbutton SW-PB 1

SW-SPDT SPDT Subminiature Toggle Switch, Right Angle Mounting, Vertical Actuation SW1 SIP3 SW-SPDT 1

CY62256LL-55SNI 32K x 8 Static RAM U3 S22_M CY62256LL-70SNC 1

SN74AHC573DW Octal Transparent D-Type Latch with 3-State Outputs U4 DW020_M SN74AHC573DW 1

P82B96D I2C Bus Isolator U6 SOIC150-8_M P82B96 1

SN74ACH04D Hex Inverter U8 D014_N SNJ 54AHC04W 1

MAX222EWN +5V-Powered, Multichannel RS-232 Driver/Receiver U10 WSO18_N MAX222EWN 1

LM2937IMP-5 500 mA Low-Dropout Regulator VR1 TS3B LM2937ES-5.0 1

???? Crystal Oscillator XTAL XTAL XTAL 1


Schedule

Project Schedule.rmp


32-bit Schematics


32-bit Schematics


Exploded Satellite View

DANDE CDH PDR ECEN 4610 Capstone Laboratory 32

Functional Block Diagram

ACC

Control

AccAcc

Acc

Acc

AccAcc

THM

Control

Coatings, Insulation

Sensors

InstrumentNMS

Control

Instrument

FOV32° x 1°

Instrument

FOV 32° x 1°

CDH

I2C I/O

CPUAVR32

RAM TBD

SSDTBDRTC

SFTOS

Scheduling

Comm

ADCS

Science

Serial I/O

Wiring Harness

SEP

Mech1

Mech2

Control

Ligh

tban

d as

sy.

ABS

EPS Photovoltaics 30W

BatteryB

14.4V 4AH

Regulation Control

FOV360°

Inhibit

Inhibit

x4

x4

Battery A14.4V 4AH

LV e

lect

rical

in

terfa

ceSa

tellit

e Se

p Pl

ane

(SSP

) COM

Tx AntRx Ant

FOV90°

FOV90°

Tx70cm

38.4kbps

Rx2m

9.6kbps

TNC

ACC

Control

AccAcc

Acc

Acc

AccAcc

ADC

Control

Horizon Crossin

g Sensor

Torquerod A

Horizon Crossin

g Sensor

Torquerod AMag (3-

axis)

FOV 2°FOV 2°

InstrumentNMS

Control

Instrument

FOV32° x 1°

Instrument

FOV 32° x 1°

ADC

Control

Horizon Crossin

g Sensor

Torquerod A

Horizon Crossin

g Sensor

Torquerod AMag (3-

axis)

FOV 2°FOV 2°

THM

Control

Coatings, Insulation

Sensors

CDH

I2C I/O

CPUAVR32

RAM TBD

SSDTBDRTC

SFTOS

Scheduling

Comm

ADCS

Science

Serial I/O

EPS Photovoltaics 30W

BatteryB

14.4V 4AH

Regulation Control

FOV360°

Inhibit

Inhibit

x4

x4

Battery A14.4V 4AH

LV e

lect

rical

in

terfa

ceSa

tellit

e Se

p Pl

ane

(SSP

) COM

Tx AntRx Ant

FOV90°

FOV90°

Tx70cm

38.4kbps

Rx2m

9.6kbps

TNC

SEP

Mech1

Mech2

Control

Ligh

tban

d as

sy.

ABS

Documents

D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling