Curtis Mayberry EE435 Lab 6

Two Stage Differential Amplifier

Building a two-stage differential amplifier can achieve a much higher gain through the cascade of two

amplifiers, a single ended differential amplifier and a common source amplifier. The other performance

criteria remained the same as the single stage differential criteria. However stability criteria were

specified to account for the need to stabilize the system that now has two poles.

Specifications for the amplifier:

Vdd=-Vss=2.5V

Total Power<1 mW (Opamp part)

Slew Rate: SR≥30V/us

DC Gain ≥ 75dB

Gain Bandwidth Product (GBW) ≥ 25MHz

Linear Output Swing Range: Vss+0.2V≤Vout≤Vdd-0.3V

CMRR≥100dB

Input Common Mode Range (ICMR): ICMR≥50%×(Vdd-Vss)

Maximum overshoot for 0.1 V step response <25%

Settling time in 0.5 V step response in unity feedback: <= 100 nS for +– 0.1%.

CL=2pF The amplifier schematic is shown in figure 1.

Design The architecture of the amplifier uses a basic differential amplifier with PMOS input and a single ended

output along with a common source second stage. It also includes miller compensation between the

first and second stage. The schematic of the design is shown in figure 1.

Figure 1: 2 stage amplifier schematic

Also the Vdd dependent current source, along with voltage generation circuits, was used to bias the

amplifier current source transistors, M6 and M7. The biasing circuitry is shown in figure 2.

Figure 2: Voltage biasing circuitry

The design was started by making some assumptions and decisions about the transistor length. The

current mirror transistors M6 and M7 were given a length of 2 *Lmin and an excess bias of

in order to insure good current mirror accuracy. All other transistors were given a length of L =

1.5*Lmin and an excess bias of

Next the power and current of each stage were budgeted. The currents’ upper limits were calculated

using the total power and the lower limits of the current were calculated using the skew rate. Before

the power could be budgeted, however, the capacitances of the design needed to be computed,

specifically the miller compensation transistor value needed to be determined. This value can be

determined by placing the zero and second pole appropriately.

Upper Current Limits Total maximum amplifier power = 1mW

Lower Current Limits

Next the transistor sizing was chosen using the selected excess bias and the selected currents.

Implementation After the design was drawn the sizing needed to be adjusted in order to insure all transistors were in

saturation and the amplifier’s requirements are meet. The currents in each branch needed to be

adjusted to meet the slew rate and gain requirements of the amplifier. A resistor was added in series

with the Miller compensation in order to improve the stability and consequently decrease the overshoot

of the amplifier. The final sizing and component values after tuning:

Biasing circuit’s sizing and component values:

Testing and Verification

Total Power The power requirement of dissipating under 1 mW was meet.

Slew Rate The slew rate was tested using the circuit shown in figure 3. The amplifier was put into a unity gain

buffer configuration and a large step from -2.5v to 2.5v was input to the amplifier. The slope of the

output’s resulting response was found by running a transient analysis simulation. The results for the

rising and falling edge, SR+ and SR- were found to be 30v/µs as shown in figures 4 and 5 respectively.

This meet the specified requirement of 30v/µs.

Figure 3: Circuit for measuring slew rate

Figure 4: plot of the rising edge slew rate

Figure 5: plot of the falling edge slew rate

DC Gain and Gain-bandwidth product The gain of the amplifier was measured to be 87.41 dB at DC. The bandwidth was found to be 1.233

kHz. The gain bandwidth product was estimated by finding the unity gain frequency at 25.24 MHz. Each

of these measurements is outlined in figure 6. Both the DC gain and gain-bandwidth product meet their

requirements of 75 dB and 25 MHz respectively.

Figure 6: Gain bode plot highlighting the DC gain, bandwidth and unity gain frequency (GB): A is the

total gain, A1 is the first stage gain and A2 is the second stage gain

Linear Output Swing Range Next the linear output swing range was measured using a closed loop inverting amplifier configuration

as shown in figure X. The linear output swing range was found to be:

This exceeds the required -2.3v ≤ Vout ≤ 2.2v output swing. The circuit used to find the output swing range is given in figure 7 and a plot of the output swing range is given in figure 8.

Figure 7: Circuit for measuring output swing range

Figure 8: Plot of output swing range

CMRR CMRR≥100dB The common mode rejection ratio is found using the circuit in figure 9 to find the common mode gain and then using this value along with the differential DC gain found previously. The common mode DC gain was found as shown in figure 10 to be-35.75 dB. Hence the common mode rejection ratio is given as:

Figure 9: Circuit for measuring the common mode gain.

Figure 10: Common mode gain bode plot

ICMR Next the input common mode range was found using the circuit shown in figure 11. The ICMR was

found to be 3.137 v over the range of -2.014v<Vicm<1.123v as shown in figure 12.

Figure 11: ICMR measurement circuit

Figure 12: Input Common Mode Range

Stability The stability of the system was measured in the time domain using two separate measures. The first is

the maximum overshoot of a 0.1v step response. The second is the settling time on a o.5v step

response at unity feedback. Both characteristics were measured using the circuit shown in figure 13,

with the input step voltage properly adjusted for the test being examined. The overshoot was found to

be 19% as shown in figure 14 and the settling time was found to be 74.22ns as shown in figure 15.

Figure 13: Circuit for measuring the overshoot and settling time

Figure 14: Transient analysis plot highlighting the overshoot.

Figure 15: Transient analysis plot verifying the settling time

Conclusion The design of the two stage differential amplifier has been shown to successfully meet the performance

criteria. The amplifier design was the first amplifier to consider stability issues. The stability of the

amplifier was insured using Miller compensation and a compensating resistor. Once the performance

criteria were meet, there was little in the way of improving the design to reduce the area. Since many of

the specifications are over designed and exceed their requirement, some performance may be sacrificed

in order to reduce cost while still meeting the requirements.